board/ti/ks2_evm/board_k2l.c

   1 /*
   2  * K2L EVM : Board initialization
   3  *
   4  * (C) Copyright 2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/ddr3.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/ti-common/keystone_net.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 unsigned int external_clk[ext_clk_count] = {
  18         [sys_clk]       = 122880000,
  19         [alt_core_clk]  = 100000000,
  20         [pa_clk]        = 122880000,
  21         [tetris_clk]    = 122880000,
  22         [ddr3_clk]      = 100000000,
  23         [pcie_clk]      = 100000000,
  24         [sgmii_clk]     = 156250000,
  25         [usb_clk]       = 100000000,
  26 };
  27
  28 static struct pll_init_data core_pll_config[] = {
  29         CORE_PLL_799,
  30         CORE_PLL_1000,
  31         CORE_PLL_1198,
  32 };
  33
  34 s16 divn_val[16] = {
  35         0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  36 };
  37
  38 static struct pll_init_data tetris_pll_config[] = {
  39         TETRIS_PLL_799,
  40         TETRIS_PLL_1000,
  41         TETRIS_PLL_1198,
  42         TETRIS_PLL_1352,
  43         TETRIS_PLL_1401,
  44 };
  45
  46 static struct pll_init_data pa_pll_config =
  47         PASS_PLL_983;
  48
  49 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  50 struct eth_priv_t eth_priv_cfg[] = {
  51         {
  52                 .int_name        = "K2L_EMAC",
  53                 .rx_flow         = 0,
  54                 .phy_addr        = 0,
  55                 .slave_port      = 1,
  56                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  57         },
  58         {
  59                 .int_name        = "K2L_EMAC1",
  60                 .rx_flow         = 8,
  61                 .phy_addr        = 1,
  62                 .slave_port      = 2,
  63                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  64         },
  65         {
  66                 .int_name        = "K2L_EMAC2",
  67                 .rx_flow         = 16,
  68                 .phy_addr        = 2,
  69                 .slave_port      = 3,
  70                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  71         },
  72         {
  73                 .int_name        = "K2L_EMAC3",
  74                 .rx_flow         = 32,
  75                 .phy_addr        = 3,
  76                 .slave_port      = 4,
  77                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  78         },
  79 };
  80
  81 int get_num_eth_ports(void)
  82 {
  83         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
  84 }
  85 #endif
  86
  87 #ifdef CONFIG_BOARD_EARLY_INIT_F
  88 int board_early_init_f(void)
  89 {
  90         int speed;
  91
  92         speed = get_max_dev_speed();
  93         init_pll(&core_pll_config[speed]);
  94
  95         init_pll(&pa_pll_config);
  96
  97         speed = get_max_arm_speed();
  98         init_pll(&tetris_pll_config[speed]);
  99
 100         return 0;
 101 }
 102 #endif
 103
 104 #ifdef CONFIG_SPL_BUILD
 105 static struct pll_init_data spl_pll_config[] = {
 106         CORE_PLL_799,
 107         TETRIS_PLL_491,
 108 };
 109
 110 void spl_init_keystone_plls(void)
 111 {
 112         init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
 113 }
 114 #endif