board/ti/ks2_evm/board_k2l.c

   1 /*
   2  * K2L EVM : Board initialization
   3  *
   4  * (C) Copyright 2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/ddr3.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/ti-common/keystone_net.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 unsigned int external_clk[ext_clk_count] = {
  18         [sys_clk]       = 122880000,
  19         [alt_core_clk]  = 100000000,
  20         [pa_clk]        = 122880000,
  21         [tetris_clk]    = 122880000,
  22         [ddr3_clk]      = 100000000,
  23         [pcie_clk]      = 100000000,
  24         [sgmii_clk]     = 156250000,
  25         [usb_clk]       = 100000000,
  26 };
  27
  28 static struct pll_init_data core_pll_config[] = {
  29         CORE_PLL_799,
  30         CORE_PLL_1000,
  31         CORE_PLL_1198,
  32 };
  33
  34 static struct pll_init_data tetris_pll_config[] = {
  35         TETRIS_PLL_799,
  36         TETRIS_PLL_1000,
  37         TETRIS_PLL_1198,
  38         TETRIS_PLL_1352,
  39         TETRIS_PLL_1401,
  40 };
  41
  42 static struct pll_init_data pa_pll_config =
  43         PASS_PLL_983;
  44
  45 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  46 struct eth_priv_t eth_priv_cfg[] = {
  47         {
  48                 .int_name        = "K2L_EMAC",
  49                 .rx_flow         = 0,
  50                 .phy_addr        = 0,
  51                 .slave_port      = 1,
  52                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  53         },
  54         {
  55                 .int_name        = "K2L_EMAC1",
  56                 .rx_flow         = 8,
  57                 .phy_addr        = 1,
  58                 .slave_port      = 2,
  59                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  60         },
  61         {
  62                 .int_name        = "K2L_EMAC2",
  63                 .rx_flow         = 16,
  64                 .phy_addr        = 2,
  65                 .slave_port      = 3,
  66                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  67         },
  68         {
  69                 .int_name        = "K2L_EMAC3",
  70                 .rx_flow         = 32,
  71                 .phy_addr        = 3,
  72                 .slave_port      = 4,
  73                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  74         },
  75 };
  76
  77 int get_num_eth_ports(void)
  78 {
  79         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
  80 }
  81 #endif
  82
  83 #ifdef CONFIG_BOARD_EARLY_INIT_F
  84 int board_early_init_f(void)
  85 {
  86         int speed;
  87
  88         speed = get_max_dev_speed();
  89         init_pll(&core_pll_config[speed]);
  90
  91         init_pll(&pa_pll_config);
  92
  93         speed = get_max_arm_speed();
  94         init_pll(&tetris_pll_config[speed]);
  95
  96         return 0;
  97 }
  98 #endif
  99
 100 #ifdef CONFIG_SPL_BUILD
 101 static struct pll_init_data spl_pll_config[] = {
 102         CORE_PLL_799,
 103         TETRIS_PLL_491,
 104 };
 105
 106 void spl_init_keystone_plls(void)
 107 {
 108         init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
 109 }
 110 #endif