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1 /*
2  * (C) Copyright 2010
3  * Texas Instruments Incorporated, <www.ti.com>
4  * Steve Sakoman  <steve@sakoman.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 #include <common.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/clocks.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/gpio.h>
30
31 #include "panda_mux_data.h"
32
33 #ifdef CONFIG_USB_EHCI
34 #include <usb.h>
35 #include <asm/arch/ehci.h>
36 #include <asm/ehci-omap.h>
37 #endif
38
39 #define PANDA_ULPI_PHY_TYPE_GPIO       182
40
41 DECLARE_GLOBAL_DATA_PTR;
42
43 const struct omap_sysinfo sysinfo = {
44         "Board: OMAP4 Panda\n"
45 };
46
47 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
48
49 /**
50  * @brief board_init
51  *
52  * @return 0
53  */
54 int board_init(void)
55 {
56         gpmc_init();
57
58         gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
59         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
60
61         return 0;
62 }
63
64 int board_eth_init(bd_t *bis)
65 {
66         return 0;
67 }
68
69 /**
70  * @brief misc_init_r - Configure Panda board specific configurations
71  * such as power configurations, ethernet initialization as phase2 of
72  * boot sequence
73  *
74  * @return 0
75  */
76 int misc_init_r(void)
77 {
78         int phy_type;
79         u32 auxclk, altclksrc;
80
81         /* EHCI is not supported on ES1.0 */
82         if (omap_revision() == OMAP4430_ES1_0)
83                 return 0;
84
85 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
86         if (omap_revision() >= OMAP4460_ES1_0 ||
87                 omap_revision() <= OMAP4460_ES1_1)
88                 setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
89 #endif
90
91         gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
92         phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
93
94         if (phy_type == 1) {
95                 /* ULPI PHY supplied by auxclk3 derived from sys_clk */
96                 debug("ULPI PHY supplied by auxclk3\n");
97
98                 auxclk = readl(&scrm->auxclk3);
99                 /* Select sys_clk */
100                 auxclk &= ~AUXCLK_SRCSELECT_MASK;
101                 auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
102                 /* Set the divisor to 2 */
103                 auxclk &= ~AUXCLK_CLKDIV_MASK;
104                 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
105                 /* Request auxilary clock #3 */
106                 auxclk |= AUXCLK_ENABLE_MASK;
107
108                 writel(auxclk, &scrm->auxclk3);
109        } else {
110                 /* ULPI PHY supplied by auxclk1 derived from PER dpll */
111                 debug("ULPI PHY supplied by auxclk1\n");
112
113                 auxclk = readl(&scrm->auxclk1);
114                 /* Select per DPLL */
115                 auxclk &= ~AUXCLK_SRCSELECT_MASK;
116                 auxclk |=  AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
117                 /* Set the divisor to 16 */
118                 auxclk &= ~AUXCLK_CLKDIV_MASK;
119                 auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
120                 /* Request auxilary clock #3 */
121                 auxclk |= AUXCLK_ENABLE_MASK;
122
123                 writel(auxclk, &scrm->auxclk1);
124         }
125
126         altclksrc = readl(&scrm->altclksrc);
127
128         /* Activate alternate system clock supplier */
129         altclksrc &= ~ALTCLKSRC_MODE_MASK;
130         altclksrc |= ALTCLKSRC_MODE_ACTIVE;
131
132         /* enable clocks */
133         altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
134
135         writel(altclksrc, &scrm->altclksrc);
136
137         return 0;
138 }
139
140 void set_muxconf_regs_essential(void)
141 {
142         do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
143                    sizeof(core_padconf_array_essential) /
144                    sizeof(struct pad_conf_entry));
145
146         do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
147                    sizeof(wkup_padconf_array_essential) /
148                    sizeof(struct pad_conf_entry));
149
150         if (omap_revision() >= OMAP4460_ES1_0)
151                 do_set_mux(CONTROL_PADCONF_WKUP,
152                                  wkup_padconf_array_essential_4460,
153                                  sizeof(wkup_padconf_array_essential_4460) /
154                                  sizeof(struct pad_conf_entry));
155 }
156
157 void set_muxconf_regs_non_essential(void)
158 {
159         do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
160                    sizeof(core_padconf_array_non_essential) /
161                    sizeof(struct pad_conf_entry));
162
163         if (omap_revision() < OMAP4460_ES1_0)
164                 do_set_mux(CONTROL_PADCONF_CORE,
165                                 core_padconf_array_non_essential_4430,
166                                 sizeof(core_padconf_array_non_essential_4430) /
167                                 sizeof(struct pad_conf_entry));
168         else
169                 do_set_mux(CONTROL_PADCONF_CORE,
170                                 core_padconf_array_non_essential_4460,
171                                 sizeof(core_padconf_array_non_essential_4460) /
172                                 sizeof(struct pad_conf_entry));
173
174         do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
175                    sizeof(wkup_padconf_array_non_essential) /
176                    sizeof(struct pad_conf_entry));
177
178         if (omap_revision() < OMAP4460_ES1_0)
179                 do_set_mux(CONTROL_PADCONF_WKUP,
180                                 wkup_padconf_array_non_essential_4430,
181                                 sizeof(wkup_padconf_array_non_essential_4430) /
182                                 sizeof(struct pad_conf_entry));
183 }
184
185 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
186 int board_mmc_init(bd_t *bis)
187 {
188         return omap_mmc_init(0, 0, 0, -1, -1);
189 }
190 #endif
191
192 #ifdef CONFIG_USB_EHCI
193
194 static struct omap_usbhs_board_data usbhs_bdata = {
195         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
196         .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
197         .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
198 };
199
200 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
201 {
202         int ret;
203         unsigned int utmi_clk;
204
205         /* Now we can enable our port clocks */
206         utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
207         utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
208         sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
209
210         ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
211         if (ret < 0)
212                 return ret;
213
214         return 0;
215 }
216
217 int ehci_hcd_stop(int index)
218 {
219         return omap_ehci_hcd_stop();
220 }
221 #endif
222
223 /*
224  * get_board_rev() - get board revision
225  */
226 u32 get_board_rev(void)
227 {
228         return 0x20;
229 }