board/ti/ti814x/evm.c

   1 /*
   2  * evm.c
   3  *
   4  * Board functions for TI814x EVM
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <cpsw.h>
  21 #include <errno.h>
  22 #include <spl.h>
  23 #include <asm/arch/cpu.h>
  24 #include <asm/arch/hardware.h>
  25 #include <asm/arch/omap.h>
  26 #include <asm/arch/ddr_defs.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/gpio.h>
  29 #include <asm/arch/mmc_host_def.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <asm/io.h>
  32 #include <asm/emif.h>
  33 #include <asm/gpio.h>
  34 #include "evm.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #ifdef CONFIG_SPL_BUILD
  39 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  40 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  41 #endif
  42
  43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  44
  45 /* UART Defines */
  46 #ifdef CONFIG_SPL_BUILD
  47 #define UART_RESET              (0x1 << 1)
  48 #define UART_CLK_RUNNING_MASK   0x1
  49 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
  50
  51 static void rtc32k_enable(void)
  52 {
  53         struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
  54
  55         /*
  56          * Unlock the RTC's registers.  For more details please see the
  57          * RTC_SS section of the TRM.  In order to unlock we need to
  58          * write these specific values (keys) in this order.
  59          */
  60         writel(0x83e70b13, &rtc->kick0r);
  61         writel(0x95a4f1e0, &rtc->kick1r);
  62
  63         /* Enable the RTC 32K OSC by setting bits 3 and 6. */
  64         writel((1 << 3) | (1 << 6), &rtc->osc);
  65 }
  66
  67 static void uart_enable(void)
  68 {
  69         u32 regVal;
  70
  71         /* UART softreset */
  72         regVal = readl(&uart_base->uartsyscfg);
  73         regVal |= UART_RESET;
  74         writel(regVal, &uart_base->uartsyscfg);
  75         while ((readl(&uart_base->uartsyssts) &
  76                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
  77                 ;
  78
  79         /* Disable smart idle */
  80         regVal = readl(&uart_base->uartsyscfg);
  81         regVal |= UART_SMART_IDLE_EN;
  82         writel(regVal, &uart_base->uartsyscfg);
  83 }
  84
  85 static void wdt_disable(void)
  86 {
  87         writel(0xAAAA, &wdtimer->wdtwspr);
  88         while (readl(&wdtimer->wdtwwps) != 0x0)
  89                 ;
  90         writel(0x5555, &wdtimer->wdtwspr);
  91         while (readl(&wdtimer->wdtwwps) != 0x0)
  92                 ;
  93 }
  94
  95 static const struct cmd_control evm_ddr2_cctrl_data = {
  96         .cmd0csratio    = 0x80,
  97         .cmd0dldiff     = 0x04,
  98         .cmd0iclkout    = 0x00,
  99
 100         .cmd1csratio    = 0x80,
 101         .cmd1dldiff     = 0x04,
 102         .cmd1iclkout    = 0x00,
 103
 104         .cmd2csratio    = 0x80,
 105         .cmd2dldiff     = 0x04,
 106         .cmd2iclkout    = 0x00,
 107 };
 108
 109 static const struct emif_regs evm_ddr2_emif0_regs = {
 110         .sdram_config                   = 0x40801ab2,
 111         .ref_ctrl                       = 0x10000c30,
 112         .sdram_tim1                     = 0x0aaaf552,
 113         .sdram_tim2                     = 0x043631d2,
 114         .sdram_tim3                     = 0x00000327,
 115         .emif_ddr_phy_ctlr_1            = 0x00000007
 116 };
 117
 118 static const struct emif_regs evm_ddr2_emif1_regs = {
 119         .sdram_config                   = 0x40801ab2,
 120         .ref_ctrl                       = 0x10000c30,
 121         .sdram_tim1                     = 0x0aaaf552,
 122         .sdram_tim2                     = 0x043631d2,
 123         .sdram_tim3                     = 0x00000327,
 124         .emif_ddr_phy_ctlr_1            = 0x00000007
 125 };
 126
 127 const struct dmm_lisa_map_regs evm_lisa_map_regs = {
 128         .dmm_lisa_map_0                 = 0x00000000,
 129         .dmm_lisa_map_1                 = 0x00000000,
 130         .dmm_lisa_map_2                 = 0x806c0300,
 131         .dmm_lisa_map_3                 = 0x806c0300,
 132 };
 133
 134 static const struct ddr_data evm_ddr2_data = {
 135         .datardsratio0          = ((0x35<<10) | (0x35<<0)),
 136         .datawdsratio0          = ((0x20<<10) | (0x20<<0)),
 137         .datawiratio0           = ((0<<10) | (0<<0)),
 138         .datagiratio0           = ((0<<10) | (0<<0)),
 139         .datafwsratio0          = ((0x90<<10) | (0x90<<0)),
 140         .datawrsratio0          = ((0x50<<10) | (0x50<<0)),
 141         .datauserank0delay      = 1,
 142         .datadldiff0            = 0x4,
 143 };
 144 #endif
 145
 146 /*
 147  * early system init of muxing and clocks.
 148  */
 149 void s_init(void)
 150 {
 151 #ifdef CONFIG_SPL_BUILD
 152         /*
 153          * Save the boot parameters passed from romcode.
 154          * We cannot delay the saving further than this,
 155          * to prevent overwrites.
 156          */
 157 #ifdef CONFIG_SPL_BUILD
 158         save_omap_boot_params();
 159 #endif
 160
 161         /* WDT1 is already running when the bootloader gets control
 162          * Disable it to avoid "random" resets
 163          */
 164         wdt_disable();
 165
 166         /* Enable timer */
 167         timer_init();
 168
 169         /* Setup the PLLs and the clocks for the peripherals */
 170         pll_init();
 171
 172         /* Enable RTC32K clock */
 173         rtc32k_enable();
 174
 175         /* Set UART pins */
 176         enable_uart0_pin_mux();
 177
 178         /* Set MMC pins */
 179         enable_mmc1_pin_mux();
 180
 181         /* Set Ethernet pins */
 182         enable_enet_pin_mux();
 183
 184         /* Enable UART */
 185         uart_enable();
 186
 187         gd = &gdata;
 188
 189         preloader_console_init();
 190
 191         config_dmm(&evm_lisa_map_regs);
 192
 193         config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 194                    &evm_ddr2_emif0_regs, 0);
 195         config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 196                    &evm_ddr2_emif1_regs, 1);
 197 #endif
 198 }
 199
 200 /*
 201  * Basic board specific setup.  Pinmux has been handled already.
 202  */
 203 int board_init(void)
 204 {
 205         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 206         return 0;
 207 }
 208
 209 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 210 int board_mmc_init(bd_t *bis)
 211 {
 212         omap_mmc_init(1, 0, 0, -1, -1);
 213
 214         return 0;
 215 }
 216 #endif
 217
 218 #ifdef CONFIG_DRIVER_TI_CPSW
 219 static void cpsw_control(int enabled)
 220 {
 221         /* VTP can be added here */
 222
 223         return;
 224 }
 225
 226 static struct cpsw_slave_data cpsw_slaves[] = {
 227         {
 228                 .slave_reg_ofs  = 0x50,
 229                 .sliver_reg_ofs = 0x700,
 230                 .phy_id         = 1,
 231         },
 232         {
 233                 .slave_reg_ofs  = 0x90,
 234                 .sliver_reg_ofs = 0x740,
 235                 .phy_id         = 0,
 236         },
 237 };
 238
 239 static struct cpsw_platform_data cpsw_data = {
 240         .mdio_base              = CPSW_MDIO_BASE,
 241         .cpsw_base              = CPSW_BASE,
 242         .mdio_div               = 0xff,
 243         .channels               = 8,
 244         .cpdma_reg_ofs          = 0x100,
 245         .slaves                 = 1,
 246         .slave_data             = cpsw_slaves,
 247         .ale_reg_ofs            = 0x600,
 248         .ale_entries            = 1024,
 249         .host_port_reg_ofs      = 0x28,
 250         .hw_stats_reg_ofs       = 0x400,
 251         .mac_control            = (1 << 5),
 252         .control                = cpsw_control,
 253         .host_port_num          = 0,
 254         .version                = CPSW_CTRL_VERSION_1,
 255 };
 256 #endif
 257
 258 int board_eth_init(bd_t *bis)
 259 {
 260         uint8_t mac_addr[6];
 261         uint32_t mac_hi, mac_lo;
 262
 263         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 264                 printf("<ethaddr> not set. Reading from E-fuse\n");
 265                 /* try reading mac address from efuse */
 266                 mac_lo = readl(&cdev->macid0l);
 267                 mac_hi = readl(&cdev->macid0h);
 268                 mac_addr[0] = mac_hi & 0xFF;
 269                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 270                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 271                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 272                 mac_addr[4] = mac_lo & 0xFF;
 273                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 274
 275                 if (is_valid_ether_addr(mac_addr))
 276                         eth_setenv_enetaddr("ethaddr", mac_addr);
 277                 else
 278                         printf("Unable to read MAC address. Set <ethaddr>\n");
 279         }
 280
 281         return cpsw_register(&cpsw_data);
 282 }