2 * Copyright 2005 DENX Software Engineering
3 * Copyright 2004 Freescale Semiconductor.
4 * (C) Copyright 2002,2003, Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
35 #if defined(CONFIG_DDR_ECC)
36 extern void ddr_enable_ecc (unsigned int dram_size);
39 extern long int spd_sdram (void);
41 void local_bus_init (void);
42 long int fixed_sdram (void);
45 int board_early_init_f (void)
52 puts ("Board: TQM8540\n");
55 printf (" PCI1: 32 bit, %d MHz (compiled)\n",
56 CONFIG_SYS_CLK_FREQ / 1000000);
58 printf (" PCI1: disabled\n");
61 * Initialize local bus.
69 long int initdram (int board_type)
72 extern long spd_sdram (void);
73 volatile immap_t *immap = (immap_t *) CFG_IMMR;
75 puts ("Initializing\n");
77 #if defined(CONFIG_DDR_DLL)
79 volatile ccsr_gur_t *gur = &immap->im_gur;
83 * Work around to stabilize DDR DLL
85 temp_ddrdll = gur->ddrdllcr;
86 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
87 asm ("sync;isync;msync");
91 #if defined(CONFIG_SPD_EEPROM)
92 dram_size = spd_sdram ();
94 dram_size = fixed_sdram ();
97 #if defined(CONFIG_DDR_ECC)
99 * Initialize and enable DDR ECC.
101 ddr_enable_ecc (dram_size);
110 * Initialize Local Bus
113 void local_bus_init (void)
115 volatile immap_t *immap = (immap_t *) CFG_IMMR;
116 volatile ccsr_gur_t *gur = &immap->im_gur;
117 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
125 * Fix Local Bus clock glitch when DLL is enabled.
127 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
128 * If localbus freq is > 133Mhz, DLL can be safely enabled.
129 * Between 66 and 133, the DLL is enabled with an override workaround.
132 get_sys_info (&sysinfo);
133 clkdiv = lbc->lcrr & 0x0f;
134 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
137 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
138 lbc->ltedr = 0xa4c80000; /* DK: !!! */
140 } else if (lbc_hz >= 133) {
141 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
145 * On REV1 boards, need to change CLKDIV before enable DLL.
146 * Default CLKDIV is 8, change it to 4 temporarily.
148 uint pvr = get_pvr ();
149 uint temp_lbcdll = 0;
151 if (pvr == PVR_85xx_REV1) {
152 /* FIXME: Justify the high bit here. */
153 lbc->lcrr = 0x10000004;
156 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
160 * Sample LBC DLL ctrl reg, upshift it to set the
163 temp_lbcdll = gur->lbcdllcr;
164 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
165 asm ("sync;isync;msync");
170 #if defined(CFG_DRAM_TEST)
173 uint *pstart = (uint *) CFG_MEMTEST_START;
174 uint *pend = (uint *) CFG_MEMTEST_END;
177 printf ("SDRAM test phase 1:\n");
178 for (p = pstart; p < pend; p++)
181 for (p = pstart; p < pend; p++) {
182 if (*p != 0xaaaaaaaa) {
183 printf ("SDRAM test fails at: %08x\n", (uint) p);
188 printf ("SDRAM test phase 2:\n");
189 for (p = pstart; p < pend; p++)
192 for (p = pstart; p < pend; p++) {
193 if (*p != 0x55555555) {
194 printf ("SDRAM test fails at: %08x\n", (uint) p);
199 printf ("SDRAM test passed.\n");
205 #if !defined(CONFIG_SPD_EEPROM)
206 /*************************************************************************
207 * fixed sdram init -- doesn't use serial presence detect.
208 ************************************************************************/
209 long int fixed_sdram (void)
212 volatile immap_t *immap = (immap_t *) CFG_IMMR;
213 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
215 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
216 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
217 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
218 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
219 ddr->sdram_mode = CFG_DDR_MODE;
220 ddr->sdram_interval = CFG_DDR_INTERVAL;
221 ddr->err_disable = 0x0000000D;
222 #if defined (CONFIG_DDR_ECC)
223 ddr->err_disable = 0x0000000D;
224 ddr->err_sbe = 0x00ff0000;
226 asm ("sync;isync;msync");
228 #if defined (CONFIG_DDR_ECC)
229 /* Enable ECC checking */
230 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
232 ddr->sdram_cfg = CFG_DDR_CONTROL;
234 asm ("sync; isync; msync");
237 return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
239 #endif /* !defined(CONFIG_SPD_EEPROM) */
242 #if defined(CONFIG_PCI)
244 * Initialize PCI Devices, report devices found.
247 #ifndef CONFIG_PCI_PNP
248 static struct pci_config_table pci_mpc85xxads_config_table[] = {
249 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
250 PCI_IDSEL_NUMBER, PCI_ANY_ID,
251 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
254 PCI_COMMAND_MASTER}},
260 static struct pci_controller hose = {
261 #ifndef CONFIG_PCI_PNP
262 config_table:pci_mpc85xxads_config_table,
266 #endif /* CONFIG_PCI */
269 void pci_init_board (void)
272 extern void pci_mpc85xx_init (struct pci_controller *hose);
274 pci_mpc85xx_init (&hose);
275 #endif /* CONFIG_PCI */