board/ttcontrol/vision2/vision2.c

   1 /*
   2  * (C) Copyright 2010
   3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/iomux-mx51.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/imx-common/spi.h>
  19 #include <i2c.h>
  20 #include <mmc.h>
  21 #include <power/pmic.h>
  22 #include <fsl_esdhc.h>
  23 #include <fsl_pmic.h>
  24 #include <mc13892.h>
  25 #include <linux/fb.h>
  26
  27 #include <ipu_pixfmt.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 static struct fb_videomode const nec_nl6448bc26_09c = {
  32         "NEC_NL6448BC26-09C",
  33         60,     /* Refresh */
  34         640,    /* xres */
  35         480,    /* yres */
  36         37650,  /* pixclock = 26.56Mhz */
  37         48,     /* left margin */
  38         16,     /* right margin */
  39         31,     /* upper margin */
  40         12,     /* lower margin */
  41         96,     /* hsync-len */
  42         2,      /* vsync-len */
  43         0,      /* sync */
  44         FB_VMODE_NONINTERLACED, /* vmode */
  45         0,      /* flag */
  46 };
  47
  48 #ifdef CONFIG_HW_WATCHDOG
  49 #include <watchdog.h>
  50 void hw_watchdog_reset(void)
  51 {
  52         int val;
  53
  54         /* toggle watchdog trigger pin */
  55         val = gpio_get_value(IMX_GPIO_NR(3, 2));
  56         val = val ? 0 : 1;
  57         gpio_set_value(IMX_GPIO_NR(3, 2), val);
  58 }
  59 #endif
  60
  61 static void init_drive_strength(void)
  62 {
  63         static const iomux_v3_cfg_t ddr_pads[] = {
  64                 NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
  65                 NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
  66                 NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
  67                 NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
  68                 NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
  69                 NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
  70                 NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
  71                 NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
  72                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  73                 NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
  74                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  75                 NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
  76                 NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
  77                 NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
  78                 NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
  79                 NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
  80                 NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
  81                 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
  82                 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
  83                 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
  84                 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
  85                 NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
  86                 NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
  87                 NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
  88                 NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
  89                 NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
  90                 NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
  91
  92                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
  93                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
  94                                 MX51_GPIO_PAD_CTRL),
  95                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
  96                                 MX51_GPIO_PAD_CTRL),
  97                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
  98                                 MX51_GPIO_PAD_CTRL),
  99                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
 100                                 MX51_GPIO_PAD_CTRL),
 101                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
 102                                 MX51_GPIO_PAD_CTRL),
 103                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
 104                                 MX51_GPIO_PAD_CTRL),
 105                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
 106                                 MX51_GPIO_PAD_CTRL),
 107                 NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
 108                 NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
 109                 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
 110                 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
 111                 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
 112                 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
 113         };
 114
 115         imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
 116 }
 117
 118 int dram_init(void)
 119 {
 120         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
 121                 PHYS_SDRAM_1_SIZE);
 122
 123         return 0;
 124 }
 125
 126 static void setup_weim(void)
 127 {
 128         struct weim  *pweim = (struct weim *)WEIM_BASE_ADDR;
 129
 130         pweim->cs0gcr1 = 0x004100b9;
 131         pweim->cs0gcr2 = 0x00000001;
 132         pweim->cs0rcr1 = 0x0a018000;
 133         pweim->cs0rcr2 = 0;
 134         pweim->cs0wcr1 = 0x0704a240;
 135 }
 136
 137 static void setup_uart(void)
 138 {
 139         static const iomux_v3_cfg_t uart_pads[] = {
 140                 MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
 141                 MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
 142         };
 143
 144         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 145 }
 146
 147 #ifdef CONFIG_MXC_SPI
 148 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 149 {
 150         return (bus == 0 && cs == 1) ? 121 : -1;
 151 }
 152
 153 void spi_io_init(void)
 154 {
 155         static const iomux_v3_cfg_t spi_pads[] = {
 156                 NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
 157                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 158                 NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
 159                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 160                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
 161                         PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 162                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
 163                         PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 164                 NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
 165                         PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 166                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
 167                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 168         };
 169
 170         imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 171 }
 172
 173 static void reset_peripherals(int reset)
 174 {
 175 #ifdef CONFIG_VISION2_HW_1_0
 176         static const iomux_v3_cfg_t fec_cfg_pads[] = {
 177                 /* RXD1 */
 178                 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
 179                 /* RXD2 */
 180                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
 181                 /* RXD3 */
 182                 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
 183                 /* RXER */
 184                 NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
 185                 /* COL */
 186                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
 187                 /* RCLK */
 188                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
 189                 /* RXD0 */
 190                 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
 191         };
 192
 193         static const iomux_v3_cfg_t fec_pads[] = {
 194                 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
 195                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
 196                 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
 197                 MX51_PAD_NANDF_D9__FEC_RDATA0,
 198                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
 199                 MX51_PAD_EIM_CS4__FEC_RX_ER,
 200                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
 201         };
 202 #endif
 203
 204         if (reset) {
 205
 206                 /* reset_n is on NANDF_D15 */
 207                 gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
 208
 209 #ifdef CONFIG_VISION2_HW_1_0
 210                 /*
 211                  * set FEC Configuration lines
 212                  * set levels of FEC config lines
 213                  */
 214                 gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
 215                 gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
 216                 gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
 217
 218                 /* set direction of FEC config lines */
 219                 gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
 220                 gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
 221                 gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
 222                 gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
 223
 224                 imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
 225                                                  ARRAY_SIZE(fec_cfg_pads));
 226 #endif
 227
 228                 /* activate reset_n pin */
 229                 imx_iomux_v3_setup_pad(
 230                                 NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
 231                                                 PAD_CTL_DSE_MAX));
 232         } else {
 233                 /* set FEC Control lines */
 234                 gpio_direction_input(IMX_GPIO_NR(3, 25));
 235                 udelay(500);
 236
 237 #ifdef CONFIG_VISION2_HW_1_0
 238                 imx_iomux_v3_setup_multiple_pads(fec_pads,
 239                                                         ARRAY_SIZE(fec_pads));
 240 #endif
 241         }
 242 }
 243
 244 static void power_init_mx51(void)
 245 {
 246         unsigned int val;
 247         struct pmic *p;
 248         int ret;
 249
 250         ret = pmic_init(I2C_PMIC);
 251         if (ret)
 252                 return;
 253
 254         p = pmic_get("FSL_PMIC");
 255         if (!p)
 256                 return;
 257
 258         /* Write needed to Power Gate 2 register */
 259         pmic_reg_read(p, REG_POWER_MISC, &val);
 260
 261         /* enable VCAM with 2.775V to enable read from PMIC */
 262         val = VCAMCONFIG | VCAMEN;
 263         pmic_reg_write(p, REG_MODE_1, val);
 264
 265         /*
 266          * Set switchers in Auto in NORMAL mode & STANDBY mode
 267          * Setup the switcher mode for SW1 & SW2
 268          */
 269         pmic_reg_read(p, REG_SW_4, &val);
 270         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 271                 (SWMODE_MASK << SWMODE2_SHIFT)));
 272         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 273                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 274         pmic_reg_write(p, REG_SW_4, val);
 275
 276         /* Setup the switcher mode for SW3 & SW4 */
 277         pmic_reg_read(p, REG_SW_5, &val);
 278         val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
 279                 (SWMODE_MASK << SWMODE3_SHIFT));
 280         val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
 281                 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
 282         pmic_reg_write(p, REG_SW_5, val);
 283
 284
 285         /* Set VGEN3 to 1.8V, VCAM to 3.0V */
 286         pmic_reg_read(p, REG_SETTING_0, &val);
 287         val &= ~(VCAM_MASK | VGEN3_MASK);
 288         val |= VCAM_3_0;
 289         pmic_reg_write(p, REG_SETTING_0, val);
 290
 291         /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
 292         pmic_reg_read(p, REG_SETTING_1, &val);
 293         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 294         val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
 295         pmic_reg_write(p, REG_SETTING_1, val);
 296
 297         /* Configure VGEN3 and VCAM regulators to use external PNP */
 298         val = VGEN3CONFIG | VCAMCONFIG;
 299         pmic_reg_write(p, REG_MODE_1, val);
 300         udelay(200);
 301
 302         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 303         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 304                 VVIDEOEN | VAUDIOEN  | VSDEN;
 305         pmic_reg_write(p, REG_MODE_1, val);
 306
 307         pmic_reg_read(p, REG_POWER_CTL2, &val);
 308         val |= WDIRESET;
 309         pmic_reg_write(p, REG_POWER_CTL2, val);
 310
 311         udelay(2500);
 312
 313 }
 314 #endif
 315
 316 static void setup_gpios(void)
 317 {
 318         static const iomux_v3_cfg_t gpio_pads_1[] = {
 319                 NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
 320                                 PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
 321                 NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
 322                                 PAD_CTL_DSE_MED), /* DAB Display EN */
 323                 NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
 324                                 PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
 325         };
 326
 327         static const iomux_v3_cfg_t gpio_pads_2[] = {
 328                 NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
 329                                 PAD_CTL_DSE_MED), /* Display2 TxEN */
 330                 NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
 331                                 PAD_CTL_DSE_MED), /* DAB Light EN */
 332                 NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
 333                                 PAD_CTL_DSE_MED), /* AUDIO_MUTE */
 334                 NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
 335                                 PAD_CTL_DSE_MED), /* SPARE_OUT */
 336                 NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
 337                                 PAD_CTL_DSE_MED), /* BEEPER_EN */
 338                 NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
 339                                 PAD_CTL_DSE_MED), /* POWER_OFF */
 340                 NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
 341                                 PAD_CTL_DSE_MED), /* FRAM_WE */
 342                 NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
 343                                 PAD_CTL_DSE_MED), /* EXPANSION_EN */
 344                 MX51_PAD_GPIO1_2__PWM1_PWMO,
 345         };
 346
 347         unsigned int i;
 348
 349         imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
 350
 351         /* Now we need to trigger the watchdog */
 352         WATCHDOG_RESET();
 353
 354         imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
 355
 356         /*
 357          * Set GPIO1_4 to high and output; it is used to reset
 358          * the system on reboot
 359          */
 360         gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
 361
 362         gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
 363         for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
 364                 gpio_direction_output(i, 0);
 365
 366         gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
 367
 368         /* Set POWER_OFF high */
 369         gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
 370
 371         gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
 372
 373         gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
 374
 375         gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
 376
 377         WATCHDOG_RESET();
 378 }
 379
 380 static void setup_fec(void)
 381 {
 382         static const iomux_v3_cfg_t fec_pads[] = {
 383                 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
 384                                 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
 385                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
 386                 MX51_PAD_NANDF_CS3__FEC_MDC,
 387                 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
 388                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
 389                 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
 390                 MX51_PAD_NANDF_D9__FEC_RDATA0,
 391                 MX51_PAD_NANDF_CS6__FEC_TDATA3,
 392                 MX51_PAD_NANDF_CS5__FEC_TDATA2,
 393                 MX51_PAD_NANDF_CS4__FEC_TDATA1,
 394                 MX51_PAD_NANDF_D8__FEC_TDATA0,
 395                 MX51_PAD_NANDF_CS7__FEC_TX_EN,
 396                 MX51_PAD_NANDF_CS2__FEC_TX_ER,
 397                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
 398                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
 399                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
 400                 MX51_PAD_EIM_CS5__FEC_CRS,
 401                 MX51_PAD_EIM_CS4__FEC_RX_ER,
 402                 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
 403         };
 404
 405         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 406 }
 407
 408 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 409         {MMC_SDHC1_BASE_ADDR},
 410 };
 411
 412 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
 413 {
 414         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 415
 416         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 417                 *cd = gpio_get_value(IMX_GPIO_NR(1, 0));
 418         else
 419                 *cd = 0;
 420
 421         return 0;
 422 }
 423
 424 #ifdef CONFIG_FSL_ESDHC
 425 int board_mmc_init(bd_t *bis)
 426 {
 427         static const iomux_v3_cfg_t sd1_pads[] = {
 428                 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
 429                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 430                 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
 431                         PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 432                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
 433                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 434                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
 435                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 436                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
 437                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 438                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
 439                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
 440                 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
 441                 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
 442         };
 443
 444         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 445
 446         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 447         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 448 }
 449 #endif
 450
 451 void lcd_enable(void)
 452 {
 453         static const iomux_v3_cfg_t lcd_pads[] = {
 454                 MX51_PAD_DI1_PIN2__DI1_PIN2,
 455                 MX51_PAD_DI1_PIN3__DI1_PIN3,
 456         };
 457
 458         int ret;
 459
 460         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 461
 462         gpio_set_value(IMX_GPIO_NR(1, 2), 1);
 463         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
 464                                                 NO_PAD_CTRL));
 465
 466         ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
 467         if (ret)
 468                 puts("LCD cannot be configured\n");
 469 }
 470
 471 int board_early_init_f(void)
 472 {
 473
 474
 475         init_drive_strength();
 476
 477         /* Setup debug led */
 478         gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
 479         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
 480                                         PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
 481
 482         /* wait a little while to give the pll time to settle */
 483         sdelay(100000);
 484
 485         setup_weim();
 486         setup_uart();
 487         setup_fec();
 488         setup_gpios();
 489
 490         spi_io_init();
 491
 492         return 0;
 493 }
 494
 495 static void backlight(int on)
 496 {
 497         if (on) {
 498                 gpio_set_value(IMX_GPIO_NR(3, 1), 1);
 499                 udelay(10000);
 500                 gpio_set_value(IMX_GPIO_NR(3, 4), 1);
 501         } else {
 502                 gpio_set_value(IMX_GPIO_NR(3, 1), 0);
 503                 gpio_set_value(IMX_GPIO_NR(3, 4), 0);
 504         }
 505 }
 506
 507 int board_init(void)
 508 {
 509         /* address of boot parameters */
 510         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 511
 512         lcd_enable();
 513
 514         backlight(1);
 515
 516         return 0;
 517 }
 518
 519 int board_late_init(void)
 520 {
 521         power_init_mx51();
 522
 523         reset_peripherals(1);
 524         udelay(2000);
 525         reset_peripherals(0);
 526         udelay(2000);
 527
 528         /* Early revisions require a second reset */
 529 #ifdef CONFIG_VISION2_HW_1_0
 530         reset_peripherals(1);
 531         udelay(2000);
 532         reset_peripherals(0);
 533         udelay(2000);
 534 #endif
 535
 536         return 0;
 537 }
 538
 539 /*
 540  * Do not overwrite the console
 541  * Use always serial for U-Boot console
 542  */
 543 int overwrite_console(void)
 544 {
 545         return 1;
 546 }
 547
 548 int checkboard(void)
 549 {
 550         puts("Board: TTControl Vision II CPU V\n");
 551
 552         return 0;
 553 }
 554
 555 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 556 {
 557         int on;
 558
 559         if (argc < 2)
 560                 return cmd_usage(cmdtp);
 561
 562         on = (strcmp(argv[1], "on") == 0);
 563         backlight(on);
 564
 565         return 0;
 566 }
 567
 568 U_BOOT_CMD(
 569         lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
 570         "Vision2 Backlight",
 571         "lcdbl [on|off]\n"
 572 );