board/ttcontrol/vision2/vision2.c

   1 /*
   2  * (C) Copyright 2010
   3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/iomux-mx51.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <i2c.h>
  19 #include <mmc.h>
  20 #include <power/pmic.h>
  21 #include <fsl_esdhc.h>
  22 #include <fsl_pmic.h>
  23 #include <mc13892.h>
  24 #include <linux/fb.h>
  25
  26 #include <ipu_pixfmt.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static struct fb_videomode const nec_nl6448bc26_09c = {
  31         "NEC_NL6448BC26-09C",
  32         60,     /* Refresh */
  33         640,    /* xres */
  34         480,    /* yres */
  35         37650,  /* pixclock = 26.56Mhz */
  36         48,     /* left margin */
  37         16,     /* right margin */
  38         31,     /* upper margin */
  39         12,     /* lower margin */
  40         96,     /* hsync-len */
  41         2,      /* vsync-len */
  42         0,      /* sync */
  43         FB_VMODE_NONINTERLACED, /* vmode */
  44         0,      /* flag */
  45 };
  46
  47 #ifdef CONFIG_HW_WATCHDOG
  48 #include <watchdog.h>
  49 void hw_watchdog_reset(void)
  50 {
  51         int val;
  52
  53         /* toggle watchdog trigger pin */
  54         val = gpio_get_value(IMX_GPIO_NR(3, 2));
  55         val = val ? 0 : 1;
  56         gpio_set_value(IMX_GPIO_NR(3, 2), val);
  57 }
  58 #endif
  59
  60 static void init_drive_strength(void)
  61 {
  62         static const iomux_v3_cfg_t ddr_pads[] = {
  63                 NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
  64                 NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
  65                 NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
  66                 NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
  67                 NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
  68                 NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
  69                 NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
  70                 NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
  71                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  72                 NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
  73                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  74                 NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
  75                 NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
  76                 NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
  77                 NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
  78                 NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
  79                 NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
  80                 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
  81                 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
  82                 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
  83                 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
  84                 NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
  85                 NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
  86                 NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
  87                 NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
  88                 NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
  89                 NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
  90
  91                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
  92                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
  93                                 MX51_GPIO_PAD_CTRL),
  94                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
  95                                 MX51_GPIO_PAD_CTRL),
  96                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
  97                                 MX51_GPIO_PAD_CTRL),
  98                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
  99                                 MX51_GPIO_PAD_CTRL),
 100                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
 101                                 MX51_GPIO_PAD_CTRL),
 102                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
 103                                 MX51_GPIO_PAD_CTRL),
 104                 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
 105                                 MX51_GPIO_PAD_CTRL),
 106                 NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
 107                 NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
 108                 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
 109                 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
 110                 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
 111                 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
 112         };
 113
 114         imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
 115 }
 116
 117 int dram_init(void)
 118 {
 119         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
 120                 PHYS_SDRAM_1_SIZE);
 121
 122         return 0;
 123 }
 124
 125 static void setup_weim(void)
 126 {
 127         struct weim  *pweim = (struct weim *)WEIM_BASE_ADDR;
 128
 129         pweim->cs0gcr1 = 0x004100b9;
 130         pweim->cs0gcr2 = 0x00000001;
 131         pweim->cs0rcr1 = 0x0a018000;
 132         pweim->cs0rcr2 = 0;
 133         pweim->cs0wcr1 = 0x0704a240;
 134 }
 135
 136 static void setup_uart(void)
 137 {
 138         static const iomux_v3_cfg_t uart_pads[] = {
 139                 MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
 140                 MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
 141         };
 142
 143         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 144 }
 145
 146 #ifdef CONFIG_MXC_SPI
 147 void spi_io_init(void)
 148 {
 149         static const iomux_v3_cfg_t spi_pads[] = {
 150                 NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
 151                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 152                 NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
 153                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 154                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
 155                         PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 156                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
 157                         PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 158                 NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
 159                         PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 160                 NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
 161                                 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
 162         };
 163
 164         imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 165 }
 166
 167 static void reset_peripherals(int reset)
 168 {
 169 #ifdef CONFIG_VISION2_HW_1_0
 170         static const iomux_v3_cfg_t fec_cfg_pads[] = {
 171                 /* RXD1 */
 172                 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
 173                 /* RXD2 */
 174                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
 175                 /* RXD3 */
 176                 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
 177                 /* RXER */
 178                 NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
 179                 /* COL */
 180                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
 181                 /* RCLK */
 182                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
 183                 /* RXD0 */
 184                 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
 185         };
 186
 187         static const iomux_v3_cfg_t fec_pads[] = {
 188                 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
 189                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
 190                 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
 191                 MX51_PAD_NANDF_D9__FEC_RDATA0,
 192                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
 193                 MX51_PAD_EIM_CS4__FEC_RX_ER,
 194                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
 195         };
 196 #endif
 197
 198         if (reset) {
 199
 200                 /* reset_n is on NANDF_D15 */
 201                 gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
 202
 203 #ifdef CONFIG_VISION2_HW_1_0
 204                 /*
 205                  * set FEC Configuration lines
 206                  * set levels of FEC config lines
 207                  */
 208                 gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
 209                 gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
 210                 gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
 211
 212                 /* set direction of FEC config lines */
 213                 gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
 214                 gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
 215                 gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
 216                 gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
 217
 218                 imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
 219                                                  ARRAY_SIZE(fec_cfg_pads));
 220 #endif
 221
 222                 /* activate reset_n pin */
 223                 imx_iomux_v3_setup_pad(
 224                                 NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
 225                                                 PAD_CTL_DSE_MAX));
 226         } else {
 227                 /* set FEC Control lines */
 228                 gpio_direction_input(IMX_GPIO_NR(3, 25));
 229                 udelay(500);
 230
 231 #ifdef CONFIG_VISION2_HW_1_0
 232                 imx_iomux_v3_setup_multiple_pads(fec_pads,
 233                                                         ARRAY_SIZE(fec_pads));
 234 #endif
 235         }
 236 }
 237
 238 static void power_init_mx51(void)
 239 {
 240         unsigned int val;
 241         struct pmic *p;
 242         int ret;
 243
 244         ret = pmic_init(I2C_PMIC);
 245         if (ret)
 246                 return;
 247
 248         p = pmic_get("FSL_PMIC");
 249         if (!p)
 250                 return;
 251
 252         /* Write needed to Power Gate 2 register */
 253         pmic_reg_read(p, REG_POWER_MISC, &val);
 254
 255         /* enable VCAM with 2.775V to enable read from PMIC */
 256         val = VCAMCONFIG | VCAMEN;
 257         pmic_reg_write(p, REG_MODE_1, val);
 258
 259         /*
 260          * Set switchers in Auto in NORMAL mode & STANDBY mode
 261          * Setup the switcher mode for SW1 & SW2
 262          */
 263         pmic_reg_read(p, REG_SW_4, &val);
 264         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 265                 (SWMODE_MASK << SWMODE2_SHIFT)));
 266         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 267                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 268         pmic_reg_write(p, REG_SW_4, val);
 269
 270         /* Setup the switcher mode for SW3 & SW4 */
 271         pmic_reg_read(p, REG_SW_5, &val);
 272         val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
 273                 (SWMODE_MASK << SWMODE3_SHIFT));
 274         val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
 275                 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
 276         pmic_reg_write(p, REG_SW_5, val);
 277
 278
 279         /* Set VGEN3 to 1.8V, VCAM to 3.0V */
 280         pmic_reg_read(p, REG_SETTING_0, &val);
 281         val &= ~(VCAM_MASK | VGEN3_MASK);
 282         val |= VCAM_3_0;
 283         pmic_reg_write(p, REG_SETTING_0, val);
 284
 285         /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
 286         pmic_reg_read(p, REG_SETTING_1, &val);
 287         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 288         val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
 289         pmic_reg_write(p, REG_SETTING_1, val);
 290
 291         /* Configure VGEN3 and VCAM regulators to use external PNP */
 292         val = VGEN3CONFIG | VCAMCONFIG;
 293         pmic_reg_write(p, REG_MODE_1, val);
 294         udelay(200);
 295
 296         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 297         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 298                 VVIDEOEN | VAUDIOEN  | VSDEN;
 299         pmic_reg_write(p, REG_MODE_1, val);
 300
 301         pmic_reg_read(p, REG_POWER_CTL2, &val);
 302         val |= WDIRESET;
 303         pmic_reg_write(p, REG_POWER_CTL2, val);
 304
 305         udelay(2500);
 306
 307 }
 308 #endif
 309
 310 static void setup_gpios(void)
 311 {
 312         static const iomux_v3_cfg_t gpio_pads_1[] = {
 313                 NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
 314                                 PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
 315                 NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
 316                                 PAD_CTL_DSE_MED), /* DAB Display EN */
 317                 NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
 318                                 PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
 319         };
 320
 321         static const iomux_v3_cfg_t gpio_pads_2[] = {
 322                 NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
 323                                 PAD_CTL_DSE_MED), /* Display2 TxEN */
 324                 NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
 325                                 PAD_CTL_DSE_MED), /* DAB Light EN */
 326                 NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
 327                                 PAD_CTL_DSE_MED), /* AUDIO_MUTE */
 328                 NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
 329                                 PAD_CTL_DSE_MED), /* SPARE_OUT */
 330                 NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
 331                                 PAD_CTL_DSE_MED), /* BEEPER_EN */
 332                 NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
 333                                 PAD_CTL_DSE_MED), /* POWER_OFF */
 334                 NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
 335                                 PAD_CTL_DSE_MED), /* FRAM_WE */
 336                 NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
 337                                 PAD_CTL_DSE_MED), /* EXPANSION_EN */
 338                 MX51_PAD_GPIO1_2__PWM1_PWMO,
 339         };
 340
 341         unsigned int i;
 342
 343         imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
 344
 345         /* Now we need to trigger the watchdog */
 346         WATCHDOG_RESET();
 347
 348         imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
 349
 350         /*
 351          * Set GPIO1_4 to high and output; it is used to reset
 352          * the system on reboot
 353          */
 354         gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
 355
 356         gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
 357         for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
 358                 gpio_direction_output(i, 0);
 359
 360         gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
 361
 362         /* Set POWER_OFF high */
 363         gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
 364
 365         gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
 366
 367         gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
 368
 369         gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
 370
 371         WATCHDOG_RESET();
 372 }
 373
 374 static void setup_fec(void)
 375 {
 376         static const iomux_v3_cfg_t fec_pads[] = {
 377                 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
 378                                 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
 379                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
 380                 MX51_PAD_NANDF_CS3__FEC_MDC,
 381                 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
 382                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
 383                 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
 384                 MX51_PAD_NANDF_D9__FEC_RDATA0,
 385                 MX51_PAD_NANDF_CS6__FEC_TDATA3,
 386                 MX51_PAD_NANDF_CS5__FEC_TDATA2,
 387                 MX51_PAD_NANDF_CS4__FEC_TDATA1,
 388                 MX51_PAD_NANDF_D8__FEC_TDATA0,
 389                 MX51_PAD_NANDF_CS7__FEC_TX_EN,
 390                 MX51_PAD_NANDF_CS2__FEC_TX_ER,
 391                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
 392                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
 393                 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
 394                 MX51_PAD_EIM_CS5__FEC_CRS,
 395                 MX51_PAD_EIM_CS4__FEC_RX_ER,
 396                 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
 397         };
 398
 399         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 400 }
 401
 402 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 403         {MMC_SDHC1_BASE_ADDR},
 404 };
 405
 406 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
 407 {
 408         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 409
 410         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 411                 *cd = gpio_get_value(IMX_GPIO_NR(1, 0));
 412         else
 413                 *cd = 0;
 414
 415         return 0;
 416 }
 417
 418 #ifdef CONFIG_FSL_ESDHC
 419 int board_mmc_init(bd_t *bis)
 420 {
 421         static const iomux_v3_cfg_t sd1_pads[] = {
 422                 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
 423                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 424                 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
 425                         PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 426                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
 427                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 428                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
 429                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 430                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
 431                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 432                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
 433                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
 434                 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
 435                 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
 436         };
 437
 438         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 439
 440         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 441         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 442 }
 443 #endif
 444
 445 void lcd_enable(void)
 446 {
 447         static const iomux_v3_cfg_t lcd_pads[] = {
 448                 MX51_PAD_DI1_PIN2__DI1_PIN2,
 449                 MX51_PAD_DI1_PIN3__DI1_PIN3,
 450         };
 451
 452         int ret;
 453
 454         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 455
 456         gpio_set_value(IMX_GPIO_NR(1, 2), 1);
 457         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
 458                                                 NO_PAD_CTRL));
 459
 460         ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
 461         if (ret)
 462                 puts("LCD cannot be configured\n");
 463 }
 464
 465 int board_early_init_f(void)
 466 {
 467
 468
 469         init_drive_strength();
 470
 471         /* Setup debug led */
 472         gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
 473         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
 474                                         PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
 475
 476         /* wait a little while to give the pll time to settle */
 477         sdelay(100000);
 478
 479         setup_weim();
 480         setup_uart();
 481         setup_fec();
 482         setup_gpios();
 483
 484         spi_io_init();
 485
 486         return 0;
 487 }
 488
 489 static void backlight(int on)
 490 {
 491         if (on) {
 492                 gpio_set_value(IMX_GPIO_NR(3, 1), 1);
 493                 udelay(10000);
 494                 gpio_set_value(IMX_GPIO_NR(3, 4), 1);
 495         } else {
 496                 gpio_set_value(IMX_GPIO_NR(3, 1), 0);
 497                 gpio_set_value(IMX_GPIO_NR(3, 4), 0);
 498         }
 499 }
 500
 501 int board_init(void)
 502 {
 503         /* address of boot parameters */
 504         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 505
 506         lcd_enable();
 507
 508         backlight(1);
 509
 510         return 0;
 511 }
 512
 513 int board_late_init(void)
 514 {
 515         power_init_mx51();
 516
 517         reset_peripherals(1);
 518         udelay(2000);
 519         reset_peripherals(0);
 520         udelay(2000);
 521
 522         /* Early revisions require a second reset */
 523 #ifdef CONFIG_VISION2_HW_1_0
 524         reset_peripherals(1);
 525         udelay(2000);
 526         reset_peripherals(0);
 527         udelay(2000);
 528 #endif
 529
 530         return 0;
 531 }
 532
 533 /*
 534  * Do not overwrite the console
 535  * Use always serial for U-Boot console
 536  */
 537 int overwrite_console(void)
 538 {
 539         return 1;
 540 }
 541
 542 int checkboard(void)
 543 {
 544         puts("Board: TTControl Vision II CPU V\n");
 545
 546         return 0;
 547 }
 548
 549 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 550 {
 551         int on;
 552
 553         if (argc < 2)
 554                 return cmd_usage(cmdtp);
 555
 556         on = (strcmp(argv[1], "on") == 0);
 557         backlight(on);
 558
 559         return 0;
 560 }
 561
 562 U_BOOT_CMD(
 563         lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
 564         "Vision2 Backlight",
 565         "lcdbl [on|off]\n"
 566 );