3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/iomux-mx51.h>
17 #include <asm/arch/sys_proto.h>
20 #include <power/pmic.h>
21 #include <fsl_esdhc.h>
26 #include <ipu_pixfmt.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 static struct fb_videomode const nec_nl6448bc26_09c = {
35 37650, /* pixclock = 26.56Mhz */
37 16, /* right margin */
38 31, /* upper margin */
39 12, /* lower margin */
43 FB_VMODE_NONINTERLACED, /* vmode */
47 #ifdef CONFIG_HW_WATCHDOG
49 void hw_watchdog_reset(void)
53 /* toggle watchdog trigger pin */
54 val = gpio_get_value(IMX_GPIO_NR(3, 2));
56 gpio_set_value(IMX_GPIO_NR(3, 2), val);
60 static void init_drive_strength(void)
62 static const iomux_v3_cfg_t ddr_pads[] = {
63 NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
64 NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
65 NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
66 NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
67 NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
68 NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
69 NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
70 NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
71 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
72 NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
73 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
74 NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
75 NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
76 NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
77 NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
78 NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
79 NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
80 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
81 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
82 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
83 NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
84 NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
85 NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
86 NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
87 NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
88 NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
89 NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
91 NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
92 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
94 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
96 NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
98 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
100 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
102 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
104 NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
106 NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
107 NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
108 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
109 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
110 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
111 NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
114 imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
119 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
125 static void setup_weim(void)
127 struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
129 pweim->cs0gcr1 = 0x004100b9;
130 pweim->cs0gcr2 = 0x00000001;
131 pweim->cs0rcr1 = 0x0a018000;
133 pweim->cs0wcr1 = 0x0704a240;
136 static void setup_uart(void)
138 static const iomux_v3_cfg_t uart_pads[] = {
139 MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
140 MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
143 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
146 #ifdef CONFIG_MXC_SPI
147 int board_spi_cs_gpio(unsigned bus, unsigned cs)
149 return (bus == 0 && cs == 1) ? 121 : -1;
152 void spi_io_init(void)
154 static const iomux_v3_cfg_t spi_pads[] = {
155 NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
156 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
157 NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
158 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
159 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
160 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
161 NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
162 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
163 NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
164 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
165 NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
166 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
169 imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
172 static void reset_peripherals(int reset)
174 #ifdef CONFIG_VISION2_HW_1_0
175 static const iomux_v3_cfg_t fec_cfg_pads[] = {
177 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
179 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
181 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
183 NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
185 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
187 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
189 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
192 static const iomux_v3_cfg_t fec_pads[] = {
193 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
194 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
195 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
196 MX51_PAD_NANDF_D9__FEC_RDATA0,
197 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
198 MX51_PAD_EIM_CS4__FEC_RX_ER,
199 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
205 /* reset_n is on NANDF_D15 */
206 gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
208 #ifdef CONFIG_VISION2_HW_1_0
210 * set FEC Configuration lines
211 * set levels of FEC config lines
213 gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
214 gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
215 gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
217 /* set direction of FEC config lines */
218 gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
219 gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
220 gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
221 gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
223 imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
224 ARRAY_SIZE(fec_cfg_pads));
227 /* activate reset_n pin */
228 imx_iomux_v3_setup_pad(
229 NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
232 /* set FEC Control lines */
233 gpio_direction_input(IMX_GPIO_NR(3, 25));
236 #ifdef CONFIG_VISION2_HW_1_0
237 imx_iomux_v3_setup_multiple_pads(fec_pads,
238 ARRAY_SIZE(fec_pads));
243 static void power_init_mx51(void)
249 ret = pmic_init(I2C_PMIC);
253 p = pmic_get("FSL_PMIC");
257 /* Write needed to Power Gate 2 register */
258 pmic_reg_read(p, REG_POWER_MISC, &val);
260 /* enable VCAM with 2.775V to enable read from PMIC */
261 val = VCAMCONFIG | VCAMEN;
262 pmic_reg_write(p, REG_MODE_1, val);
265 * Set switchers in Auto in NORMAL mode & STANDBY mode
266 * Setup the switcher mode for SW1 & SW2
268 pmic_reg_read(p, REG_SW_4, &val);
269 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
270 (SWMODE_MASK << SWMODE2_SHIFT)));
271 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
272 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
273 pmic_reg_write(p, REG_SW_4, val);
275 /* Setup the switcher mode for SW3 & SW4 */
276 pmic_reg_read(p, REG_SW_5, &val);
277 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
278 (SWMODE_MASK << SWMODE3_SHIFT));
279 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
280 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
281 pmic_reg_write(p, REG_SW_5, val);
284 /* Set VGEN3 to 1.8V, VCAM to 3.0V */
285 pmic_reg_read(p, REG_SETTING_0, &val);
286 val &= ~(VCAM_MASK | VGEN3_MASK);
288 pmic_reg_write(p, REG_SETTING_0, val);
290 /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
291 pmic_reg_read(p, REG_SETTING_1, &val);
292 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
293 val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
294 pmic_reg_write(p, REG_SETTING_1, val);
296 /* Configure VGEN3 and VCAM regulators to use external PNP */
297 val = VGEN3CONFIG | VCAMCONFIG;
298 pmic_reg_write(p, REG_MODE_1, val);
301 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
302 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
303 VVIDEOEN | VAUDIOEN | VSDEN;
304 pmic_reg_write(p, REG_MODE_1, val);
306 pmic_reg_read(p, REG_POWER_CTL2, &val);
308 pmic_reg_write(p, REG_POWER_CTL2, val);
315 static void setup_gpios(void)
317 static const iomux_v3_cfg_t gpio_pads_1[] = {
318 NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
319 PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
320 NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
321 PAD_CTL_DSE_MED), /* DAB Display EN */
322 NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
323 PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
326 static const iomux_v3_cfg_t gpio_pads_2[] = {
327 NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
328 PAD_CTL_DSE_MED), /* Display2 TxEN */
329 NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
330 PAD_CTL_DSE_MED), /* DAB Light EN */
331 NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
332 PAD_CTL_DSE_MED), /* AUDIO_MUTE */
333 NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
334 PAD_CTL_DSE_MED), /* SPARE_OUT */
335 NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
336 PAD_CTL_DSE_MED), /* BEEPER_EN */
337 NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
338 PAD_CTL_DSE_MED), /* POWER_OFF */
339 NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
340 PAD_CTL_DSE_MED), /* FRAM_WE */
341 NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
342 PAD_CTL_DSE_MED), /* EXPANSION_EN */
343 MX51_PAD_GPIO1_2__PWM1_PWMO,
348 imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
350 /* Now we need to trigger the watchdog */
353 imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
356 * Set GPIO1_4 to high and output; it is used to reset
357 * the system on reboot
359 gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
361 gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
362 for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
363 gpio_direction_output(i, 0);
365 gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
367 /* Set POWER_OFF high */
368 gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
370 gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
372 gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
374 gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
379 static void setup_fec(void)
381 static const iomux_v3_cfg_t fec_pads[] = {
382 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
383 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
384 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
385 MX51_PAD_NANDF_CS3__FEC_MDC,
386 NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
387 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
388 NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
389 MX51_PAD_NANDF_D9__FEC_RDATA0,
390 MX51_PAD_NANDF_CS6__FEC_TDATA3,
391 MX51_PAD_NANDF_CS5__FEC_TDATA2,
392 MX51_PAD_NANDF_CS4__FEC_TDATA1,
393 MX51_PAD_NANDF_D8__FEC_TDATA0,
394 MX51_PAD_NANDF_CS7__FEC_TX_EN,
395 MX51_PAD_NANDF_CS2__FEC_TX_ER,
396 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
397 NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
398 NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
399 MX51_PAD_EIM_CS5__FEC_CRS,
400 MX51_PAD_EIM_CS4__FEC_RX_ER,
401 NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
404 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
407 struct fsl_esdhc_cfg esdhc_cfg[1] = {
408 {MMC_SDHC1_BASE_ADDR},
411 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
413 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
415 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
416 *cd = gpio_get_value(IMX_GPIO_NR(1, 0));
423 #ifdef CONFIG_FSL_ESDHC
424 int board_mmc_init(bd_t *bis)
426 static const iomux_v3_cfg_t sd1_pads[] = {
427 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
428 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
429 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
430 PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
431 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
432 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
433 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
434 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
435 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
436 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
437 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
438 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
439 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
440 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
443 imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
445 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
446 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
450 void lcd_enable(void)
452 static const iomux_v3_cfg_t lcd_pads[] = {
453 MX51_PAD_DI1_PIN2__DI1_PIN2,
454 MX51_PAD_DI1_PIN3__DI1_PIN3,
459 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
461 gpio_set_value(IMX_GPIO_NR(1, 2), 1);
462 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
465 ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
467 puts("LCD cannot be configured\n");
470 int board_early_init_f(void)
474 init_drive_strength();
476 /* Setup debug led */
477 gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
478 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
479 PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
481 /* wait a little while to give the pll time to settle */
494 static void backlight(int on)
497 gpio_set_value(IMX_GPIO_NR(3, 1), 1);
499 gpio_set_value(IMX_GPIO_NR(3, 4), 1);
501 gpio_set_value(IMX_GPIO_NR(3, 1), 0);
502 gpio_set_value(IMX_GPIO_NR(3, 4), 0);
508 /* address of boot parameters */
509 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
518 int board_late_init(void)
522 reset_peripherals(1);
524 reset_peripherals(0);
527 /* Early revisions require a second reset */
528 #ifdef CONFIG_VISION2_HW_1_0
529 reset_peripherals(1);
531 reset_peripherals(0);
539 * Do not overwrite the console
540 * Use always serial for U-Boot console
542 int overwrite_console(void)
549 puts("Board: TTControl Vision II CPU V\n");
554 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
559 return cmd_usage(cmdtp);
561 on = (strcmp(argv[1], "on") == 0);
568 lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,