2 * (C) Copyright 2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/mx35.h>
27 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
28 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
29 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
31 .endm // nfc_cmd_input
35 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
36 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
37 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
39 .endm // do_addr_input
41 .section ".text.load", "x"
44 ldr r2, U_BOOT_NAND_START
45 1: ldmia r0!, {r3-r10}
51 ldr r2, U_BOOT_NAND_START
68 mov r0, #NFC_BASE_ADDR
70 ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
74 ldr r7, =CCM_BASE_ADDR
75 ldr r1, [r7, #CLKCTL_RCSR]
88 orrne r1, r1, #0x100 /*2KB page size*/
89 biceq r1, r1, #0x100 /*512B page size*/
90 movne r2, #32 /*64 bytes*/
91 moveq r2, #8 /*16 bytes*/
95 bicne r3, r3, #1 /*Enable 8bit ECC mode*/
96 movne r2, #109 /*218 bytes*/
97 moveq r2, #64 /*128 bytes*/
99 str r1, [r7, #CLKCTL_RCSR]
100 strh r2, [r12, #ECC_RSLT_SPARE_AREA_REG_OFF]
101 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
103 //unlock internal buffer
105 strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
108 strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF]
110 strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF]
112 strh r3, [r12, #NF_WR_PROT_REG_OFF]
114 /* r0: NFC base address. RAM buffer base address. [constantly]
115 * r1: starting flash address to be copied. [constantly]
116 * r2: page size. [Doesn't change]
117 * r3: used as argument.
118 * r11: starting SDRAM address for copying. [Updated constantly].
119 * r12: NFC register base address. [constantly].
120 * r13: end of SDRAM address for copying. [Doesn't change].
124 ldr r3, [r7, #CLKCTL_RCSR]
129 mov r1, #0x800 /*Strange Why is not 4K offset*/
132 1: /*Update the indicator of copy area */
133 ldr r11, U_BOOT_NAND_START
134 add r13, r11, #0x00088000; /*512K + 32K*/
146 do_addr_input //1st addr cycle
148 do_addr_input //2nd addr cycle
150 do_addr_input //3rd addr cycle
152 do_addr_input //4th addr cycle
153 b end_of_nfc_addr_ops
157 do_addr_input //1st addr cycle
159 do_addr_input //2nd addr cycle
161 do_addr_input //3rd addr cycle
163 do_addr_input //4th addr cycle
165 do_addr_input //5th addr cycle
169 b end_of_nfc_addr_ops
173 do_addr_input //1st addr cycle
175 do_addr_input //2nd addr cycle
177 do_addr_input //3rd addr cycle
179 do_addr_input //4th addr cycle
181 do_addr_input //5th addr cycle
190 // Check if x16/2kb page
192 bhi nfc_addr_data_output_done_4k
193 beq nfc_addr_data_output_done_2k
194 beq nfc_addr_data_output_done_512
196 // check for bad block
197 // mov r3, r1, lsl #(32-17) // get rid of block number
198 // cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
199 b nfc_addr_data_output_done
201 nfc_addr_data_output_done_4k:
203 b nfc_addr_data_output_done
205 nfc_addr_data_output_done_2k:
207 // check for bad block
208 //TODO mov r3, r1, lsl #(32-17) // get rid of block number
209 // cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
210 b nfc_addr_data_output_done
212 nfc_addr_data_output_done_512:
213 // check for bad block
214 // TODO mov r3, r1, lsl #(32-5-9) // get rid of block number
215 // TODO cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
217 nfc_addr_data_output_done:
220 add r2, r2, #NFC_BASE_ADDR
221 1: ldmia r0!, {r3-r10}
225 sub r2, r2, #NFC_BASE_ADDR
228 bge NAND_Copy_Main_done
229 // Check if x16/2kb page
231 mov r0, #NFC_BASE_ADDR
242 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
243 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
248 ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
249 orr r3, r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
250 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
252 strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
254 mov r3, #FDO_PAGE_SPARE_VAL
255 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
258 U_BOOT_NAND_START: .word TEXT_BASE
259 CONST_0X0FFF: .word 0x0FFF