2 * Copyright (C) 2008 Embedded Alley Solutions Inc.
4 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
6 * Freescale MX23 SSP/SPI driver
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <asm/arch/spi.h>
25 #define SPI_NUM_BUSES 2
26 #define SPI_NUM_SLAVES 3
28 /* Initalized in spi_init() depending on SSP port configuration */
29 static unsigned long ssp_bases[SPI_NUM_BUSES];
31 /* Set in spi_set_cfg() depending on which SSP port is being used */
32 static unsigned long ssp_base = SSP1_BASE;
35 * Init SSP port: SSP1 (@bus = 0) or SSP2 (@bus == 1)
37 static void ssp_spi_init(unsigned int bus)
42 if (bus >= SPI_NUM_BUSES) {
43 printf("SPI bus %d doesn't exist\n", bus);
47 ssp_base = ssp_bases[bus];
52 REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
53 while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_SFTRST)
57 REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE);
59 /* Set SFTRST and wait until CLKGATE is set */
60 REG_SET(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
61 while (!(REG_RD(ssp_base + SSP_CTRL0) & CTRL0_CLKGATE))
64 /* Clear SFTRST and CLKGATE */
65 REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
66 REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE);
69 * Set CLK to desired value
72 spi_div = ((CONFIG_SSP_CLK>>1) + CONFIG_SPI_CLK - 1) / CONFIG_SPI_CLK;
73 val = (2 << TIMING_CLOCK_DIVIDE) | ((spi_div - 1) << TIMING_CLOCK_RATE);
74 REG_WR(ssp_base + SSP_TIMING, val);
76 /* Set transfer parameters */
78 /* Set SSP SPI Master mode and word length to 8 bit */
79 REG_WR(ssp_base + SSP_CTRL1, WORD_LENGTH8 | SSP_MODE_SPI);
81 /* Set BUS_WIDTH to 1 bit and XFER_COUNT to 1 byte */
82 REG_WR(ssp_base + SSP_CTRL0,
83 BUS_WIDTH_SPI1 | (0x1 << CTRL0_XFER_COUNT));
86 * Set BLOCK_SIZE and BLOCK_COUNT to 0, so that XFER_COUNT
87 * reflects number of bytes to send. Disalbe other bits as
90 REG_WR(ssp_base + SSP_CMD0, 0x0);
94 * Init SSP ports, must be called first and only once
98 #ifdef CONFIG_SPI_SSP1
99 ssp_bases[0] = SSP1_BASE;
103 #ifdef CONFIG_SPI_SSP2
104 ssp_bases[1] = SSP2_BASE;
109 void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode)
114 if (bus >= SPI_NUM_BUSES || cs >= SPI_NUM_SLAVES) {
115 printf("SPI device %d:%d doesn't exist", bus, cs);
119 if (ssp_bases[bus] == 0) {
120 printf("SSP port %d isn't in SPI mode\n", bus + 1);
124 /* Set SSP port to use */
125 ssp_base = ssp_bases[bus];
127 /* Set phase and polarity: HW_SSP_CTRL1 */
128 if (mode & SPI_PHASE)
129 set_mask |= CTRL1_PHASE;
131 clr_mask |= CTRL1_PHASE;
133 if (mode & SPI_POLARITY)
134 set_mask |= CTRL1_POLARITY;
136 clr_mask |= CTRL1_POLARITY;
138 REG_SET(ssp_base + SSP_CTRL1, set_mask);
139 REG_CLR(ssp_base + SSP_CTRL1, clr_mask);
141 /* Set SSn number: HW_SSP_CTRL0 */
142 REG_CLR(ssp_base + SSP_CTRL0, SPI_CS_CLR_MASK);
156 REG_SET(ssp_base + SSP_CTRL0, set_mask);
159 /* Read single data byte */
160 static unsigned char spi_read(void)
164 /* Set XFER_LENGTH to 1 */
165 REG_CLR(ssp_base + SSP_CTRL0, 0xffff);
166 REG_SET(ssp_base + SSP_CTRL0, 1);
168 /* Enable READ mode */
169 REG_SET(ssp_base + SSP_CTRL0, CTRL0_READ);
172 REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN);
176 REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER);
178 while (REG_RD(ssp_base + SSP_STATUS) & STATUS_FIFO_EMPTY)
182 b = REG_RD(ssp_base + SSP_DATA) & 0xff;
184 /* Wait until RUN bit is cleared */
185 while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN)
191 /* Write single data byte */
192 static void spi_write(unsigned char b)
194 /* Set XFER_LENGTH to 1 */
195 REG_CLR(ssp_base + SSP_CTRL0, 0xffff);
196 REG_SET(ssp_base + SSP_CTRL0, 1);
198 /* Enable WRITE mode */
199 REG_CLR(ssp_base + SSP_CTRL0, CTRL0_READ);
202 REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN);
204 /* Write data byte */
205 REG_WR(ssp_base + SSP_DATA, b);
208 REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER);
210 /* Wait until RUN bit is cleared */
211 while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN)
215 static void spi_lock_cs(void)
217 REG_CLR(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC);
218 REG_SET(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS);
221 static void spi_unlock_cs(void)
223 REG_CLR(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS);
224 REG_SET(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC);
227 void spi_txrx(const char *dout, unsigned int tx_len, char *din,
228 unsigned int rx_len, unsigned long flags)
232 if (tx_len == 0 && rx_len == 0)
235 if (flags & SPI_START)
238 for (i = 0; i < tx_len; i++) {
240 /* Check if it is last data byte to transfer */
241 if (flags & SPI_STOP && rx_len == 0 && i == tx_len - 1)
247 for (i = 0; i < rx_len; i++) {
249 /* Check if it is last data byte to transfer */
250 if (flags & SPI_STOP && i == rx_len - 1)