2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
4 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <asm/arch/regs-uartdbg.h>
24 DECLARE_GLOBAL_DATA_PTR;
27 * Set baud rate. The settings are always 8n1:
28 * 8 data bits, no parity, 1 stop bit
30 void serial_setbrg(void)
35 /* Disable everything */
36 cr = REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGCR);
37 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0);
39 /* Calculate and set baudrate */
40 quot = (CONFIG_UARTDBG_CLK * 4) / gd->baudrate;
41 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGFBRD, quot & 0x3f);
42 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIBRD, quot >> 6);
44 /* Set 8n1 mode, enable FIFOs */
45 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGLCR_H,
46 BM_UARTDBGLCR_H_WLEN | BM_UARTDBGLCR_H_FEN);
48 /* Enable Debug UART */
49 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, cr);
55 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0);
58 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIMSC, 0);
60 /* Set default baudrate */
64 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR,
65 BM_UARTDBGCR_TXE | BM_UARTDBGCR_RXE | BM_UARTDBGCR_UARTEN);
70 /* Send a character */
71 void serial_putc(const char c)
73 /* Wait for room in TX FIFO */
74 while (REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_TXFF)
77 /* Write the data byte */
78 REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGDR, c);
84 void serial_puts(const char *s)
90 /* Test whether a character is in TX buffer */
93 /* Check if RX FIFO is not empty */
94 return !(REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_RXFE);
97 /* Receive character */
100 /* Wait while TX FIFO is empty */
101 while (REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_RXFE)
105 return REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGDR) & 0xff;