2 * (C) Copyright 2008 Texas Insturments
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
9 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/arch/sys_proto.h>
37 #include <asm/system.h>
40 DECLARE_GLOBAL_DATA_PTR;
44 void l2cache_disable(void);
47 static void cache_flush(void);
52 * setup up stacks if necessary
56 _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
57 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
62 int cleanup_before_linux(void)
67 * this function is called just before we call linux
68 * it prepares the processor for linux
70 * we turn off caches etc ...
74 /* turn off I/D-cache */
78 /* invalidate I-cache */
82 /* turn off L2 cache */
84 /* invalidate L2 cache also */
85 v7_flush_dcache_all(get_device_type());
88 /* mem barrier to sync up things */
89 asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
98 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
100 disable_interrupts();
107 void l2cache_enable()
110 volatile unsigned int j;
112 /* ES2 onwards we can disable/enable L2 ourselves */
113 if (get_cpu_rev() == CPU_3430_ES2) {
114 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
115 __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
116 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
118 /* Save r0, r12 and restore them after usage */
119 __asm__ __volatile__("mov %0, r12":"=r"(j));
120 __asm__ __volatile__("mov %0, r0":"=r"(i));
123 * GP Device ROM code API usage here
124 * r12 = AUXCR Write function and r0 value
126 __asm__ __volatile__("mov r12, #0x3");
127 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
128 __asm__ __volatile__("orr r0, r0, #0x2");
129 /* SMI instruction to call ROM Code API */
130 __asm__ __volatile__(".word 0xE1600070");
131 __asm__ __volatile__("mov r0, %0":"=r"(i));
132 __asm__ __volatile__("mov r12, %0":"=r"(j));
137 void l2cache_disable()
140 volatile unsigned int j;
142 /* ES2 onwards we can disable/enable L2 ourselves */
143 if (get_cpu_rev() == CPU_3430_ES2) {
144 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
145 __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
146 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
148 /* Save r0, r12 and restore them after usage */
149 __asm__ __volatile__("mov %0, r12":"=r"(j));
150 __asm__ __volatile__("mov %0, r0":"=r"(i));
153 * GP Device ROM code API usage here
154 * r12 = AUXCR Write function and r0 value
156 __asm__ __volatile__("mov r12, #0x3");
157 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
158 __asm__ __volatile__("bic r0, r0, #0x2");
159 /* SMI instruction to call ROM Code API */
160 __asm__ __volatile__(".word 0xE1600070");
161 __asm__ __volatile__("mov r0, %0":"=r"(i));
162 __asm__ __volatile__("mov r12, %0":"=r"(j));
166 static void cache_flush(void)
168 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));