2 * (C) Copyright 2008 Texas Insturments
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/system.h>
37 #include <asm/cache.h>
38 #include <asm/cache-cp15.h>
43 #include <asm/arch/sys_proto.h>
47 #define cache_flush(void) \
50 "stmfd sp!, {r0-r5, r7, r9-r11};" \
51 "mrc p15, 1, r0, c0, c0, 1;" /*@ read clidr*/ \
52 /* @ extract loc from clidr */ \
53 "ands r3, r0, #0x7000000;" \
54 /* @ left align loc bit field*/ \
55 "mov r3, r3, lsr #23;" \
56 /* @ if loc is 0, then no need to clean*/ \
57 "beq 555f;" /* finished;" */ \
58 /* @ start clean at cache level 0*/ \
61 /* @ work out 3x current cache level */ \
62 "add r2, r10, r10, lsr #1;" \
63 /* @ extract cache type bits from clidr */ \
64 "mov r1, r0, lsr r2;" \
65 /* @ mask of the bits for current cache only */ \
67 /* @ see what cache we have at this level*/ \
69 /* @ skip if no cache, or just i-cache*/ \
70 "blt 444f;" /* skip;" */ \
71 /* @ select current cache level in cssr*/ \
72 "mcr p15, 2, r10, c0, c0, 0;" \
73 /* @ isb to sych the new cssr&csidr */ \
74 "mcr p15, 0, r10, c7, c5, 4;" \
75 /* @ read the new csidr */ \
76 "mrc p15, 1, r1, c0, c0, 0;" \
77 /* @ extract the length of the cache lines */ \
79 /* @ add 4 (line length offset) */ \
82 /* @ find maximum number on the way size*/ \
83 "ands r4, r4, r1, lsr #3;" \
84 /*"clz r5, r4;" @ find bit position of way size increment*/ \
87 /* @ extract max number of the index size*/ \
88 "ands r7, r7, r1, lsr #13;" \
89 "222:" /* loop2:" */ \
90 /* @ create working copy of max way size*/ \
92 "333:" /* loop3:" */ \
93 /* @ factor way and cache number into r11*/ \
94 "orr r11, r10, r9, lsl r5;" \
95 /* @ factor index number into r11*/ \
96 "orr r11, r11, r7, lsl r2;" \
97 /* @ clean & invalidate by set/way */ \
98 "mcr p15, 0, r11, c7, c14, 2;" \
99 /* @ decrement the way */ \
101 "bge 333b;" /* loop3;" */ \
102 /* @ decrement the index */ \
104 "bge 222b;" /* loop2;" */ \
106 /*@ increment cache number */ \
107 "add r10, r10, #2;" \
109 "bgt 111b;" /* loop1; */ \
110 "555:" /* "finished:" */ \
111 /* @ swith back to cache level 0 */ \
113 /* @ select current cache level in cssr */ \
114 "mcr p15, 2, r10, c0, c0, 0;" \
115 /* @ isb to sych the new cssr&csidr */ \
116 "mcr p15, 0, r10, c7, c5, 4;" \
117 "ldmfd sp!, {r0-r5, r7, r9-r11};" \
118 "666:" /* iflush:" */ \
120 /* @ invalidate I+BTB */ \
121 "mcr p15, 0, r0, c7, c5, 0;" \
123 "mcr p15, 0, r0, c7, c10, 4;" \
126 : "r0" /* Clobber list */ \
130 int cleanup_before_linux(void)
135 * this function is called just before we call linux
136 * it prepares the processor for linux
138 * we turn off caches etc ...
140 disable_interrupts();
145 /* turn off I/D-cache */
147 /* invalidate D-cache */
150 #ifndef CONFIG_L2_OFF
151 /* turn off L2 cache */
153 /* invalidate L2 cache also */
154 v7_flush_dcache_all(get_device_type());
157 /* mem barrier to sync up things */
158 asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
163 #ifndef CONFIG_L2_OFF