2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #ifndef __ARCH_ARM_MACH_MX53_CRM_REGS_H__
20 #define __ARCH_ARM_MACH_MX53_CRM_REGS_H__
22 #define MXC_CCM_BASE CCM_BASE_ADDR
23 #define MXC_DPLL1_BASE PLL1_BASE_ADDR
24 #define MXC_DPLL2_BASE PLL2_BASE_ADDR
25 #define MXC_DPLL3_BASE PLL3_BASE_ADDR
26 #define MXC_DPLL4_BASE PLL4_BASE_ADDR
28 /* PLL Register Offsets */
29 #define MXC_PLL_DP_CTL 0x00
30 #define MXC_PLL_DP_CONFIG 0x04
31 #define MXC_PLL_DP_OP 0x08
32 #define MXC_PLL_DP_MFD 0x0C
33 #define MXC_PLL_DP_MFN 0x10
34 #define MXC_PLL_DP_MFNMINUS 0x14
35 #define MXC_PLL_DP_MFNPLUS 0x18
36 #define MXC_PLL_DP_HFS_OP 0x1C
37 #define MXC_PLL_DP_HFS_MFD 0x20
38 #define MXC_PLL_DP_HFS_MFN 0x24
39 #define MXC_PLL_DP_MFN_TOGC 0x28
40 #define MXC_PLL_DP_DESTAT 0x2c
42 /* PLL Register Bit definitions */
43 #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
44 #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
45 #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
46 #define MXC_PLL_DP_CTL_ADE 0x800
47 #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
48 #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
49 #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
50 #define MXC_PLL_DP_CTL_HFSM 0x80
51 #define MXC_PLL_DP_CTL_PRE 0x40
52 #define MXC_PLL_DP_CTL_UPEN 0x20
53 #define MXC_PLL_DP_CTL_RST 0x10
54 #define MXC_PLL_DP_CTL_RCP 0x8
55 #define MXC_PLL_DP_CTL_PLM 0x4
56 #define MXC_PLL_DP_CTL_BRM0 0x2
57 #define MXC_PLL_DP_CTL_LRF 0x1
59 #define MXC_PLL_DP_CONFIG_BIST 0x8
60 #define MXC_PLL_DP_CONFIG_SJC_CE 0x4
61 #define MXC_PLL_DP_CONFIG_AREN 0x2
62 #define MXC_PLL_DP_CONFIG_LDREQ 0x1
64 #define MXC_PLL_DP_OP_MFI_OFFSET 4
65 #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
66 #define MXC_PLL_DP_OP_PDF_OFFSET 0
67 #define MXC_PLL_DP_OP_PDF_MASK 0xF
69 #define MXC_PLL_DP_MFD_OFFSET 0
70 #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
72 #define MXC_PLL_DP_MFN_OFFSET 0x0
73 #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
75 #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
76 #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
77 #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
78 #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
80 #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
81 #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
83 /* Register addresses of CCM*/
84 #define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
85 #define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
86 #define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
87 #define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
88 #define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
89 #define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
90 #define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
91 #define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
92 #define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
93 #define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
94 #define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
95 #define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
96 #define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
97 #define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
98 #define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
99 #define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
100 #define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
101 #define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
102 #define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
103 #define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
104 #define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
105 #define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
106 #define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
107 #define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
108 #define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
109 #define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
110 #define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
111 #define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
112 #define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
113 #define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
114 #define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
115 #define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
116 #define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
117 #define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x80)
118 #define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
120 /* Define the bits in register CCR */
121 #define MXC_CCM_CCR_COSC_EN (1 << 12)
122 #define MXC_CCM_CCR_CAMP2_EN (1 << 10)
123 #define MXC_CCM_CCR_CAMP1_EN (1 << 9)
124 #define MXC_CCM_CCR_FPM_EN (1 << 8)
125 #define MXC_CCM_CCR_OSCNT_OFFSET (0)
126 #define MXC_CCM_CCR_OSCNT_MASK (0xFF)
128 /* Define the bits in register CCDR */
129 #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21)
130 #define MXC_CCM_CCDR_EMI_HS_INT2_MASK (0x1 << 20)
131 #define MXC_CCM_CCDR_EMI_HS_INT1_MASK (0x1 << 19)
132 #define MXC_CCM_CCDR_EMI_HS_SLOW_MASK (0x1 << 18)
133 #define MXC_CCM_CCDR_EMI_HS_FAST_MASK (0x1 << 17)
134 #define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
136 /* Define the bits in register CSR */
137 #define MXC_CCM_CSR_COSR_READY (1 << 5)
138 #define MXC_CCM_CSR_LVS_VALUE (1 << 4)
139 #define MXC_CCM_CSR_CAMP2_READY (1 << 3)
140 #define MXC_CCM_CSR_CAMP1_READY (1 << 2)
141 #define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1)
142 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
144 /* Define the bits in register CCSR */
145 #define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10)
146 #define MXC_CCM_CCSR_LP_APM_SEL_OFFSET 10
147 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (1 << 9)
148 #define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
149 #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
150 #define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
151 #define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
152 #define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
153 #define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
154 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
155 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
156 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
158 /* Define the bits in register CACRR */
159 #define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
160 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
162 /* Define the bits in register CBCDR */
163 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
164 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
165 #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
166 #define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
167 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
168 #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
169 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
170 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
171 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
172 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
173 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
174 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
175 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
176 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
177 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
178 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
179 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
180 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
181 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
182 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
183 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
184 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
185 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
186 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
188 /* Define the bits in register CBCMR */
189 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
190 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
191 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
192 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
193 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
194 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
195 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
196 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
197 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
198 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
199 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
200 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
201 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
202 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
203 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
204 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL_OFFSET (1)
205 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
206 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL_OFFSET (0)
208 /* Define the bits in register CSCMR1 */
209 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
210 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
211 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
212 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
213 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
214 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
215 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
216 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
217 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
218 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
219 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
220 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
221 #define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 19)
222 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
223 #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16)
224 #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16)
225 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
226 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
227 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
228 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
229 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
230 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
231 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
232 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
233 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
234 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
235 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
236 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
237 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
238 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
239 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
241 /* Define the bits in register CSCMR2 */
242 #define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
243 #define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
244 #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
245 #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
246 #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
247 #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
248 #define MXC_CCM_CSCMR2_ASRC_CLK_SEL (1<<21)
249 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19)
250 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
251 #define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET (16)
252 #define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK (0x7 << 16)
253 #define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET (14)
254 #define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK (0x3 << 14)
255 #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
256 #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
257 #define MXC_CCM_CSCMR2_LBD_DI1_IPU_DIV (0x1 << 11)
258 #define MXC_CCM_CSCMR2_LBD_DI0_IPU_DIV (0x1 << 10)
259 #define MXC_CCM_CSCMR2_LBD_DI1_CLK_SEL (0x1 << 9)
260 #define MXC_CCM_CSCMR2_LBD_DI0_CLK_SEL (0x1 << 8)
261 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (6)
262 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 6)
263 #define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
264 #define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
265 #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
266 #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
267 #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
268 #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
270 /* Define the bits in register CSCDR1 */
271 #define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET (22)
272 #define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK (0x7 << 22)
273 #define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET (19)
274 #define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK (0x7 << 19)
275 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
276 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
277 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
278 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
279 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
280 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
281 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
282 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
283 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
284 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
285 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
286 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
287 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
288 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
290 /* Define the bits in register CS1CDR and CS2CDR */
291 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25)
292 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
293 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
294 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
295 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
296 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
297 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9)
298 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x7 << 9)
299 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
300 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
301 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
302 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
304 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
305 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
306 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
307 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
308 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
309 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
310 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
311 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
313 /* Define the bits in register CDCDR */
314 #define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
315 #define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
316 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
317 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
318 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
319 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
320 #define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET (16)
321 #define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK (0x7 << 16)
322 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
323 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
324 #define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET (6)
325 #define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK (0x7 << 6)
326 #define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
327 #define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
328 #define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
329 #define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
331 /* Define the bits in register CHSCCDR */
332 #define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET (6)
333 #define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK (0x3 << 6)
334 #define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET (4)
335 #define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK (0x3 << 4)
336 #define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET (2)
337 #define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK (0x3 << 2)
338 #define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET (0)
339 #define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK (0x3)
341 /* Define the bits in register CSCDR2 */
342 #define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET (28)
343 #define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK (0x7 << 28)
344 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
345 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
346 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
347 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
348 #define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9)
349 #define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9)
350 #define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6)
351 #define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6)
352 #define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0)
353 #define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK (0x3F)
355 /* Define the bits in register CSCDR3 */
356 #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
357 #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
358 #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
359 #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
360 #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
361 #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
362 #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
363 #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
365 /* Define the bits in register CSCDR4 */
366 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
367 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
368 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
369 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
370 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
371 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
372 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
373 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
375 /* Define the bits in register CDHIPR */
376 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
377 #define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
378 #define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
379 #define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
380 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
381 #define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
382 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
383 #define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
384 #define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
385 #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
387 /* Define the bits in register CDCR */
388 #define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
389 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
390 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
392 /* Define the bits in register CLPCR */
393 #define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS (0x1 << 27)
394 #define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS (0x1 << 27)
395 #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 26)
396 #define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
397 #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24)
398 #define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS (0x1 << 23)
399 #define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS (0x1 << 22)
400 #define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS (0x1 << 21)
401 #define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS (0x1 << 20)
402 #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
403 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
404 #define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
405 #define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
406 #define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
407 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
408 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
409 #define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
410 #define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
411 #define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
412 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
413 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
414 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
415 #define MXC_CCM_CLPCR_LPM_OFFSET (0)
416 #define MXC_CCM_CLPCR_LPM_MASK (0x3)
418 /* Define the bits in register CISR */
419 #define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26)
420 #define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25)
421 #define MXC_CCM_CISR_EMI_CLK_SEL_LOADED (0x1 << 23)
422 #define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22)
423 #define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
424 #define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
425 #define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
426 #define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
427 #define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
428 #define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
429 #define MXC_CCM_CISR_COSC_READY (0x1 << 6)
430 #define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
431 #define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
432 #define MXC_CCM_CISR_FPM_READY (0x1 << 3)
433 #define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
434 #define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
435 #define MXC_CCM_CISR_LRF_PLL1 (0x1)
437 /* Define the bits in register CIMR */
438 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26)
439 #define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25)
440 #define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED (0x1 << 23)
441 #define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22)
442 #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
443 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (0x1 << 20)
444 #define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED (0x1 << 19)
445 #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
446 #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
447 #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
448 #define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6)
449 #define MXC_CCM_CIMR_MASK_CAMP2_READY (0x1 << 5)
450 #define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4)
451 #define MXC_CCM_CIMR_MASK_LRF_PLL4 (0x1 << 3)
452 #define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
453 #define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
454 #define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
456 /* Define the bits in register CCOSR */
457 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
458 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
459 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
460 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
461 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
462 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
463 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
464 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
465 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
466 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
468 /* Define the bits in registers CGPR */
469 #define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL (0x1 << 24)
470 #define MXC_CCM_CGPR_ARM_ASYNC_REF_EN (0x1 << 23)
471 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
472 #define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
473 #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
474 #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
476 /* Define the bits in registers CCGRx */
477 #define MXC_CCM_CCGR_CG_MASK 0x3
479 #define MXC_CCM_CCGR0_CG15_OFFSET 30
480 #define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
481 #define MXC_CCM_CCGR0_CG14_OFFSET 28
482 #define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
483 #define MXC_CCM_CCGR0_CG13_OFFSET 26
484 #define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
485 #define MXC_CCM_CCGR0_CG12_OFFSET 24
486 #define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
487 #define MXC_CCM_CCGR0_CG11_OFFSET 22
488 #define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
489 #define MXC_CCM_CCGR0_CG10_OFFSET 20
490 #define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
491 #define MXC_CCM_CCGR0_CG9_OFFSET 18
492 #define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
493 #define MXC_CCM_CCGR0_CG8_OFFSET 16
494 #define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
495 #define MXC_CCM_CCGR0_CG7_OFFSET 14
496 #define MXC_CCM_CCGR0_CG6_OFFSET 12
497 #define MXC_CCM_CCGR0_CG5_OFFSET 10
498 #define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
499 #define MXC_CCM_CCGR0_CG4_OFFSET 8
500 #define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
501 #define MXC_CCM_CCGR0_CG3_OFFSET 6
502 #define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
503 #define MXC_CCM_CCGR0_CG2_OFFSET 4
504 #define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
505 #define MXC_CCM_CCGR0_CG1_OFFSET 2
506 #define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
507 #define MXC_CCM_CCGR0_CG0_OFFSET 0
508 #define MXC_CCM_CCGR0_CG0_MASK 0x3
510 #define MXC_CCM_CCGR1_CG15_OFFSET 30
511 #define MXC_CCM_CCGR1_CG14_OFFSET 28
512 #define MXC_CCM_CCGR1_CG13_OFFSET 26
513 #define MXC_CCM_CCGR1_CG12_OFFSET 24
514 #define MXC_CCM_CCGR1_CG11_OFFSET 22
515 #define MXC_CCM_CCGR1_CG10_OFFSET 20
516 #define MXC_CCM_CCGR1_CG9_OFFSET 18
517 #define MXC_CCM_CCGR1_CG8_OFFSET 16
518 #define MXC_CCM_CCGR1_CG7_OFFSET 14
519 #define MXC_CCM_CCGR1_CG6_OFFSET 12
520 #define MXC_CCM_CCGR1_CG5_OFFSET 10
521 #define MXC_CCM_CCGR1_CG4_OFFSET 8
522 #define MXC_CCM_CCGR1_CG3_OFFSET 6
523 #define MXC_CCM_CCGR1_CG2_OFFSET 4
524 #define MXC_CCM_CCGR1_CG1_OFFSET 2
525 #define MXC_CCM_CCGR1_CG0_OFFSET 0
527 #define MXC_CCM_CCGR2_CG15_OFFSET 30
528 #define MXC_CCM_CCGR2_CG14_OFFSET 28
529 #define MXC_CCM_CCGR2_CG13_OFFSET 26
530 #define MXC_CCM_CCGR2_CG12_OFFSET 24
531 #define MXC_CCM_CCGR2_CG11_OFFSET 22
532 #define MXC_CCM_CCGR2_CG10_OFFSET 20
533 #define MXC_CCM_CCGR2_CG9_OFFSET 18
534 #define MXC_CCM_CCGR2_CG8_OFFSET 16
535 #define MXC_CCM_CCGR2_CG7_OFFSET 14
536 #define MXC_CCM_CCGR2_CG6_OFFSET 12
537 #define MXC_CCM_CCGR2_CG5_OFFSET 10
538 #define MXC_CCM_CCGR2_CG4_OFFSET 8
539 #define MXC_CCM_CCGR2_CG3_OFFSET 6
540 #define MXC_CCM_CCGR2_CG2_OFFSET 4
541 #define MXC_CCM_CCGR2_CG1_OFFSET 2
542 #define MXC_CCM_CCGR2_CG0_OFFSET 0
544 #define MXC_CCM_CCGR3_CG15_OFFSET 30
545 #define MXC_CCM_CCGR3_CG14_OFFSET 28
546 #define MXC_CCM_CCGR3_CG13_OFFSET 26
547 #define MXC_CCM_CCGR3_CG12_OFFSET 24
548 #define MXC_CCM_CCGR3_CG11_OFFSET 22
549 #define MXC_CCM_CCGR3_CG10_OFFSET 20
550 #define MXC_CCM_CCGR3_CG9_OFFSET 18
551 #define MXC_CCM_CCGR3_CG8_OFFSET 16
552 #define MXC_CCM_CCGR3_CG7_OFFSET 14
553 #define MXC_CCM_CCGR3_CG6_OFFSET 12
554 #define MXC_CCM_CCGR3_CG5_OFFSET 10
555 #define MXC_CCM_CCGR3_CG4_OFFSET 8
556 #define MXC_CCM_CCGR3_CG3_OFFSET 6
557 #define MXC_CCM_CCGR3_CG2_OFFSET 4
558 #define MXC_CCM_CCGR3_CG1_OFFSET 2
559 #define MXC_CCM_CCGR3_CG0_OFFSET 0
561 #define MXC_CCM_CCGR4_CG15_OFFSET 30
562 #define MXC_CCM_CCGR4_CG14_OFFSET 28
563 #define MXC_CCM_CCGR4_CG13_OFFSET 26
564 #define MXC_CCM_CCGR4_CG12_OFFSET 24
565 #define MXC_CCM_CCGR4_CG11_OFFSET 22
566 #define MXC_CCM_CCGR4_CG10_OFFSET 20
567 #define MXC_CCM_CCGR4_CG9_OFFSET 18
568 #define MXC_CCM_CCGR4_CG8_OFFSET 16
569 #define MXC_CCM_CCGR4_CG7_OFFSET 14
570 #define MXC_CCM_CCGR4_CG6_OFFSET 12
571 #define MXC_CCM_CCGR4_CG5_OFFSET 10
572 #define MXC_CCM_CCGR4_CG4_OFFSET 8
573 #define MXC_CCM_CCGR4_CG3_OFFSET 6
574 #define MXC_CCM_CCGR4_CG2_OFFSET 4
575 #define MXC_CCM_CCGR4_CG1_OFFSET 2
576 #define MXC_CCM_CCGR4_CG0_OFFSET 0
578 #define MXC_CCM_CCGR5_CG15_OFFSET 30
579 #define MXC_CCM_CCGR5_CG14_OFFSET 28
580 #define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
581 #define MXC_CCM_CCGR5_CG13_OFFSET 26
582 #define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
583 #define MXC_CCM_CCGR5_CG12_OFFSET 24
584 #define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
585 #define MXC_CCM_CCGR5_CG11_OFFSET 22
586 #define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
587 #define MXC_CCM_CCGR5_CG10_OFFSET 20
588 #define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
589 #define MXC_CCM_CCGR5_CG9_OFFSET 18
590 #define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
591 #define MXC_CCM_CCGR5_CG8_OFFSET 16
592 #define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
593 #define MXC_CCM_CCGR5_CG7_OFFSET 14
594 #define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
595 #define MXC_CCM_CCGR5_CG6_OFFSET 12
596 #define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
597 #define MXC_CCM_CCGR5_CG5_OFFSET 10
598 #define MXC_CCM_CCGR5_CG4_OFFSET 8
599 #define MXC_CCM_CCGR5_CG3_OFFSET 6
600 #define MXC_CCM_CCGR5_CG2_OFFSET 4
601 #define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
602 #define MXC_CCM_CCGR5_CG1_OFFSET 2
603 #define MXC_CCM_CCGR5_CG0_OFFSET 0
605 #define MXC_CCM_CCGR6_CG15_OFFSET 30
606 #define MXC_CCM_CCGR6_CG14_OFFSET 28
607 #define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
608 #define MXC_CCM_CCGR6_CG13_OFFSET 26
609 #define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
610 #define MXC_CCM_CCGR6_CG12_OFFSET 24
611 #define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
612 #define MXC_CCM_CCGR6_CG11_OFFSET 22
613 #define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
614 #define MXC_CCM_CCGR6_CG10_OFFSET 20
615 #define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
616 #define MXC_CCM_CCGR6_CG9_OFFSET 18
617 #define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
618 #define MXC_CCM_CCGR6_CG8_OFFSET 16
619 #define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
620 #define MXC_CCM_CCGR6_CG7_OFFSET 14
621 #define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
622 #define MXC_CCM_CCGR6_CG6_OFFSET 12
623 #define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
624 #define MXC_CCM_CCGR6_CG5_OFFSET 10
625 #define MXC_CCM_CCGR6_CG4_OFFSET 8
626 #define MXC_CCM_CCGR6_CG3_OFFSET 6
627 #define MXC_CCM_CCGR6_CG2_OFFSET 4
628 #define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
629 #define MXC_CCM_CCGR6_CG1_OFFSET 2
630 #define MXC_CCM_CCGR6_CG0_OFFSET 0
632 #define MXC_CCM_CCGR7_CG15_OFFSET 30
633 #define MXC_CCM_CCGR7_CG14_OFFSET 28
634 #define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
635 #define MXC_CCM_CCGR7_CG13_OFFSET 26
636 #define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
637 #define MXC_CCM_CCGR7_CG12_OFFSET 24
638 #define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
639 #define MXC_CCM_CCGR7_CG11_OFFSET 22
640 #define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
641 #define MXC_CCM_CCGR7_CG10_OFFSET 20
642 #define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
643 #define MXC_CCM_CCGR7_CG9_OFFSET 18
644 #define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
645 #define MXC_CCM_CCGR7_CG8_OFFSET 16
646 #define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
647 #define MXC_CCM_CCGR7_CG7_OFFSET 14
648 #define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
649 #define MXC_CCM_CCGR7_CG6_OFFSET 12
650 #define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
651 #define MXC_CCM_CCGR7_CG5_OFFSET 10
652 #define MXC_CCM_CCGR7_CG4_OFFSET 8
653 #define MXC_CCM_CCGR7_CG3_OFFSET 6
654 #define MXC_CCM_CCGR7_CG2_OFFSET 4
655 #define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
656 #define MXC_CCM_CCGR7_CG1_OFFSET 2
657 #define MXC_CCM_CCGR7_CG0_OFFSET 0
659 #define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR))
660 #define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80)
661 #define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100)
662 #define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180)
663 #define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4)
664 #define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220)
665 #define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240)
666 #define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260)
667 #define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280)
668 #define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0)
669 #define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0)
670 #define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0)
671 #define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0)
672 #define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300)
675 #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
676 #define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
677 #define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
678 #define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
679 #define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
680 #define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
681 #define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
682 #define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
683 #define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
684 #define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
685 #define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
686 #define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
687 #define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
688 #define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
689 #define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
690 #define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
691 #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
694 #define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE)
695 #define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04)
696 #define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08)
697 #define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C)
698 #define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10)
699 #define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14)
700 #define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18)
701 #define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C)
704 #define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
705 #define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
706 #define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
707 #define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
708 #define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
711 #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
712 #define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
713 #define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
714 #define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
715 #define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
716 #define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
718 #define MXC_PGCR_PCR 1
719 #define MXC_SRPGCR_PCR 1
720 #define MXC_EMPGCR_PCR 1
721 #define MXC_PGSR_PSR 1
724 #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
725 #define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
728 #define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
729 #define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
730 #define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
732 #define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
733 #define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
734 #define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
736 #define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
737 #define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
738 #define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
740 #define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
741 #define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
742 #define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
744 #define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
745 #define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
746 #define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
748 #define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
749 #define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
750 #define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
752 #endif /* __ARCH_ARM_MACH_MX53_CRM_REGS_H__ */