3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
19 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 defined(CONFIG_MPC5XXX_FEC)
23 static void tfifo_print(mpc5xxx_fec_priv *fec);
24 static void rfifo_print(mpc5xxx_fec_priv *fec);
28 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
31 /********************************************************************/
32 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
38 * the receive ring is located right after the transmit one
40 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
41 data = (char *)malloc(FEC_MAX_PKT_SIZE);
43 printf ("RBD INIT FAILED\n");
46 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
47 fec->rbdBase[ix].dataLength = 0;
48 fec->rbdBase[ix].dataPointer = (uint32)data;
52 * have the last RBD to close the ring
54 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
60 /********************************************************************/
61 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
65 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
66 fec->tbdBase[ix].status = 0;
70 * Have the last TBD to close the ring
72 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
75 * Initialize some indices
78 fec->usedTbdIndex = 0;
79 fec->cleanTbdNum = FEC_TBD_NUM;
82 /********************************************************************/
83 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, FEC_RBD * pRbd)
86 * Reset buffer descriptor as empty
88 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
89 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
91 pRbd->status = FEC_RBD_EMPTY;
96 * Now, we have an empty RxBD, restart the SmartDMA receive task
98 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
103 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
106 /********************************************************************/
107 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
112 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
113 fec->cleanTbdNum, fec->usedTbdIndex);
117 * process all the consumed TBDs
119 while (fec->cleanTbdNum < FEC_TBD_NUM) {
120 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
121 if (pUsedTbd->status & FEC_TBD_READY) {
123 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
129 * clean this buffer descriptor
131 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
132 pUsedTbd->status = FEC_TBD_WRAP;
134 pUsedTbd->status = 0;
137 * update some indeces for a correct handling of the TBD ring
140 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
144 /********************************************************************/
145 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
147 uint8 currByte; /* byte for which to compute the CRC */
148 int byte; /* loop - counter */
149 int bit; /* loop - counter */
150 uint32 crc = 0xffffffff; /* initial value */
153 * The algorithm used is the following:
154 * we loop on each of the six bytes of the provided address,
155 * and we compute the CRC by left-shifting the previous
156 * value by one position, so that each bit in the current
157 * byte of the address may contribute the calculation. If
158 * the latter and the MSB in the CRC are different, then
159 * the CRC value so computed is also ex-ored with the
160 * "polynomium generator". The current byte of the address
161 * is also shifted right by one bit at each iteration.
162 * This is because the CRC generatore in hardware is implemented
163 * as a shift-register with as many ex-ores as the radixes
164 * in the polynomium. This suggests that we represent the
165 * polynomiumm itself as a 32-bit constant.
167 for (byte = 0; byte < 6; byte++) {
168 currByte = mac[byte];
169 for (bit = 0; bit < 8; bit++) {
170 if ((currByte & 0x01) ^ (crc & 0x01)) {
172 crc = crc ^ 0xedb88320;
183 * Set individual hash table register
186 fec->eth->iaddr1 = (1 << (crc - 32));
187 fec->eth->iaddr2 = 0;
189 fec->eth->iaddr1 = 0;
190 fec->eth->iaddr2 = (1 << crc);
194 * Set physical address
196 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
197 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
200 /********************************************************************/
201 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
203 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
204 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
205 const uint8 phyAddr = 0; /* Only one PHY */
208 printf ("mpc5xxx_fec_init... Begin\n");
212 * Initialize RxBD/TxBD rings
214 mpc5xxx_fec_rbd_init(fec);
215 mpc5xxx_fec_tbd_init(fec);
218 * Initialize GPIO pins
220 if (fec->xcv_type == SEVENWIRE) {
221 /* 10MBit with 7-wire operation */
222 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
224 /* 100MBit with MD operation */
225 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
229 * Clear FEC-Lite interrupt event register(IEVENT)
231 fec->eth->ievent = 0xffffffff;
234 * Set interrupt mask register
236 fec->eth->imask = 0x00000000;
239 * Set FEC-Lite receive control register(R_CNTRL):
241 if (fec->xcv_type == SEVENWIRE) {
243 * Frame length=1518; 7-wire mode
245 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
248 * Frame length=1518; MII mode;
250 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
253 if (fec->xcv_type == SEVENWIRE) {
255 * Set FEC-Lite transmit control register(X_CNTRL):
257 /*fec->eth->x_cntrl = 0x00000002; */ /* half-duplex, heartbeat */
258 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
260 /*fec->eth->x_cntrl = 0x00000006; */ /* full-duplex, heartbeat */
261 fec->eth->x_cntrl = 0x00000004; /* full-duplex, heartbeat disabled */
264 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock(25Mhz)
265 * and do not drop the Preamble.
267 fec->eth->mii_speed = (0x5 << 1); /* No MII for 7-wire mode */
271 * Set Opcode/Pause Duration Register
273 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
276 * Set Rx FIFO alarm and granularity value
278 fec->eth->rfifo_cntrl = 0x0c000000;
279 fec->eth->rfifo_alarm = 0x0000030c;
281 if (fec->eth->rfifo_status & 0x00700000 ) {
282 printf("mpc5xxx_fec_init() RFIFO error\n");
287 * Set Tx FIFO granularity value
289 fec->eth->tfifo_cntrl = 0x0c000000;
291 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
292 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
296 * Set transmit fifo watermark register(X_WMRK), default = 64
298 fec->eth->tfifo_alarm = 0x00000080;
299 fec->eth->x_wmrk = 0x2;
302 * Set individual address filter for unicast address
303 * and set physical address registers.
305 mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
308 * Set multicast address filter
310 fec->eth->gaddr1 = 0x00000000;
311 fec->eth->gaddr2 = 0x00000000;
314 * Turn ON cheater FSM: ????
316 fec->eth->xmit_fsm = 0x03000000;
318 #if defined(CONFIG_MPC5200)
320 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
321 * work w/ the current receive task.
323 sdma->PtdCntrl |= 0x00000001;
327 * Set priority of different initiators
329 sdma->IPR0 = 7; /* always */
330 sdma->IPR3 = 6; /* Eth RX */
331 sdma->IPR4 = 5; /* Eth Tx */
334 * Clear SmartDMA task interrupt pending bits
336 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
339 * Set SmartDMA intMask register to enable SmartDMA task interrupts
341 SDMA_INT_ENABLE(FEC_RECV_TASK_NO);
344 * Initialize SmartDMA parameters stored in SRAM
346 *(int *)FEC_TBD_BASE = (int)fec->tbdBase;
347 *(int *)FEC_RBD_BASE = (int)fec->rbdBase;
348 *(int *)FEC_TBD_NEXT = (int)fec->tbdBase;
349 *(int *)FEC_RBD_NEXT = (int)fec->rbdBase;
351 if (fec->xcv_type != SEVENWIRE) {
353 * Initialize PHY(LXT971A):
355 * Generally, on power up, the LXT971A reads its configuration
356 * pins to check for forced operation, If not cofigured for
357 * forced operation, it uses auto-negotiation/parallel detection
358 * to automatically determine line operating conditions.
359 * If the PHY device on the other side of the link supports
360 * auto-negotiation, the LXT971A auto-negotiates with it
361 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
362 * support auto-negotiation, the LXT971A automatically detects
363 * the presence of either link pulses(10Mbps PHY) or Idle
364 * symbols(100Mbps) and sets its operating conditions accordingly.
366 * When auto-negotiation is controlled by software, the following
367 * steps are recommended.
370 * The physical address is dependent on hardware configuration.
377 * Reset PHY, then delay 300ns
379 miiphy_write(phyAddr, 0x0, 0x8000);
382 if (fec->xcv_type == MII10) {
384 * Force 10Base-T, FDX operation
386 printf("Forcing 10 Mbps ethernet link... ");
387 miiphy_read(phyAddr, 0x1, &phyStatus);
389 miiphy_write(fec, phyAddr, 0x0, 0x0100);
391 miiphy_write(phyAddr, 0x0, 0x0180);
394 do { /* wait for link status to go down */
396 if ((timeout--) == 0) {
398 printf("hmmm, should not have waited...");
402 miiphy_read(phyAddr, 0x1, &phyStatus);
406 } while ((phyStatus & 0x0004)); /* !link up */
409 do { /* wait for link status to come back up */
411 if ((timeout--) == 0) {
412 printf("failed. Link is down.\n");
415 miiphy_read(phyAddr, 0x1, &phyStatus);
419 } while (!(phyStatus & 0x0004)); /* !link up */
422 } else { /* MII100 */
424 * Set the auto-negotiation advertisement register bits
426 miiphy_write(phyAddr, 0x4, 0x01e1);
429 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
431 miiphy_write(phyAddr, 0x0, 0x1200);
434 * Wait for AN completion
440 if ((timeout--) == 0) {
442 printf("PHY auto neg 0 failed...\n");
447 if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
449 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
453 } while ((phyStatus & 0x0020) != 0x0020);
456 printf("PHY auto neg complete! \n");
463 * Enable FEC-Lite controller
465 fec->eth->ecntrl |= 0x00000006;
467 if (fec->xcv_type != SEVENWIRE) {
472 for (i = 0; i < 9; i++) {
473 miiphy_read(phyAddr, i, &phyStatus);
474 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
476 for (i = 16; i < 21; i++) {
477 miiphy_read(phyAddr, i, &phyStatus);
478 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
483 * Enable SmartDMA receive task
485 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
488 printf("mpc5xxx_fec_init... Done \n");
494 /********************************************************************/
495 static void mpc5xxx_fec_halt(struct eth_device *dev)
497 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
498 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
499 int counter = 0xffff;
502 if (fec->xcv_type != SEVENWIRE) {
506 for (i = 0; i < 9; i++) {
507 miiphy_read(phyAddr, i, &phyStatus);
508 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
510 for (i = 16; i < 21; i++) {
511 miiphy_read(phyAddr, i, &phyStatus);
512 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
519 * mask FEC chip interrupts
524 * issue graceful stop command to the FEC transmitter if necessary
526 fec->eth->x_cntrl |= 0x00000001;
529 * wait for graceful stop to register
531 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
533 SDMA_INT_DISABLE (FEC_RECV_TASK_NO);
536 * Disable SmartDMA tasks
538 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
539 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
541 #if defined(CONFIG_MPC5200)
543 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
544 * done. It doesn't work w/ the current receive task.
546 sdma->PtdCntrl &= ~0x00000001;
550 * Disable the Ethernet Controller
552 fec->eth->ecntrl &= 0xfffffffd;
555 * Clear FIFO status registers
557 fec->eth->rfifo_status &= 0x00700000;
558 fec->eth->tfifo_status &= 0x00700000;
560 fec->eth->reset_cntrl = 0x01000000;
563 * Issue a reset command to the FEC chip
565 fec->eth->ecntrl |= 0x1;
568 * wait at least 16 clock cycles
573 printf("Ethernet task stopped\n");
578 /********************************************************************/
580 static void tfifo_print(mpc5xxx_fec_priv *fec)
585 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
586 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
588 miiphy_read(phyAddr, 0x1, &phyStatus);
589 printf("\nphyStatus: 0x%04x\n", phyStatus);
590 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
591 printf("ievent: 0x%08x\n", fec->eth->ievent);
592 printf("x_status: 0x%08x\n", fec->eth->x_status);
593 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
595 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
596 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
597 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
598 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
599 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
600 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
604 static void rfifo_print(mpc5xxx_fec_priv *fec)
609 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
610 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
612 miiphy_read(phyAddr, 0x1, &phyStatus);
613 printf("\nphyStatus: 0x%04x\n", phyStatus);
614 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
615 printf("ievent: 0x%08x\n", fec->eth->ievent);
616 printf("x_status: 0x%08x\n", fec->eth->x_status);
617 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
619 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
620 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
621 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
622 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
623 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
624 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
629 /********************************************************************/
631 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
635 * This routine transmits one frame. This routine only accepts
636 * 6-byte Ethernet addresses.
638 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
642 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
647 * Clear Tx BD ring at first
649 mpc5xxx_fec_tbd_scrub(fec);
652 * Check for valid length of data.
654 if ((data_length > 1500) || (data_length <= 0)) {
659 * Check the number of vacant TxBDs.
661 if (fec->cleanTbdNum < 1) {
663 printf("No available TxBDs ...\n");
669 * Get the first TxBD to send the mac header
671 pTbd = &fec->tbdBase[fec->tbdIndex];
672 pTbd->dataLength = data_length;
673 pTbd->dataPointer = (uint32)eth_data;
674 pTbd->status |= FEC_TBD_READY;
675 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
678 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
684 if (fec->xcv_type != SEVENWIRE) {
686 miiphy_read(0, 0x1, &phyStatus);
690 * Enable SmartDMA transmit task
696 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
704 fec->cleanTbdNum -= 1;
706 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
707 printf ("smartDMA ethernet Tx task enabled\n");
710 * wait until frame is sent .
712 while (pTbd->status & FEC_TBD_READY) {
715 printf ("TDB status = %04x\n", pTbd->status);
723 /********************************************************************/
724 static int mpc5xxx_fec_recv(struct eth_device *dev)
727 * This command pulls one frame from the card
729 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
730 FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
731 unsigned long ievent;
736 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
743 * Check if any critical events have happened
745 ievent = fec->eth->ievent;
746 fec->eth->ievent = ievent;
747 if (ievent & 0x20060000) {
748 /* BABT, Rx/Tx FIFO errors */
749 mpc5xxx_fec_halt(dev);
750 mpc5xxx_fec_init(dev, NULL);
753 if (ievent & 0x80000000) {
754 /* Heartbeat error */
755 fec->eth->x_cntrl |= 0x00000001;
757 if (ievent & 0x10000000) {
758 /* Graceful stop complete */
759 if (fec->eth->x_cntrl & 0x00000001) {
760 mpc5xxx_fec_halt(dev);
761 fec->eth->x_cntrl &= ~0x00000001;
762 mpc5xxx_fec_init(dev, NULL);
767 * Do we have data in Rx FIFO?
769 if ((pRbd->status & FEC_RBD_EMPTY) || !(pRbd->status & FEC_RBD_LAST)){
774 * Pass the packet up only if reception was Ok
776 if ((pRbd->dataLength <= 14) || (pRbd->status & FEC_RBD_ERR)) {
777 mpc5xxx_fec_rbd_clean(fec, pRbd);
785 * Get buffer address and size
787 frame = (char *)pRbd->dataPointer;
788 frame_length = pRbd->dataLength;
791 * Pass the buffer to upper layers
793 NetReceive(frame, frame_length);
796 * Reset buffer descriptor as empty
798 mpc5xxx_fec_rbd_clean(fec, pRbd);
804 /********************************************************************/
805 int mpc5xxx_fec_initialize(bd_t * bis)
807 mpc5xxx_fec_priv *fec;
808 struct eth_device *dev;
810 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
811 dev = (struct eth_device *)malloc(sizeof(*dev));
813 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
814 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
815 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
816 #ifdef CONFIG_ICECUBE
817 fec->xcv_type = MII100;
820 dev->priv = (void *)fec;
821 dev->iobase = MPC5XXX_FEC;
822 dev->init = mpc5xxx_fec_init;
823 dev->halt = mpc5xxx_fec_halt;
824 dev->send = mpc5xxx_fec_send;
825 dev->recv = mpc5xxx_fec_recv;
832 /* MII-interface related functions */
833 /********************************************************************/
834 int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
836 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
837 uint32 reg; /* convenient holder for the PHY register */
838 uint32 phy; /* convenient holder for the PHY */
839 int timeout = 0xffff;
842 * reading from any PHY's register is done by properly
843 * programming the FEC's MII data register.
845 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
846 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
848 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
851 * wait for the related interrupt
853 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
857 printf ("Read MDIO failed...\n");
863 * clear mii interrupt bit
865 eth->ievent = 0x00800000;
868 * it's now safe to read the PHY's register
870 *retVal = (uint16) eth->mii_data;
875 /********************************************************************/
876 int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
878 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
879 uint32 reg; /* convenient holder for the PHY register */
880 uint32 phy; /* convenient holder for the PHY */
881 int timeout = 0xffff;
883 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
884 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
886 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
887 FEC_MII_DATA_TA | phy | reg | data);
890 * wait for the MII interrupt
892 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
896 printf ("Write MDIO failed...\n");
902 * clear MII interrupt bit
904 eth->ievent = 0x00800000;
910 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
914 unsigned int crc, count;
920 * crc = 0xffffffff; * The initialized value should be 0xffffffff
924 for (i = len; --i >= 0;) {
926 for (count = 0; count < 8; count++) {
927 if ((c & 0x01) ^ (crc & 0x01)) {
929 crc = crc ^ 0xedb88320;
938 * In big endian system, do byte swaping for crc value
944 #endif /* CONFIG_MPC5XXX_FEC */