2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /* U-Boot - Startup Code for PowerPC based Embedded Boards
28 * The processor starts at 0x00000100 and the code is executed
29 * from flash. The code is organized to be at an other address
30 * in memory, but as long we don't jump around before relocating.
31 * board_init lies at a quite high address and when the cpu has
32 * jumped there, everything is ok.
33 * This works because the cpu gives the FLASH (CS0) the whole
34 * address space at startup, and board_init lies as a echo of
35 * the flash somewhere up there in the memorymap.
37 * board_init will change CS0 to be positioned at the correct
38 * address and (s)dram will be positioned at address 0
44 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
46 #include <ppc_asm.tmpl>
49 #include <asm/cache.h>
52 #ifndef CONFIG_IDENT_STRING
53 #define CONFIG_IDENT_STRING ""
56 /* We don't want the MMU yet.
59 /* FP, Machine Check and Recoverable Interr. */
60 #define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI )
63 * Set up GOT: Global Offset Table
65 * Use r14 to access the GOT
68 GOT_ENTRY(_GOT2_TABLE_)
69 GOT_ENTRY(_FIXUP_TABLE_)
72 GOT_ENTRY(_start_of_vectors)
73 GOT_ENTRY(_end_of_vectors)
74 GOT_ENTRY(transfer_to_handler)
78 #if defined(CONFIG_FADS)
79 GOT_ENTRY(environment)
84 * r3 - 1st arg to board_init(): IMMP pointer
85 * r4 - 2nd arg to board_init(): boot flag
88 .long 0x27051956 /* U-Boot Magic Number */
92 .ascii " (", __DATE__, " - ", __TIME__, ")"
93 .ascii CONFIG_IDENT_STRING, "\0"
98 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
101 . = EXC_OFF_SYS_RESET + 0x10
105 li r21, BOOTFLAG_WARM /* Software reboot */
111 /* Initialize machine status; enable machine check interrupt */
112 /*----------------------------------------------------------------------*/
113 li r3, MSR_KERNEL /* Set FP, ME, RI flags */
115 mtspr SRR1, r3 /* Make SRR1 match MSR */
117 addis r0,0,0x0000 /* lets make sure that r0 is really 0 */
118 mtspr HID0, r0 /* disable I and D caches */
120 mfspr r3, ICR /* clear Interrupt Cause Register */
122 mfmsr r3 /* turn off address translation */
128 sync /* the MMU should be off... */
132 #if defined(CONFIG_BMW)
133 bl early_init_f /* Must be ASM: no stack yet! */
136 * Setup BATs - cannot be done in C since we don't have a stack yet
143 ori r3, r3, (MSR_IR | MSR_DR)
145 #if !defined(CONFIG_BMW)
146 /* Enable and invalidate data cache.
150 ori r3, r3, HID0_DCE | HID0_DCI
157 /* Allocate Initial RAM in data cache.
159 lis r3, CFG_INIT_RAM_ADDR@h
160 ori r3, r3, CFG_INIT_RAM_ADDR@l
168 /* Lock way0 in data cache.
177 #endif /* !CONFIG_BMW */
179 * Thisk the stack pointer *somewhere* sensible. Doesnt
180 * matter much where as we'll move it when we relocate
182 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
183 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
185 li r0, 0 /* Make room for stack frame header and */
186 stwu r0, -4(r1) /* clear final stack frame so that */
187 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
189 /* let the C-code set up the rest */
191 /* Be careful to keep code relocatable ! */
192 /*----------------------------------------------------------------------*/
194 GET_GOT /* initialize GOT access */
197 bl cpu_init_f /* run low-level CPU init code (from Flash) */
201 bl board_init_f /* run 1st part of board init code (from Flash) */
205 .globl _start_of_vectors
209 STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)
211 /* Data Storage exception. "Never" generated on the 860. */
212 STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)
214 /* Instruction Storage exception. "Never" generated on the 860. */
215 STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)
217 /* External Interrupt exception. */
218 STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)
220 /* Alignment exception. */
228 addi r3,r1,STACK_FRAME_OVERHEAD
230 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
231 lwz r6,GOT(transfer_to_handler)
235 .long AlignmentException - _start + EXC_OFF_SYS_RESET
236 .long int_return - _start + EXC_OFF_SYS_RESET
238 /* Program check exception */
242 addi r3,r1,STACK_FRAME_OVERHEAD
244 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
245 lwz r6,GOT(transfer_to_handler)
249 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
250 .long int_return - _start + EXC_OFF_SYS_RESET
252 /* No FPU on MPC8xx. This exception is not supposed to happen.
254 STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)
256 /* I guess we could implement decrementer, and may have
257 * to someday for timekeeping.
259 STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
260 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
261 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
265 * r0 - SYSCALL number
269 addis r11,r0,0 /* get functions table addr */
270 ori r11,r11,0 /* Note: this code is patched in trap_init */
271 addis r12,r0,0 /* get number of functions */
277 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
281 li r12,0xd00-4*3 /* save LR & SRRx */
289 li r12,0xc00+_back-SystemCall
298 mfmsr r11 /* Disable interrupts */
302 SYNC /* Some chip revs need this... */
306 li r12,0xd00-4*3 /* restore regs */
317 STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
319 STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
320 STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)
322 STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
323 STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
324 STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
325 STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, UnknownException)
326 STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
327 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
328 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
329 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
330 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
331 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
332 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
333 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
334 STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
335 STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
336 STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
337 STD_EXCEPTION(0x1f00, ReservedF, UnknownException)
339 STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)
341 .globl _end_of_vectors
348 * This code finishes saving the registers to the exception frame
349 * and jumps to the appropriate handler for the exception.
350 * Register r21 is pointer into trap frame, r1 has new stack pointer.
352 .globl transfer_to_handler
364 mfspr r23,SPRG3 /* if from user, fix up tss.regs */
366 addi r24,r1,STACK_FRAME_OVERHEAD
368 2: addi r2,r23,-TSS /* set r2 to current */
372 andi. r24,r23,0x3f00 /* get vector offset */
376 mtspr SPRG2,r22 /* r1 is now kernel sp */
378 addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
382 bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
384 lwz r24,0(r23) /* virtual address of handler */
385 lwz r23,4(r23) /* where to go when done */
387 ori r20,r20,0x30 /* enable IR, DR */
391 rfi /* jump to handler, enable MMU */
394 mfmsr r28 /* Disable interrupts */
398 SYNC /* Some chip revs need this... */
413 lwz r2,_NIP(r1) /* Restore environment */
427 mfspr r5,HID0 /* turn on the I cache. */
428 ori r5,r5,0x8800 /* Instruction cache only! */
431 and r6,r5,r6 /* clear the invalidate bit */
439 .globl icache_disable
454 srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */
460 mfspr r5,HID0 /* turn on the D cache. */
461 ori r5,r5,0x4400 /* Data cache only! */
462 mfspr r4, PVR /* read PVR */
463 srawi r3, r4, 16 /* shift off the least 16 bits */
464 cmpi 0, 0, r3, 0xC /* Check for Max pvr */
466 ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */
470 and r6,r5,r6 /* clear the invalidate bit */
478 .globl dcache_disable
493 srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */
499 /*TODO : who uses this, what should it do?
510 /*------------------------------------------------------------------------------*/
513 * void relocate_code (addr_sp, gd, addr_moni)
515 * This "function" does not return, instead it continues in RAM
516 * after relocating the monitor code.
520 * r5 = length in bytes
526 mr r1, r3 /* Set new stack pointer */
527 mr r9, r4 /* Save copy of Global Data pointer */
528 mr r10, r5 /* Save copy of Destination Address */
530 mr r3, r5 /* Destination Address */
532 lis r4, CFG_SDRAM_BASE@h /* Source Address */
533 ori r4, r4, CFG_SDRAM_BASE@l
535 lis r4, CFG_MONITOR_BASE@h /* Source Address */
536 ori r4, r4, CFG_MONITOR_BASE@l
538 lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */
539 ori r5, r5, CFG_MONITOR_LEN@l
540 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
545 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
551 /* First our own GOT */
553 /* the the one used by the C code */
563 beq cr1,4f /* In place copy is not necessary */
564 beq 7f /* Protect against 0 count */
583 * Now flush the cache: note that we must start from a cache aligned
584 * address. Otherwise we might miss one cache line.
588 beq 7f /* Always flush prefetch queue in any case */
596 sync /* Wait for all dcbst to complete on bus */
602 7: sync /* Wait for all icbi to complete on bus */
606 * We are done. Do not return, instead branch to second part of board
607 * initialization, now running from RAM.
610 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
617 * Relocation Function, r14 point to got2+0x8000
619 * Adjust got2 pointers, no need to check for 0, this code
620 * already puts a few entries in the table.
622 li r0,__got2_entries@sectoff@l
623 la r3,GOT(_GOT2_TABLE_)
624 lwz r11,GOT(_GOT2_TABLE_)
634 * Now adjust the fixups and the pointers to the fixups
635 * in case we need to move ourselves again.
637 2: li r0,__fixup_entries@sectoff@l
638 lwz r3,GOT(_FIXUP_TABLE_)
652 * Now clear BSS segment
668 mr r3, r9 /* Global Data pointer */
669 mr r4, r10 /* Destination Address */
672 /* Problems accessing "end" in C, so do it here */
679 * Copy exception vector code to low memory
682 * r7: source address, r8: end address, r9: target address
687 lwz r8, GOT(_end_of_vectors)
689 rlwinm r9, r7, 0, 18, 31 /* _start & 0x3FFF */
692 bgelr /* return if r7>=r8 - just in case */
694 mflr r4 /* save link register */
704 * relocate `hdlr' and `int_return' entries
706 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
707 li r8, Alignment - _start + EXC_OFF_SYS_RESET
710 addi r7, r7, 0x100 /* next exception vector */
714 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
717 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
720 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
721 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
724 addi r7, r7, 0x100 /* next exception vector */
728 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
729 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
732 addi r7, r7, 0x100 /* next exception vector */
736 mtlr r4 /* restore link register */
740 * Function: relocate entries for one exception vector
743 lwz r0, 0(r7) /* hdlr ... */
744 add r0, r0, r3 /* ... += dest_addr */
747 lwz r0, 4(r7) /* int_return ... */
748 add r0, r0, r3 /* ... += dest_addr */
753 /* Setup the BAT registers.
757 ori r4, r4, CFG_IBAT0L@l
759 ori r3, r3, CFG_IBAT0U@l
765 ori r4, r4, CFG_DBAT0L@l
767 ori r3, r3, CFG_DBAT0U@l
773 ori r4, r4, CFG_IBAT1L@l
775 ori r3, r3, CFG_IBAT1U@l
781 ori r4, r4, CFG_DBAT1L@l
783 ori r3, r3, CFG_DBAT1U@l
789 ori r4, r4, CFG_IBAT2L@l
791 ori r3, r3, CFG_IBAT2U@l
797 ori r4, r4, CFG_DBAT2L@l
799 ori r3, r3, CFG_DBAT2U@l
805 ori r4, r4, CFG_IBAT3L@l
807 ori r3, r3, CFG_IBAT3U@l
813 ori r4, r4, CFG_DBAT3L@l
815 ori r3, r3, CFG_DBAT3U@l
821 * -> for (val = 0; val < 0x20000; val+=0x1000)