cpu/mpc83xx/cpu_init.c

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <mpc83xx.h>
  25 #include <ioports.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_QE
  30 extern qe_iop_conf_t qe_iop_conf_tab[];
  31 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  32                          int open_drain, int assign);
  33 extern void qe_init(uint qe_base);
  34 extern void qe_reset(void);
  35
  36 static void config_qe_ioports(void)
  37 {
  38         u8      port, pin;
  39         int     dir, open_drain, assign;
  40         int     i;
  41
  42         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  43                 port            = qe_iop_conf_tab[i].port;
  44                 pin             = qe_iop_conf_tab[i].pin;
  45                 dir             = qe_iop_conf_tab[i].dir;
  46                 open_drain      = qe_iop_conf_tab[i].open_drain;
  47                 assign          = qe_iop_conf_tab[i].assign;
  48                 qe_config_iopin(port, pin, dir, open_drain, assign);
  49         }
  50 }
  51 #endif
  52
  53 /*
  54  * Breathe some life into the CPU...
  55  *
  56  * Set up the memory map,
  57  * initialize a bunch of registers,
  58  * initialize the UPM's
  59  */
  60 void cpu_init_f (volatile immap_t * im)
  61 {
  62         /* Pointer is writable since we allocated a register for it */
  63         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  64
  65         /* Clear initial global data */
  66         memset ((void *) gd, 0, sizeof (gd_t));
  67
  68         /* system performance tweaking */
  69
  70 #ifdef CONFIG_SYS_ACR_PIPE_DEP
  71         /* Arbiter pipeline depth */
  72         im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
  73                           (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
  74 #endif
  75
  76 #ifdef CONFIG_SYS_ACR_RPTCNT
  77         /* Arbiter repeat count */
  78         im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
  79                           (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
  80 #endif
  81
  82 #ifdef CONFIG_SYS_SPCR_OPT
  83         /* Optimize transactions between CSB and other devices */
  84         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
  85                            (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
  86 #endif
  87
  88 #ifdef CONFIG_SYS_SPCR_TSECEP
  89         /* all eTSEC's Emergency priority */
  90         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
  91                            (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
  92 #endif
  93
  94 #ifdef CONFIG_SYS_SPCR_TSEC1EP
  95         /* TSEC1 Emergency priority */
  96         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
  97                            (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
  98 #endif
  99
 100 #ifdef CONFIG_SYS_SPCR_TSEC2EP
 101         /* TSEC2 Emergency priority */
 102         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
 103                            (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
 104 #endif
 105
 106 #ifdef CONFIG_SYS_SCCR_ENCCM
 107         /* Encryption clock mode */
 108         im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
 109                        (CONFIG_SYS_SCCR_ENCCM << SCCR_PCICM_SHIFT);
 110 #endif
 111
 112 #ifdef CONFIG_SYS_SCCR_PCICM
 113         /* PCI & DMA clock mode */
 114         im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
 115                        (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT);
 116 #endif
 117
 118 #ifdef CONFIG_SYS_SCCR_TSECCM
 119         /* all TSEC's clock mode */
 120         im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
 121                        (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
 122 #endif
 123
 124 #ifdef CONFIG_SYS_SCCR_TSEC1CM
 125         /* TSEC1 clock mode */
 126         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
 127                        (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
 128 #endif
 129
 130 #ifdef CONFIG_SYS_SCCR_TSEC2CM
 131         /* TSEC2 clock mode */
 132         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
 133                        (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
 134 #endif
 135
 136 #ifdef CONFIG_SYS_SCCR_TSEC1ON
 137         /* TSEC1 clock switch */
 138         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
 139                        (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
 140 #endif
 141
 142 #ifdef CONFIG_SYS_SCCR_TSEC2ON
 143         /* TSEC2 clock switch */
 144         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
 145                        (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
 146 #endif
 147
 148 #ifdef CONFIG_SYS_SCCR_USBMPHCM
 149         /* USB MPH clock mode */
 150         im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
 151                        (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
 152 #endif
 153
 154 #ifdef CONFIG_SYS_SCCR_USBDRCM
 155         /* USB DR clock mode */
 156         im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
 157                        (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
 158 #endif
 159
 160 #ifdef CONFIG_SYS_SCCR_SATACM
 161         /* SATA controller clock mode */
 162         im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
 163                        (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT);
 164 #endif
 165
 166         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 167         gd->reset_status = im->reset.rsr;
 168         im->reset.rsr = ~(RSR_RES);
 169
 170         /* AER - Arbiter Event Register - store status */
 171         gd->arbiter_event_attributes = im->arbiter.aeatr;
 172         gd->arbiter_event_address = im->arbiter.aeadr;
 173
 174         /*
 175          * RMR - Reset Mode Register
 176          * contains checkstop reset enable (4.6.1.4)
 177          */
 178         im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
 179
 180         /* LCRR - Clock Ratio Register (10.3.1.16) */
 181         im->lbus.lcrr = CONFIG_SYS_LCRR;
 182
 183         /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
 184         im->sysconf.spcr |= SPCR_TBEN;
 185
 186         /* System General Purpose Register */
 187 #ifdef CONFIG_SYS_SICRH
 188 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
 189         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 190         im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
 191 #else
 192         im->sysconf.sicrh = CONFIG_SYS_SICRH;
 193 #endif
 194 #endif
 195 #ifdef CONFIG_SYS_SICRL
 196         im->sysconf.sicrl = CONFIG_SYS_SICRL;
 197 #endif
 198         /* DDR control driver register */
 199 #ifdef CONFIG_SYS_DDRCDR
 200         im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
 201 #endif
 202         /* Output buffer impedance register */
 203 #ifdef CONFIG_SYS_OBIR
 204         im->sysconf.obir = CONFIG_SYS_OBIR;
 205 #endif
 206
 207 #ifdef CONFIG_QE
 208         /* Config QE ioports */
 209         config_qe_ioports();
 210 #endif
 211
 212         /*
 213          * Memory Controller:
 214          */
 215
 216         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 217          * addresses - these have to be modified later when FLASH size
 218          * has been determined
 219          */
 220
 221 #if defined(CONFIG_SYS_BR0_PRELIM)  \
 222         && defined(CONFIG_SYS_OR0_PRELIM) \
 223         && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
 224         && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 225         im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
 226         im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
 227         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 228         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 229 #else
 230 #error  CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 231 #endif
 232
 233 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 234         im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
 235         im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
 236 #endif
 237 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 238         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 239         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 240 #endif
 241 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 242         im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
 243         im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
 244 #endif
 245 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 246         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 247         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 248 #endif
 249 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 250         im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
 251         im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
 252 #endif
 253 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 254         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 255         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 256 #endif
 257 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 258         im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
 259         im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
 260 #endif
 261 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 262         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 263         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 264 #endif
 265 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 266         im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
 267         im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
 268 #endif
 269 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 270         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 271         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 272 #endif
 273 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 274         im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
 275         im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
 276 #endif
 277 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 278         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 279         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 280 #endif
 281 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 282         im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
 283         im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
 284 #endif
 285 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 286         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 287         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 288 #endif
 289 #ifdef CONFIG_SYS_GPIO1_PRELIM
 290         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 291         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 292 #endif
 293 #ifdef CONFIG_SYS_GPIO2_PRELIM
 294         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 295         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 296 #endif
 297 }
 298
 299 int cpu_init_r (void)
 300 {
 301 #ifdef CONFIG_QE
 302         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 303         qe_init(qe_base);
 304         qe_reset();
 305 #endif
 306         return 0;
 307 }
 308
 309 /*
 310  * Print out the bus arbiter event
 311  */
 312 #if defined(CONFIG_DISPLAY_AER_FULL)
 313 static int print_83xx_arb_event(int force)
 314 {
 315         static char* event[] = {
 316                 "Address Time Out",
 317                 "Data Time Out",
 318                 "Address Only Transfer Type",
 319                 "External Control Word Transfer Type",
 320                 "Reserved Transfer Type",
 321                 "Transfer Error",
 322                 "reserved",
 323                 "reserved"
 324         };
 325         static char* master[] = {
 326                 "e300 Core Data Transaction",
 327                 "reserved",
 328                 "e300 Core Instruction Fetch",
 329                 "reserved",
 330                 "TSEC1",
 331                 "TSEC2",
 332                 "USB MPH",
 333                 "USB DR",
 334                 "Encryption Core",
 335                 "I2C Boot Sequencer",
 336                 "JTAG",
 337                 "reserved",
 338                 "eSDHC",
 339                 "PCI1",
 340                 "PCI2",
 341                 "DMA",
 342                 "QUICC Engine 00",
 343                 "QUICC Engine 01",
 344                 "QUICC Engine 10",
 345                 "QUICC Engine 11",
 346                 "reserved",
 347                 "reserved",
 348                 "reserved",
 349                 "reserved",
 350                 "SATA1",
 351                 "SATA2",
 352                 "SATA3",
 353                 "SATA4",
 354                 "reserved",
 355                 "PCI Express 1",
 356                 "PCI Express 2",
 357                 "TDM-DMAC"
 358         };
 359         static char *transfer[] = {
 360                 "Address-only, Clean Block",
 361                 "Address-only, lwarx reservation set",
 362                 "Single-beat or Burst write",
 363                 "reserved",
 364                 "Address-only, Flush Block",
 365                 "reserved",
 366                 "Burst write",
 367                 "reserved",
 368                 "Address-only, sync",
 369                 "Address-only, tlbsync",
 370                 "Single-beat or Burst read",
 371                 "Single-beat or Burst read",
 372                 "Address-only, Kill Block",
 373                 "Address-only, icbi",
 374                 "Burst read",
 375                 "reserved",
 376                 "Address-only, eieio",
 377                 "reserved",
 378                 "Single-beat write",
 379                 "reserved",
 380                 "ecowx - Illegal single-beat write",
 381                 "reserved",
 382                 "reserved",
 383                 "reserved",
 384                 "Address-only, TLB Invalidate",
 385                 "reserved",
 386                 "Single-beat or Burst read",
 387                 "reserved",
 388                 "eciwx - Illegal single-beat read",
 389                 "reserved",
 390                 "Burst read",
 391                 "reserved"
 392         };
 393
 394         int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
 395                     >> AEATR_EVENT_SHIFT;
 396         int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
 397                       >> AEATR_MSTR_ID_SHIFT;
 398         int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
 399                    >> AEATR_TBST_SHIFT;
 400         int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
 401                     >> AEATR_TSIZE_SHIFT;
 402         int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
 403                     >> AEATR_TTYPE_SHIFT;
 404
 405         if (!force && !gd->arbiter_event_address)
 406                 return 0;
 407
 408         puts("Arbiter Event Status:\n");
 409         printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
 410         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 411         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 412         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 413                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 414         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 415
 416         return gd->arbiter_event_address;
 417 }
 418
 419 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 420
 421 static int print_83xx_arb_event(int force)
 422 {
 423         if (!force && !gd->arbiter_event_address)
 424                 return 0;
 425
 426         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 427                 gd->arbiter_event_attributes, gd->arbiter_event_address);
 428
 429         return gd->arbiter_event_address;
 430 }
 431 #endif /* CONFIG_DISPLAY_AER_xxxx */
 432
 433 /*
 434  * Figure out the cause of the reset
 435  */
 436 int prt_83xx_rsr(void)
 437 {
 438         static struct {
 439                 ulong mask;
 440                 char *desc;
 441         } bits[] = {
 442                 {
 443                 RSR_SWSR, "Software Soft"}, {
 444                 RSR_SWHR, "Software Hard"}, {
 445                 RSR_JSRS, "JTAG Soft"}, {
 446                 RSR_CSHR, "Check Stop"}, {
 447                 RSR_SWRS, "Software Watchdog"}, {
 448                 RSR_BMRS, "Bus Monitor"}, {
 449                 RSR_SRS,  "External/Internal Soft"}, {
 450                 RSR_HRS,  "External/Internal Hard"}
 451         };
 452         static int n = sizeof bits / sizeof bits[0];
 453         ulong rsr = gd->reset_status;
 454         int i;
 455         char *sep;
 456
 457         puts("Reset Status:");
 458
 459         sep = " ";
 460         for (i = 0; i < n; i++)
 461                 if (rsr & bits[i].mask) {
 462                         printf("%s%s", sep, bits[i].desc);
 463                         sep = ", ";
 464                 }
 465         puts("\n");
 466
 467 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 468         print_83xx_arb_event(rsr & RSR_BMRS);
 469 #endif
 470         puts("\n");
 471
 472         return 0;
 473 }