cpu/mpc85xx/pci.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Copyright (C) 2003 Motorola Inc.
   4  * Xianghua Xiao (x.xiao@motorola.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * PCI Configuration space access support for MPC85xx PCI Bridge
  27  */
  28 #include <common.h>
  29 #include <asm/cpm_85xx.h>
  30 #include <pci.h>
  31
  32
  33 #if defined(CONFIG_PCI)
  34
  35 void
  36 pci_mpc85xx_init(struct pci_controller *hose)
  37 {
  38         volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
  39         volatile ccsr_pcix_t *pcix = &immap->im_pcix;
  40
  41         u16 reg16;
  42
  43         hose->first_busno = 0;
  44         hose->last_busno = 0xff;
  45
  46         pci_set_region(hose->regions + 0,
  47                        CFG_PCI1_MEM_BASE,
  48                        CFG_PCI1_MEM_PHYS,
  49                        CFG_PCI1_MEM_SIZE,
  50                        PCI_REGION_MEM);
  51
  52         pci_set_region(hose->regions + 1,
  53                        CFG_PCI1_IO_BASE,
  54                        CFG_PCI1_IO_PHYS,
  55                        CFG_PCI1_IO_SIZE,
  56                        PCI_REGION_IO);
  57
  58         hose->region_count = 2;
  59
  60         pci_setup_indirect(hose,
  61                            (CFG_IMMR+0x8000),
  62                            (CFG_IMMR+0x8004));
  63
  64         pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
  65         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  66         pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
  67
  68         /*
  69          * Clear non-reserved bits in status register.
  70          */
  71         pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
  72         pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
  73
  74         pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  75         pcix->potear1  = 0x00000000;
  76         pcix->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  77         pcix->powbear1 = 0x00000000;
  78         pcix->powar1   = 0x8004401c;    /* 512M MEM space */
  79
  80         pcix->potar2   = 0x00000000;
  81         pcix->potear2  = 0x00000000;
  82         pcix->powbar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
  83         pcix->powbear2 = 0x00000000;
  84         pcix->powar2   = 0x80088017;    /* 16M IO space */
  85
  86         pcix->pitar1 = 0x00000000;
  87         pcix->piwbar1 = 0x00000000;
  88         pcix->piwar1 = 0xa0f5501e;      /* Enable, Prefetch, Local Mem,
  89                                          * Snoop R/W, 2G */
  90
  91         /*
  92          * Hose scan.
  93          */
  94         pci_register_hose(hose);
  95
  96 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
  97         /*
  98          * This is a SW workaround for an apparent HW problem
  99          * in the PCI controller on the MPC85555/41 CDS boards.
 100          * The first config cycle must be to a valid, known
 101          * device on the PCI bus in order to trick the PCI
 102          * controller state machine into a known valid state.
 103          * Without this, the first config cycle has the chance
 104          * of hanging the controller permanently, just leaving
 105          * it in a semi-working state, or leaving it working.
 106          *
 107          * Pick on the Tundra, Device 17, to get it right.
 108          */
 109         {
 110                 u8 header_type;
 111
 112                 pci_hose_read_config_byte(hose,
 113                                           PCI_BDF(0,17,0),
 114                                           PCI_HEADER_TYPE,
 115                                           &header_type);
 116         }
 117
 118 #endif
 119
 120         hose->last_busno = pci_hose_scan(hose);
 121 }
 122
 123 #endif /* CONFIG_PCI */