cpu/ppc4xx/spd_sdram.c

   1 /*
   2  * (C) Copyright 2001
   3  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   4  *
   5  * Based on code by:
   6  *
   7  * Kenneth Johansson ,Ericsson Business Innovation.
   8  * kenneth.johansson@inn.ericsson.se
   9  *
  10  * hacked up by bill hunter. fixed so we could run before
  11  * serial_init and console_init. previous version avoided this by
  12  * running out of cache memory during serial/console init, then running
  13  * this code later.
  14  *
  15  * (C) Copyright 2002
  16  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  17  * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
  18  *
  19  * See file CREDITS for list of people who contributed to this
  20  * project.
  21  *
  22  * This program is free software; you can redistribute it and/or
  23  * modify it under the terms of the GNU General Public License as
  24  * published by the Free Software Foundation; either version 2 of
  25  * the License, or (at your option) any later version.
  26  *
  27  * This program is distributed in the hope that it will be useful,
  28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30  * GNU General Public License for more details.
  31  *
  32  * You should have received a copy of the GNU General Public License
  33  * along with this program; if not, write to the Free Software
  34  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  35  * MA 02111-1307 USA
  36  */
  37
  38 #include <common.h>
  39 #include <asm/processor.h>
  40 #include <i2c.h>
  41 #include <ppc4xx.h>
  42
  43 #ifdef CONFIG_SPD_EEPROM
  44
  45 /*
  46  * Set default values
  47  */
  48 #ifndef CFG_I2C_SPEED
  49 #define CFG_I2C_SPEED   50000
  50 #endif
  51
  52 #ifndef CFG_I2C_SLAVE
  53 #define CFG_I2C_SLAVE   0xFE
  54 #endif
  55
  56 #ifndef  CONFIG_440              /* for 405 WALNUT board */
  57
  58 #define  SDRAM0_CFG_DCE          0x80000000
  59 #define  SDRAM0_CFG_SRE          0x40000000
  60 #define  SDRAM0_CFG_PME          0x20000000
  61 #define  SDRAM0_CFG_MEMCHK       0x10000000
  62 #define  SDRAM0_CFG_REGEN        0x08000000
  63 #define  SDRAM0_CFG_ECCDD        0x00400000
  64 #define  SDRAM0_CFG_EMDULR       0x00200000
  65 #define  SDRAM0_CFG_DRW_SHIFT    (31-6)
  66 #define  SDRAM0_CFG_BRPF_SHIFT   (31-8)
  67
  68 #define  SDRAM0_TR_CASL_SHIFT    (31-8)
  69 #define  SDRAM0_TR_PTA_SHIFT     (31-13)
  70 #define  SDRAM0_TR_CTP_SHIFT     (31-15)
  71 #define  SDRAM0_TR_LDF_SHIFT     (31-17)
  72 #define  SDRAM0_TR_RFTA_SHIFT    (31-29)
  73 #define  SDRAM0_TR_RCD_SHIFT     (31-31)
  74
  75 #define  SDRAM0_RTR_SHIFT        (31-15)
  76 #define  SDRAM0_ECCCFG_SHIFT     (31-11)
  77
  78 /* SDRAM0_CFG enable macro  */
  79 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
  80
  81 #define SDRAM0_BXCR_SZ_MASK  0x000e0000
  82 #define SDRAM0_BXCR_AM_MASK  0x0000e000
  83
  84 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
  85 #define SDRAM0_BXCR_AM_SHIFT (31-18)
  86
  87 #define SDRAM0_BXCR_SZ(x)  ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
  88 #define SDRAM0_BXCR_AM(x)  ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
  89
  90 #ifdef CONFIG_W7O
  91 # define SPD_ERR(x) do { return 0; } while (0)
  92 #else
  93 # define SPD_ERR(x) do { printf(x); hang(); } while (0)
  94 #endif
  95
  96 /*
  97  * what we really want is
  98  * (1/hertz) but we don't want to use floats so multiply with 10E9
  99  *
 100  * The error needs to be on the safe side so we want the floor function.
 101  * This means we get an exact value or we calculate that our bus frequency is
 102  * a bit faster than it really is and thus we don't progam the sdram controller
 103  * to run to fast
 104  */
 105 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
 106
 107 /* function prototypes */
 108 int spd_read(uint addr);                        /* prototype */
 109
 110
 111 /*
 112  * This function is reading data from the DIMM module EEPROM over the SPD bus
 113  * and uses that to program the sdram controller.
 114  *
 115  * This works on boards that has the same schematics that the IBM walnut has.
 116  *
 117  * BUG: Don't handle ECC memory
 118  * BUG: A few values in the TR register is currently hardcoded
 119  */
 120
 121 long int spd_sdram(void)
 122 {
 123         int bus_period,tmp,row,col;
 124         int total_size,bank_size,bank_code;
 125         int ecc_on;
 126         int mode = 4;
 127         int bank_cnt = 1;
 128
 129         int sdram0_pmit=0x07c00000;
 130         int sdram0_besr0=-1;
 131         int sdram0_besr1=-1;
 132         int sdram0_eccesr=-1;
 133         int sdram0_ecccfg;
 134
 135         int sdram0_rtr=0;
 136         int sdram0_tr=0;
 137
 138         int sdram0_b0cr;
 139         int sdram0_b1cr;
 140         int sdram0_b2cr;
 141         int sdram0_b3cr;
 142
 143         int sdram0_cfg=0;
 144
 145         int t_rp;
 146         int t_rcd;
 147         int t_rc = 70; /* This value not available in SPD_EEPROM */
 148         int min_cas = 2;
 149
 150         /*
 151          * Make sure I2C controller is initialized
 152          * before continuing.
 153          */
 154         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 155
 156         /*
 157          * Calculate the bus period, we do it this
 158          * way to minimize stack utilization.
 159          */
 160         tmp = (mfdcr(pllmd) >> (31-6)) & 0xf;   /* get FBDV bits */
 161         tmp = CONFIG_SYS_CLK_FREQ * tmp;        /* get plb freq */
 162         bus_period = sdram_HZ_to_ns(tmp);       /* get sdram speed */
 163
 164         /* Make shure we are using SDRAM */
 165         if (spd_read(2) != 0x04){
 166           SPD_ERR("SDRAM - non SDRAM memory module found\n");
 167           }
 168
 169 /*------------------------------------------------------------------
 170   configure memory timing register
 171
 172   data from DIMM:
 173   27    IN Row Precharge Time ( t RP)
 174   29    MIN RAS to CAS Delay ( t RCD)
 175   127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
 176   -------------------------------------------------------------------*/
 177
 178      /*
 179       * first figure out which cas latency mode to use
 180       * use the min supported mode
 181       */
 182
 183         tmp = spd_read(127) & 0x6;
 184      if(tmp == 0x02){              /* only cas = 2 supported */
 185           min_cas = 2;
 186 /*        t_ck = spd_read(9); */
 187 /*        t_ac = spd_read(10); */
 188           }
 189      else if (tmp == 0x04){         /* only cas = 3 supported */
 190           min_cas = 3;
 191 /*        t_ck = spd_read(9); */
 192 /*        t_ac = spd_read(10); */
 193           }
 194      else if (tmp == 0x06){         /* 2,3 supported, so use 2 */
 195           min_cas = 2;
 196 /*        t_ck = spd_read(23); */
 197 /*        t_ac = spd_read(24); */
 198           }
 199      else {
 200              SPD_ERR("SDRAM - unsupported CAS latency \n");
 201         }
 202
 203      /* get some timing values, t_rp,t_rcd
 204      */
 205      t_rp = spd_read(27);
 206      t_rcd = spd_read(29);
 207
 208
 209      /* The following timing calcs subtract 1 before deviding.
 210       * this has effect of using ceiling intead of floor rounding,
 211       * and also subtracting 1 to convert number to reg value
 212       */
 213      /* set up CASL */
 214      sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
 215      /* set up PTA */
 216      sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
 217      /* set up CTP */
 218      tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
 219      if(tmp<1) SPD_ERR("SDRAM - unsupported prech to act time (Trp)\n");
 220      sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
 221      /* set LDF = 2 cycles, reg value = 1 */
 222      sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
 223      /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
 224         tmp = ((t_rc - 1) / bus_period)-4;
 225         if(tmp<0)tmp=0;
 226         if(tmp>6)tmp=6;
 227         sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
 228      /* set RCD = t_rcd/bus_period*/
 229      sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;
 230
 231
 232 /*------------------------------------------------------------------
 233   configure RTR register
 234   -------------------------------------------------------------------*/
 235      row = spd_read(3);
 236      col = spd_read(4);
 237      tmp = spd_read(12) & 0x7f ; /* refresh type less self refresh bit */
 238      switch(tmp){
 239         case 0x00:
 240           tmp=15625;
 241           break;
 242         case 0x01:
 243           tmp=15625/4;
 244           break;
 245         case 0x02:
 246           tmp=15625/2;
 247           break;
 248         case 0x03:
 249           tmp=15625*2;
 250           break;
 251         case 0x04:
 252           tmp=15625*4;
 253           break;
 254         case 0x05:
 255           tmp=15625*8;
 256           break;
 257         default:
 258           SPD_ERR("SDRAM - Bad refresh period \n");
 259         }
 260         /* convert from nsec to bus cycles */
 261         tmp = tmp/bus_period;
 262         sdram0_rtr = (tmp & 0x3ff8)<<  SDRAM0_RTR_SHIFT;
 263
 264 /*------------------------------------------------------------------
 265   determine the number of banks used
 266   -------------------------------------------------------------------*/
 267         /* byte 7:6 is module data width */
 268         if(spd_read(7) != 0)
 269             SPD_ERR("SDRAM - unsupported module width\n");
 270         tmp = spd_read(6);
 271         if (tmp < 32)
 272             SPD_ERR("SDRAM - unsupported module width\n");
 273         else if (tmp < 64)
 274             bank_cnt=1;         /* one bank per sdram side */
 275         else if (tmp < 73)
 276             bank_cnt=2; /* need two banks per side */
 277         else if (tmp < 161)
 278             bank_cnt=4; /* need four banks per side */
 279         else
 280             SPD_ERR("SDRAM - unsupported module width\n");
 281
 282         /* byte 5 is the module row count (refered to as dimm "sides") */
 283         tmp = spd_read(5);
 284         if(tmp==1);
 285         else if(tmp==2) bank_cnt *=2;
 286         else if(tmp==4) bank_cnt *=4;
 287         else bank_cnt = 8;              /* 8 is an error code */
 288
 289         if(bank_cnt > 4)        /* we only have 4 banks to work with */
 290             SPD_ERR("SDRAM - unsupported module rows for this width\n");
 291
 292         /* now check for ECC ability of module. We only support ECC
 293          *   on 32 bit wide devices with 8 bit ECC.
 294          */
 295         if ( (spd_read(11)==2) && ((spd_read(6)==40) || (spd_read(14)==8)) ){
 296            sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
 297            ecc_on = 1;
 298         }
 299         else{
 300            sdram0_ecccfg=0;
 301            ecc_on = 0;
 302         }
 303
 304 /*------------------------------------------------------------------
 305         calculate total size
 306   -------------------------------------------------------------------*/
 307         /* calculate total size and do sanity check */
 308         tmp = spd_read(31);
 309         total_size=1<<22;       /* total_size = 4MB */
 310         /* now multiply 4M by the smallest device roe density */
 311         /* note that we don't support asymetric rows */
 312         while (((tmp & 0x0001) == 0) && (tmp != 0)){
 313             total_size= total_size<<1;
 314             tmp = tmp>>1;
 315             }
 316         total_size *= spd_read(5);      /* mult by module rows (dimm sides) */
 317
 318 /*------------------------------------------------------------------
 319         map  rows * cols * banks to a mode
 320  -------------------------------------------------------------------*/
 321
 322         switch( row )
 323         {
 324         case 11:
 325                 switch ( col )
 326                 {
 327                 case 8:
 328                         mode=4; /* mode 5 */
 329                         break;
 330                 case 9:
 331                 case 10:
 332                         mode=0; /* mode 1 */
 333                         break;
 334                 default:
 335                 SPD_ERR("SDRAM - unsupported mode\n");
 336                 }
 337                 break;
 338         case 12:
 339                 switch ( col )
 340                 {
 341                 case 8:
 342                         mode=3; /* mode 4 */
 343                         break;
 344                 case 9:
 345                 case 10:
 346                         mode=1; /* mode 2 */
 347                         break;
 348                 default:
 349                 SPD_ERR("SDRAM - unsupported mode\n");
 350                 }
 351                 break;
 352         case 13:
 353                 switch ( col )
 354                 {
 355                 case 8:
 356                         mode=5; /* mode 6 */
 357                         break;
 358                 case 9:
 359                 case 10:
 360                         if (spd_read(17) ==2 )
 361                                 mode=6; /* mode 7 */
 362                         else
 363                                 mode=2; /* mode 3 */
 364                         break;
 365                 case 11:
 366                         mode=2; /* mode 3 */
 367                         break;
 368                 default:
 369                 SPD_ERR("SDRAM - unsupported mode\n");
 370                 }
 371                 break;
 372         default:
 373              SPD_ERR("SDRAM - unsupported mode\n");
 374         }
 375
 376 /*------------------------------------------------------------------
 377         using the calculated values, compute the bank
 378         config register values.
 379  -------------------------------------------------------------------*/
 380         sdram0_b1cr = 0;
 381         sdram0_b2cr = 0;
 382         sdram0_b3cr = 0;
 383
 384         /* compute the size of each bank */
 385         bank_size = total_size / bank_cnt;
 386         /* convert bank size to bank size code for ppc4xx
 387                 by takeing log2(bank_size) - 22 */
 388         tmp=bank_size;          /* start with tmp = bank_size */
 389         bank_code=0;                    /* and bank_code = 0 */
 390         while (tmp>1){          /* this takes log2 of tmp */
 391                 bank_code++;            /* and stores result in bank_code */
 392                 tmp=tmp>>1;
 393                 }                               /* bank_code is now log2(bank_size) */
 394         bank_code-=22;                          /* subtract 22 to get the code */
 395
 396         tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
 397         sdram0_b0cr = (bank_size) * 0 | tmp;
 398         if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
 399         if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
 400         if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
 401
 402
 403         /*
 404          *   enable sdram controller DCE=1
 405          *  enable burst read prefetch to 32 bytes BRPF=2
 406          *  leave other functions off
 407          */
 408
 409 /*------------------------------------------------------------------
 410         now that we've done our calculations, we are ready to
 411         program all the registers.
 412  -------------------------------------------------------------------*/
 413
 414
 415 #define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
 416         /* disable memcontroller so updates work */
 417         sdram0_cfg = 0;
 418         mtsdram0( mem_mcopt1, sdram0_cfg );
 419
 420         mtsdram0( mem_besra , sdram0_besr0 );
 421         mtsdram0( mem_besrb , sdram0_besr1 );
 422         mtsdram0( mem_rtr   , sdram0_rtr );
 423         mtsdram0( mem_pmit  , sdram0_pmit );
 424         mtsdram0( mem_mb0cf , sdram0_b0cr );
 425         mtsdram0( mem_mb1cf , sdram0_b1cr );
 426         mtsdram0( mem_mb2cf , sdram0_b2cr );
 427         mtsdram0( mem_mb3cf , sdram0_b3cr );
 428         mtsdram0( mem_sdtr1 , sdram0_tr );
 429         mtsdram0( mem_ecccf , sdram0_ecccfg );
 430         mtsdram0( mem_eccerr, sdram0_eccesr );
 431
 432         /* SDRAM have a power on delay,  500 micro should do */
 433         udelay(500);
 434         sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 435         if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
 436         mtsdram0( mem_mcopt1, sdram0_cfg );
 437
 438
 439         /* kernel 2.4.2 from mvista has a bug with memory over 128MB */
 440 #ifdef MVISTA_MEM_BUG
 441         if (total_size > 128*1024*1024 )
 442                 total_size=128*1024*1024;
 443 #endif
 444         return (total_size);
 445 }
 446
 447 int spd_read(uint addr)
 448 {
 449         char data[2];
 450
 451         if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 452                 return (int)data[0];
 453         else
 454                 return 0;
 455 }
 456
 457 #else                             /* CONFIG_440 */
 458
 459 /*-----------------------------------------------------------------------------
 460 |  Memory Controller Options 0
 461 +-----------------------------------------------------------------------------*/
 462 #define SDRAM_CFG0_DCEN           0x80000000  /* SDRAM Controller Enable      */
 463 #define SDRAM_CFG0_MCHK_MASK      0x30000000  /* Memory data errchecking mask */
 464 #define SDRAM_CFG0_MCHK_NON       0x00000000  /* No ECC generation            */
 465 #define SDRAM_CFG0_MCHK_GEN       0x20000000  /* ECC generation               */
 466 #define SDRAM_CFG0_MCHK_CHK       0x30000000  /* ECC generation and checking  */
 467 #define SDRAM_CFG0_RDEN           0x08000000  /* Registered DIMM enable       */
 468 #define SDRAM_CFG0_PMUD           0x04000000  /* Page management unit         */
 469 #define SDRAM_CFG0_DMWD_MASK      0x02000000  /* DRAM width mask              */
 470 #define SDRAM_CFG0_DMWD_32        0x00000000  /* 32 bits                      */
 471 #define SDRAM_CFG0_DMWD_64        0x02000000  /* 64 bits                      */
 472 #define SDRAM_CFG0_UIOS_MASK      0x00C00000  /* Unused IO State              */
 473 #define SDRAM_CFG0_PDP            0x00200000  /* Page deallocation policy     */
 474
 475 /*-----------------------------------------------------------------------------
 476 |  Memory Controller Options 1
 477 +-----------------------------------------------------------------------------*/
 478 #define SDRAM_CFG1_SRE            0x80000000  /* Self-Refresh Entry           */
 479 #define SDRAM_CFG1_PMEN           0x40000000  /* Power Management Enable      */
 480
 481 /*-----------------------------------------------------------------------------+
 482 |  SDRAM DEVPOT Options
 483 +-----------------------------------------------------------------------------*/
 484 #define SDRAM_DEVOPT_DLL          0x80000000
 485 #define SDRAM_DEVOPT_DS           0x40000000
 486
 487 /*-----------------------------------------------------------------------------+
 488 |  SDRAM MCSTS Options
 489 +-----------------------------------------------------------------------------*/
 490 #define SDRAM_MCSTS_MRSC          0x80000000
 491 #define SDRAM_MCSTS_SRMS          0x40000000
 492 #define SDRAM_MCSTS_CIS           0x20000000
 493
 494 /*-----------------------------------------------------------------------------
 495 |  SDRAM Refresh Timer Register
 496 +-----------------------------------------------------------------------------*/
 497 #define SDRAM_RTR_RINT_MASK       0xFFFF0000
 498 #define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
 499 #define sdram_HZ_to_ns(hertz)     (1000000000/(hertz))
 500
 501 /*-----------------------------------------------------------------------------+
 502 |  SDRAM UABus Base Address Reg
 503 +-----------------------------------------------------------------------------*/
 504 #define SDRAM_UABBA_UBBA_MASK     0x0000000F
 505
 506 /*-----------------------------------------------------------------------------+
 507 |  Memory Bank 0-7 configuration
 508 +-----------------------------------------------------------------------------*/
 509 #define SDRAM_BXCR_SDBA_MASK      0xff800000      /* Base address             */
 510 #define SDRAM_BXCR_SDSZ_MASK      0x000e0000      /* Size                     */
 511 #define SDRAM_BXCR_SDSZ_8         0x00020000      /*   8M                     */
 512 #define SDRAM_BXCR_SDSZ_16        0x00040000      /*  16M                     */
 513 #define SDRAM_BXCR_SDSZ_32        0x00060000      /*  32M                     */
 514 #define SDRAM_BXCR_SDSZ_64        0x00080000      /*  64M                     */
 515 #define SDRAM_BXCR_SDSZ_128       0x000a0000      /* 128M                     */
 516 #define SDRAM_BXCR_SDSZ_256       0x000c0000      /* 256M                     */
 517 #define SDRAM_BXCR_SDSZ_512       0x000e0000      /* 512M                     */
 518 #define SDRAM_BXCR_SDAM_MASK      0x0000e000      /* Addressing mode          */
 519 #define SDRAM_BXCR_SDAM_1         0x00000000      /*   Mode 1                 */
 520 #define SDRAM_BXCR_SDAM_2         0x00002000      /*   Mode 2                 */
 521 #define SDRAM_BXCR_SDAM_3         0x00004000      /*   Mode 3                 */
 522 #define SDRAM_BXCR_SDAM_4         0x00006000      /*   Mode 4                 */
 523 #define SDRAM_BXCR_SDBE           0x00000001      /* Memory Bank Enable       */
 524
 525 /*-----------------------------------------------------------------------------+
 526 |  SDRAM TR0 Options
 527 +-----------------------------------------------------------------------------*/
 528 #define SDRAM_TR0_SDWR_MASK       0x80000000
 529 #define   SDRAM_TR0_SDWR_2_CLK    0x00000000
 530 #define   SDRAM_TR0_SDWR_3_CLK    0x80000000
 531 #define SDRAM_TR0_SDWD_MASK       0x40000000
 532 #define   SDRAM_TR0_SDWD_0_CLK    0x00000000
 533 #define   SDRAM_TR0_SDWD_1_CLK    0x40000000
 534 #define SDRAM_TR0_SDCL_MASK       0x01800000
 535 #define   SDRAM_TR0_SDCL_2_0_CLK  0x00800000
 536 #define   SDRAM_TR0_SDCL_2_5_CLK  0x01000000
 537 #define   SDRAM_TR0_SDCL_3_0_CLK  0x01800000
 538 #define SDRAM_TR0_SDPA_MASK       0x000C0000
 539 #define   SDRAM_TR0_SDPA_2_CLK    0x00040000
 540 #define   SDRAM_TR0_SDPA_3_CLK    0x00080000
 541 #define   SDRAM_TR0_SDPA_4_CLK    0x000C0000
 542 #define SDRAM_TR0_SDCP_MASK       0x00030000
 543 #define   SDRAM_TR0_SDCP_2_CLK    0x00000000
 544 #define   SDRAM_TR0_SDCP_3_CLK    0x00010000
 545 #define   SDRAM_TR0_SDCP_4_CLK    0x00020000
 546 #define   SDRAM_TR0_SDCP_5_CLK    0x00030000
 547 #define SDRAM_TR0_SDLD_MASK       0x0000C000
 548 #define   SDRAM_TR0_SDLD_1_CLK    0x00000000
 549 #define   SDRAM_TR0_SDLD_2_CLK    0x00004000
 550 #define SDRAM_TR0_SDRA_MASK       0x0000001C
 551 #define   SDRAM_TR0_SDRA_6_CLK    0x00000000
 552 #define   SDRAM_TR0_SDRA_7_CLK    0x00000004
 553 #define   SDRAM_TR0_SDRA_8_CLK    0x00000008
 554 #define   SDRAM_TR0_SDRA_9_CLK    0x0000000C
 555 #define   SDRAM_TR0_SDRA_10_CLK   0x00000010
 556 #define   SDRAM_TR0_SDRA_11_CLK   0x00000014
 557 #define   SDRAM_TR0_SDRA_12_CLK   0x00000018
 558 #define   SDRAM_TR0_SDRA_13_CLK   0x0000001C
 559 #define SDRAM_TR0_SDRD_MASK       0x00000003
 560 #define   SDRAM_TR0_SDRD_2_CLK    0x00000001
 561 #define   SDRAM_TR0_SDRD_3_CLK    0x00000002
 562 #define   SDRAM_TR0_SDRD_4_CLK    0x00000003
 563
 564 /*-----------------------------------------------------------------------------+
 565 |  SDRAM TR1 Options
 566 +-----------------------------------------------------------------------------*/
 567 #define SDRAM_TR1_RDSS_MASK         0xC0000000
 568 #define   SDRAM_TR1_RDSS_TR0        0x00000000
 569 #define   SDRAM_TR1_RDSS_TR1        0x40000000
 570 #define   SDRAM_TR1_RDSS_TR2        0x80000000
 571 #define   SDRAM_TR1_RDSS_TR3        0xC0000000
 572 #define SDRAM_TR1_RDSL_MASK         0x00C00000
 573 #define   SDRAM_TR1_RDSL_STAGE1     0x00000000
 574 #define   SDRAM_TR1_RDSL_STAGE2     0x00400000
 575 #define   SDRAM_TR1_RDSL_STAGE3     0x00800000
 576 #define SDRAM_TR1_RDCD_MASK         0x00000800
 577 #define   SDRAM_TR1_RDCD_RCD_0_0    0x00000000
 578 #define   SDRAM_TR1_RDCD_RCD_1_2    0x00000800
 579 #define SDRAM_TR1_RDCT_MASK         0x000001FF
 580 #define   SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
 581 #define   SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
 582 #define   SDRAM_TR1_RDCT_MIN        0x00000000
 583 #define   SDRAM_TR1_RDCT_MAX        0x000001FF
 584
 585 /*-----------------------------------------------------------------------------+
 586 |  SDRAM WDDCTR Options
 587 +-----------------------------------------------------------------------------*/
 588 #define SDRAM_WDDCTR_WRCP_MASK       0xC0000000
 589 #define   SDRAM_WDDCTR_WRCP_0DEG     0x00000000
 590 #define   SDRAM_WDDCTR_WRCP_90DEG    0x40000000
 591 #define   SDRAM_WDDCTR_WRCP_180DEG   0x80000000
 592 #define SDRAM_WDDCTR_DCD_MASK        0x000001FF
 593
 594 /*-----------------------------------------------------------------------------+
 595 |  SDRAM CLKTR Options
 596 +-----------------------------------------------------------------------------*/
 597 #define SDRAM_CLKTR_CLKP_MASK       0xC0000000
 598 #define   SDRAM_CLKTR_CLKP_0DEG     0x00000000
 599 #define   SDRAM_CLKTR_CLKP_90DEG    0x40000000
 600 #define   SDRAM_CLKTR_CLKP_180DEG   0x80000000
 601 #define SDRAM_CLKTR_DCDT_MASK       0x000001FF
 602
 603 /*-----------------------------------------------------------------------------+
 604 |  SDRAM DLYCAL Options
 605 +-----------------------------------------------------------------------------*/
 606 #define SDRAM_DLYCAL_DLCV_MASK      0x000003FC
 607 #define   SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 608 #define   SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 609
 610 /*-----------------------------------------------------------------------------+
 611 |  General Definition
 612 +-----------------------------------------------------------------------------*/
 613 #define DEFAULT_SPD_ADDR1   0x53
 614 #define DEFAULT_SPD_ADDR2   0x52
 615 #define ONE_BILLION         1000000000
 616 #define MAXBANKS            4               /* at most 4 dimm banks */
 617 #define MAX_SPD_BYTES       256
 618 #define NUMHALFCYCLES       4
 619 #define NUMMEMTESTS         8
 620 #define NUMMEMWORDS         8
 621 #define MAXBXCR             4
 622 #define TRUE                1
 623 #define FALSE               0
 624
 625 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 626     {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 627      0xFFFFFFFF, 0xFFFFFFFF},
 628     {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 629      0x00000000, 0x00000000},
 630     {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 631      0x55555555, 0x55555555},
 632     {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 633      0xAAAAAAAA, 0xAAAAAAAA},
 634     {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 635      0x5A5A5A5A, 0x5A5A5A5A},
 636     {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 637      0xA5A5A5A5, 0xA5A5A5A5},
 638     {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 639      0x55AA55AA, 0x55AA55AA},
 640     {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 641      0xAA55AA55, 0xAA55AA55}
 642 };
 643
 644
 645 unsigned char spd_read(uchar chip, uint addr);
 646
 647 void get_spd_info(unsigned long* dimm_populated,
 648                   unsigned char* iic0_dimm_addr,
 649                   unsigned long  num_dimm_banks);
 650
 651 void check_mem_type
 652                  (unsigned long* dimm_populated,
 653                   unsigned char* iic0_dimm_addr,
 654                   unsigned long  num_dimm_banks);
 655
 656 void check_volt_type
 657                  (unsigned long* dimm_populated,
 658                   unsigned char* iic0_dimm_addr,
 659                   unsigned long  num_dimm_banks);
 660
 661 void program_cfg0(unsigned long* dimm_populated,
 662                   unsigned char* iic0_dimm_addr,
 663                   unsigned long  num_dimm_banks);
 664
 665 void program_cfg1(unsigned long* dimm_populated,
 666                   unsigned char* iic0_dimm_addr,
 667                   unsigned long  num_dimm_banks);
 668
 669 void program_rtr (unsigned long* dimm_populated,
 670                   unsigned char* iic0_dimm_addr,
 671                   unsigned long  num_dimm_banks);
 672
 673 void program_tr0 (unsigned long* dimm_populated,
 674                   unsigned char* iic0_dimm_addr,
 675                   unsigned long  num_dimm_banks);
 676
 677 void program_tr1 (void);
 678
 679 void program_ecc (unsigned long  num_bytes);
 680
 681 unsigned
 682 long  program_bxcr(unsigned long* dimm_populated,
 683                    unsigned char* iic0_dimm_addr,
 684                    unsigned long  num_dimm_banks);
 685
 686 /*
 687  * This function is reading data from the DIMM module EEPROM over the SPD bus
 688  * and uses that to program the sdram controller.
 689  *
 690  * This works on boards that has the same schematics that the IBM walnut has.
 691  *
 692  * BUG: Don't handle ECC memory
 693  * BUG: A few values in the TR register is currently hardcoded
 694  */
 695
 696 long int spd_sdram(void) {
 697     unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 698     unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 699     unsigned long total_size;
 700     unsigned long cfg0;
 701     unsigned long mcsts;
 702     unsigned long num_dimm_banks;               /* on board dimm banks */
 703
 704     num_dimm_banks = sizeof(iic0_dimm_addr);
 705
 706         /*
 707          * Make sure I2C controller is initialized
 708          * before continuing.
 709          */
 710         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 711
 712     /*
 713      * Read the SPD information using I2C interface. Check to see if the
 714      * DIMM slots are populated.
 715      */
 716     get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 717
 718     /*
 719      * Check the memory type for the dimms plugged.
 720      */
 721     check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 722
 723     /*
 724      * Check the voltage type for the dimms plugged.
 725      */
 726     check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 727
 728     /*
 729      * program 440GP SDRAM controller options (SDRAM0_CFG0)
 730      */
 731     program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 732
 733     /*
 734      * program 440GP SDRAM controller options (SDRAM0_CFG1)
 735      */
 736     program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 737
 738     /*
 739      * program SDRAM refresh register (SDRAM0_RTR)
 740      */
 741     program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 742
 743     /*
 744      * program SDRAM Timing Register 0 (SDRAM0_TR0)
 745      */
 746     program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 747
 748     /*
 749      * program the BxCR registers to find out total sdram installed
 750      */
 751     total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 752         num_dimm_banks);
 753
 754     /*
 755      * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 756      */
 757     mtsdram(mem_clktr, 0x40000000);
 758
 759     /*
 760      * delay to ensure 200 usec has elapsed
 761      */
 762     udelay(400);
 763
 764     /*
 765      * enable the memory controller
 766      */
 767     mfsdram(mem_cfg0, cfg0);
 768     mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
 769
 770     /*
 771      * wait for SDRAM_CFG0_DC_EN to complete
 772      */
 773     while(1) {
 774         mfsdram(mem_mcsts, mcsts);
 775         if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
 776             break;
 777         }
 778     }
 779
 780     /*
 781      * program SDRAM Timing Register 1, adding some delays
 782      */
 783     program_tr1();
 784
 785     /*
 786      * if ECC is enabled, initialize parity bits
 787      */
 788
 789         return total_size;
 790 }
 791
 792 unsigned char spd_read(uchar chip, uint addr) {
 793         unsigned char data[2];
 794
 795         if (i2c_read(chip, addr, 1, data, 1) == 0)
 796                 return data[0];
 797         else
 798                 return 0;
 799 }
 800
 801 void get_spd_info(unsigned long*   dimm_populated,
 802                   unsigned char*   iic0_dimm_addr,
 803                   unsigned long    num_dimm_banks)
 804 {
 805     unsigned long dimm_num;
 806     unsigned long dimm_found;
 807     unsigned char num_of_bytes;
 808     unsigned char total_size;
 809
 810     dimm_found = FALSE;
 811     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 812         num_of_bytes = 0;
 813         total_size = 0;
 814
 815         num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 816         total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 817
 818         if ((num_of_bytes != 0) && (total_size != 0)) {
 819             dimm_populated[dimm_num] = TRUE;
 820             dimm_found = TRUE;
 821 #if 0
 822             printf("DIMM slot %lu: populated\n", dimm_num);
 823 #endif
 824         }
 825         else {
 826             dimm_populated[dimm_num] = FALSE;
 827 #if 0
 828             printf("DIMM slot %lu: Not populated\n", dimm_num);
 829 #endif
 830         }
 831     }
 832
 833     if (dimm_found == FALSE) {
 834         printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 835         hang();
 836     }
 837 }
 838
 839 void check_mem_type(unsigned long*   dimm_populated,
 840                     unsigned char*   iic0_dimm_addr,
 841                     unsigned long    num_dimm_banks)
 842 {
 843     unsigned long dimm_num;
 844     unsigned char dimm_type;
 845
 846     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 847         if (dimm_populated[dimm_num] == TRUE) {
 848             dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 849             switch (dimm_type) {
 850             case 7:
 851 #if 0
 852                 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 853 #endif
 854                 break;
 855             default:
 856                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 857                     dimm_num);
 858                 printf("Only DDR SDRAM DIMMs are supported.\n");
 859                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 860                 hang();
 861                 break;
 862             }
 863         }
 864     }
 865 }
 866
 867
 868 void check_volt_type(unsigned long*   dimm_populated,
 869                      unsigned char*   iic0_dimm_addr,
 870                      unsigned long    num_dimm_banks)
 871 {
 872     unsigned long dimm_num;
 873     unsigned long voltage_type;
 874
 875     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 876         if (dimm_populated[dimm_num] == TRUE) {
 877             voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 878             if (voltage_type != 0x04) {
 879                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 880                     dimm_num);
 881                 hang();
 882             }
 883             else {
 884 #if 0
 885                 printf("DIMM %lu voltage level supported.\n", dimm_num);
 886 #endif
 887             }
 888             break;
 889         }
 890     }
 891 }
 892
 893 void program_cfg0(unsigned long* dimm_populated,
 894                   unsigned char* iic0_dimm_addr,
 895                   unsigned long  num_dimm_banks)
 896 {
 897     unsigned long dimm_num;
 898     unsigned long cfg0;
 899     unsigned long ecc_enabled;
 900     unsigned char ecc;
 901     unsigned char attributes;
 902     unsigned long data_width;
 903     unsigned long dimm_32bit;
 904     unsigned long dimm_64bit;
 905
 906     /*
 907      * get Memory Controller Options 0 data
 908      */
 909     mfsdram(mem_cfg0, cfg0);
 910
 911     /*
 912      * clear bits
 913      */
 914     cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 915               SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 916               SDRAM_CFG0_DMWD_MASK |
 917               SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 918
 919
 920     /*
 921      * FIXME: assume the DDR SDRAMs in both banks are the same
 922      */
 923     ecc_enabled = TRUE;
 924     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 925         if (dimm_populated[dimm_num] == TRUE) {
 926             ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 927             if (ecc != 0x02) {
 928                 ecc_enabled = FALSE;
 929             }
 930
 931             /*
 932              * program Registered DIMM Enable
 933              */
 934             attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 935             if ((attributes & 0x02) != 0x00) {
 936                 cfg0 |= SDRAM_CFG0_RDEN;
 937             }
 938
 939             /*
 940              * program DDR SDRAM Data Width
 941              */
 942             data_width =
 943                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 944                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 945             if (data_width == 64 || data_width == 72) {
 946                 dimm_64bit = TRUE;
 947                 cfg0 |= SDRAM_CFG0_DMWD_64;
 948             }
 949             else if (data_width == 32 || data_width == 40) {
 950                 dimm_32bit = TRUE;
 951                 cfg0 |= SDRAM_CFG0_DMWD_32;
 952             }
 953             else {
 954                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 955                     data_width);
 956                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 957                 hang();
 958             }
 959             break;
 960         }
 961     }
 962
 963     /*
 964      * program Memory Data Error Checking
 965      */
 966     if (ecc_enabled == TRUE) {
 967         cfg0 |= SDRAM_CFG0_MCHK_GEN;
 968     }
 969     else {
 970         cfg0 |= SDRAM_CFG0_MCHK_NON;
 971     }
 972
 973     /*
 974      * program Page Management Unit
 975      */
 976     cfg0 |= SDRAM_CFG0_PMUD;
 977
 978     /*
 979      * program Memory Controller Options 0
 980      * Note: DCEN must be enabled after all DDR SDRAM controller
 981      * configuration registers get initialized.
 982      */
 983     mtsdram(mem_cfg0, cfg0);
 984 }
 985
 986 void program_cfg1(unsigned long* dimm_populated,
 987                   unsigned char* iic0_dimm_addr,
 988                   unsigned long  num_dimm_banks)
 989 {
 990     unsigned long cfg1;
 991     mfsdram(mem_cfg1, cfg1);
 992
 993     /*
 994      * Self-refresh exit, disable PM
 995      */
 996     cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
 997
 998     /*
 999      * program Memory Controller Options 1
1000      */
1001     mtsdram(mem_cfg1, cfg1);
1002 }
1003
1004 void program_rtr (unsigned long* dimm_populated,
1005                   unsigned char* iic0_dimm_addr,
1006                   unsigned long  num_dimm_banks)
1007 {
1008     unsigned long dimm_num;
1009     unsigned long bus_period_x_10;
1010     unsigned long refresh_rate = 0;
1011     unsigned char refresh_rate_type;
1012     unsigned long refresh_interval;
1013     unsigned long sdram_rtr;
1014     PPC440_SYS_INFO sys_info;
1015
1016     /*
1017      * get the board info
1018      */
1019     get_sys_info(&sys_info);
1020     bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1021
1022
1023     for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
1024         if (dimm_populated[dimm_num] == TRUE) {
1025             refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1026             switch (refresh_rate_type) {
1027             case 0x00:
1028                 refresh_rate = 15625;
1029                 break;
1030             case 0x011:
1031                 refresh_rate = 15625/4;
1032                 break;
1033             case 0x02:
1034                 refresh_rate = 15625/2;
1035                 break;
1036             case 0x03:
1037                 refresh_rate = 15626*2;
1038                 break;
1039             case 0x04:
1040                 refresh_rate = 15625*4;
1041                 break;
1042             case 0x05:
1043                 refresh_rate = 15625*8;
1044                 break;
1045             default:
1046                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1047                     dimm_num);
1048                 printf("Replace the DIMM module with a supported DIMM.\n");
1049                 break;
1050             }
1051
1052             break;
1053         }
1054     }
1055
1056     refresh_interval = refresh_rate * 10 / bus_period_x_10;
1057     sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
1058
1059     /*
1060      * program Refresh Timer Register (SDRAM0_RTR)
1061      */
1062     mtsdram(mem_rtr, sdram_rtr);
1063 }
1064
1065 void program_tr0 (unsigned long* dimm_populated,
1066                   unsigned char* iic0_dimm_addr,
1067                   unsigned long  num_dimm_banks)
1068 {
1069     unsigned long dimm_num;
1070     unsigned long tr0;
1071     unsigned char wcsbc;
1072     unsigned char t_rp_ns;
1073     unsigned char t_rcd_ns;
1074     unsigned char t_ras_ns;
1075     unsigned long t_rp_clk;
1076     unsigned long t_ras_rcd_clk;
1077     unsigned long t_rcd_clk;
1078     unsigned long t_rfc_clk;
1079     unsigned long plb_check;
1080     unsigned char cas_bit;
1081     unsigned long cas_index;
1082     unsigned char cas_2_0_available;
1083     unsigned char cas_2_5_available;
1084     unsigned char cas_3_0_available;
1085     unsigned long cycle_time_ns_x_10[3];
1086     unsigned long tcyc_3_0_ns_x_10;
1087     unsigned long tcyc_2_5_ns_x_10;
1088     unsigned long tcyc_2_0_ns_x_10;
1089     unsigned long tcyc_reg;
1090     unsigned long bus_period_x_10;
1091     PPC440_SYS_INFO sys_info;
1092     unsigned long residue;
1093
1094     /*
1095      * get the board info
1096      */
1097     get_sys_info(&sys_info);
1098     bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1099
1100     /*
1101      * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1102      */
1103     mfsdram(mem_tr0, tr0);
1104     tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1105              SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1106              SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1107              SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
1108
1109     /*
1110      * initialization
1111      */
1112     wcsbc = 0;
1113     t_rp_ns = 0;
1114     t_rcd_ns = 0;
1115     t_ras_ns = 0;
1116     cas_2_0_available = TRUE;
1117     cas_2_5_available = TRUE;
1118     cas_3_0_available = TRUE;
1119     tcyc_2_0_ns_x_10 = 0;
1120     tcyc_2_5_ns_x_10 = 0;
1121     tcyc_3_0_ns_x_10 = 0;
1122
1123     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1124         if (dimm_populated[dimm_num] == TRUE) {
1125             wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1126             t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1127             t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1128             t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1129             cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1130
1131             for (cas_index = 0; cas_index < 3; cas_index++) {
1132                 switch (cas_index) {
1133                 case 0:
1134                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1135                     break;
1136                 case 1:
1137                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1138                     break;
1139                 default:
1140                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1141                     break;
1142                 }
1143
1144                 if ((tcyc_reg & 0x0F) >= 10) {
1145                     printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1146                         dimm_num);
1147                     hang();
1148                 }
1149
1150                 cycle_time_ns_x_10[cas_index] =
1151                     (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1152             }
1153
1154             cas_index = 0;
1155
1156             if ((cas_bit & 0x80) != 0) {
1157                 cas_index += 3;
1158             }
1159             else if ((cas_bit & 0x40) != 0) {
1160                 cas_index += 2;
1161             }
1162             else if ((cas_bit & 0x20) != 0) {
1163                 cas_index += 1;
1164             }
1165
1166             if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1167                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1168                 cas_index++;
1169             }
1170             else {
1171                 if (cas_index != 0) {
1172                     cas_index++;
1173                 }
1174                 cas_3_0_available = FALSE;
1175             }
1176
1177             if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1178                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1179                 cas_index++;
1180             }
1181             else {
1182                 if (cas_index != 0) {
1183                     cas_index++;
1184                 }
1185                 cas_2_5_available = FALSE;
1186             }
1187
1188             if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1189                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1190                 cas_index++;
1191             }
1192             else {
1193                 if (cas_index != 0) {
1194                     cas_index++;
1195                 }
1196                 cas_2_0_available = FALSE;
1197             }
1198
1199             break;
1200         }
1201     }
1202
1203     /*
1204      * Program SD_WR and SD_WCSBC fields
1205      */
1206     tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
1207     switch (wcsbc) {
1208     case 0:
1209         tr0 |= SDRAM_TR0_SDWD_0_CLK;
1210         break;
1211     default:
1212         tr0 |= SDRAM_TR0_SDWD_1_CLK;
1213         break;
1214     }
1215
1216     /*
1217      * Program SD_CASL field
1218      */
1219     if ((cas_2_0_available == TRUE) &&
1220         (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1221         tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1222     }
1223     else if((cas_2_5_available == TRUE) &&
1224         (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1225         tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1226     }
1227     else if((cas_3_0_available == TRUE) &&
1228         (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1229         tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1230     }
1231     else {
1232         printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1233         printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1234         printf("Make sure the PLB speed is within the supported range.\n");
1235         hang();
1236     }
1237
1238     /*
1239      * Calculate Trp in clock cycles and round up if necessary
1240      * Program SD_PTA field
1241      */
1242     t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1243     plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1244     if (sys_info.freqPLB != plb_check) {
1245         t_rp_clk++;
1246     }
1247     switch ((unsigned long)t_rp_clk) {
1248     case 0:
1249     case 1:
1250     case 2:
1251         tr0 |= SDRAM_TR0_SDPA_2_CLK;
1252         break;
1253     case 3:
1254         tr0 |= SDRAM_TR0_SDPA_3_CLK;
1255         break;
1256     default:
1257         tr0 |= SDRAM_TR0_SDPA_4_CLK;
1258         break;
1259     }
1260
1261     /*
1262      * Program SD_CTP field
1263      */
1264     t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1265     plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1266     if (sys_info.freqPLB != plb_check) {
1267         t_ras_rcd_clk++;
1268     }
1269     switch (t_ras_rcd_clk) {
1270     case 0:
1271     case 1:
1272     case 2:
1273       tr0 |= SDRAM_TR0_SDCP_2_CLK;
1274       break;
1275     case 3:
1276       tr0 |= SDRAM_TR0_SDCP_3_CLK;
1277       break;
1278     case 4:
1279       tr0 |= SDRAM_TR0_SDCP_4_CLK;
1280       break;
1281     default:
1282       tr0 |= SDRAM_TR0_SDCP_5_CLK;
1283       break;
1284     }
1285
1286     /*
1287      * Program SD_LDF field
1288      */
1289     tr0 |= SDRAM_TR0_SDLD_2_CLK;
1290
1291     /*
1292      * Program SD_RFTA field
1293      * FIXME tRFC hardcoded as 75 nanoseconds
1294      */
1295     t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1296     residue = sys_info.freqPLB % (ONE_BILLION / 75);
1297     if (residue >= (ONE_BILLION / 150)) {
1298         t_rfc_clk++;
1299     }
1300     switch (t_rfc_clk) {
1301     case 0:
1302     case 1:
1303     case 2:
1304     case 3:
1305     case 4:
1306     case 5:
1307     case 6:
1308         tr0 |= SDRAM_TR0_SDRA_6_CLK;
1309         break;
1310     case 7:
1311         tr0 |= SDRAM_TR0_SDRA_7_CLK;
1312         break;
1313     case 8:
1314         tr0 |= SDRAM_TR0_SDRA_8_CLK;
1315         break;
1316     case 9:
1317         tr0 |= SDRAM_TR0_SDRA_9_CLK;
1318         break;
1319     case 10:
1320         tr0 |= SDRAM_TR0_SDRA_10_CLK;
1321         break;
1322     case 11:
1323         tr0 |= SDRAM_TR0_SDRA_11_CLK;
1324         break;
1325     case 12:
1326         tr0 |= SDRAM_TR0_SDRA_12_CLK;
1327         break;
1328     default:
1329         tr0 |= SDRAM_TR0_SDRA_13_CLK;
1330         break;
1331     }
1332
1333     /*
1334      * Program SD_RCD field
1335      */
1336     t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1337     plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1338     if (sys_info.freqPLB != plb_check) {
1339         t_rcd_clk++;
1340     }
1341     switch (t_rcd_clk) {
1342     case 0:
1343     case 1:
1344     case 2:
1345         tr0 |= SDRAM_TR0_SDRD_2_CLK;
1346         break;
1347     case 3:
1348         tr0 |= SDRAM_TR0_SDRD_3_CLK;
1349         break;
1350     default:
1351         tr0 |= SDRAM_TR0_SDRD_4_CLK;
1352         break;
1353     }
1354
1355 #if 0
1356     printf("tr0: %x\n", tr0);
1357 #endif
1358     mtsdram(mem_tr0, tr0);
1359 }
1360
1361 void program_tr1 (void)
1362 {
1363     unsigned long tr0;
1364     unsigned long tr1;
1365     unsigned long cfg0;
1366     unsigned long ecc_temp;
1367     unsigned long dlycal;
1368     unsigned long dly_val;
1369     unsigned long i, j, k;
1370     unsigned long bxcr_num;
1371     unsigned long max_pass_length;
1372     unsigned long current_pass_length;
1373     unsigned long current_fail_length;
1374     unsigned long current_start;
1375     unsigned long rdclt;
1376     unsigned long rdclt_offset;
1377     long max_start;
1378     long max_end;
1379     long rdclt_average;
1380     unsigned char window_found;
1381     unsigned char fail_found;
1382     unsigned char pass_found;
1383     unsigned long * membase;
1384     PPC440_SYS_INFO sys_info;
1385
1386     /*
1387      * get the board info
1388      */
1389     get_sys_info(&sys_info);
1390
1391     /*
1392      * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1393      */
1394     mfsdram(mem_tr1, tr1);
1395     tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1396              SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1397
1398     mfsdram(mem_tr0, tr0);
1399     if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1400        (sys_info.freqPLB > 100000000)) {
1401         tr1 |= SDRAM_TR1_RDSS_TR2;
1402         tr1 |= SDRAM_TR1_RDSL_STAGE3;
1403         tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1404     }
1405     else {
1406         tr1 |= SDRAM_TR1_RDSS_TR1;
1407         tr1 |= SDRAM_TR1_RDSL_STAGE2;
1408         tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1409     }
1410
1411     /*
1412      * save CFG0 ECC setting to a temporary variable and turn ECC off
1413      */
1414     mfsdram(mem_cfg0, cfg0);
1415     ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1416     mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1417
1418     /*
1419      * get the delay line calibration register value
1420      */
1421     mfsdram(mem_dlycal, dlycal);
1422     dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1423
1424     max_pass_length = 0;
1425     max_start = 0;
1426     max_end = 0;
1427     current_pass_length = 0;
1428     current_fail_length = 0;
1429     current_start = 0;
1430     rdclt_offset = 0;
1431     window_found = FALSE;
1432     fail_found = FALSE;
1433     pass_found = FALSE;
1434 #ifdef DEBUG
1435     printf("Starting memory test ");
1436 #endif
1437     for (k = 0; k < NUMHALFCYCLES; k++) {
1438         for (rdclt = 0; rdclt < dly_val; rdclt++)  {
1439             /*
1440              * Set the timing reg for the test.
1441              */
1442             mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1443
1444             for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1445                 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1446                 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1447                     /* Bank is enabled */
1448                     membase = (unsigned long*)
1449                         (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1450
1451                     /*
1452                      * Run the short memory test
1453                      */
1454                     for (i = 0; i < NUMMEMTESTS; i++) {
1455                         for (j = 0; j < NUMMEMWORDS; j++) {
1456                             membase[j] = test[i][j];
1457                             ppcDcbf((unsigned long)&(membase[j]));
1458                         }
1459
1460                         for (j = 0; j < NUMMEMWORDS; j++) {
1461                             if (membase[j] != test[i][j]) {
1462                                 ppcDcbf((unsigned long)&(membase[j]));
1463                                 break;
1464                             }
1465                             ppcDcbf((unsigned long)&(membase[j]));
1466                         }
1467
1468                         if (j < NUMMEMWORDS) {
1469                             break;
1470                         }
1471                     }
1472
1473                     /*
1474                      * see if the rdclt value passed
1475                      */
1476                     if (i < NUMMEMTESTS) {
1477                         break;
1478                     }
1479                 }
1480             }
1481
1482             if (bxcr_num == MAXBXCR) {
1483                 if (fail_found == TRUE) {
1484                     pass_found = TRUE;
1485                     if (current_pass_length == 0) {
1486                         current_start = rdclt_offset + rdclt;
1487                     }
1488
1489                     current_fail_length = 0;
1490                     current_pass_length++;
1491
1492                     if (current_pass_length > max_pass_length) {
1493                         max_pass_length = current_pass_length;
1494                         max_start = current_start;
1495                         max_end = rdclt_offset + rdclt;
1496                     }
1497                 }
1498             }
1499             else {
1500                 current_pass_length = 0;
1501                 current_fail_length++;
1502
1503                 if (current_fail_length >= (dly_val>>2)) {
1504                     if (fail_found == FALSE) {
1505                         fail_found = TRUE;
1506                     }
1507                     else if (pass_found == TRUE) {
1508                         window_found = TRUE;
1509                         break;
1510                     }
1511                 }
1512             }
1513         }
1514 #ifdef DEBUG
1515         printf(".");
1516 #endif
1517         if (window_found == TRUE) {
1518             break;
1519         }
1520
1521         tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1522         rdclt_offset += dly_val;
1523     }
1524 #ifdef DEBUG
1525     printf("\n");
1526 #endif
1527
1528     /*
1529      * make sure we find the window
1530      */
1531     if (window_found == FALSE) {
1532        printf("ERROR: Cannot determine a common read delay.\n");
1533        hang();
1534     }
1535
1536     /*
1537      * restore the orignal ECC setting
1538      */
1539     mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1540
1541     /*
1542      * set the SDRAM TR1 RDCD value
1543      */
1544     tr1 &= ~SDRAM_TR1_RDCD_MASK;
1545     if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1546         tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1547     }
1548     else {
1549         tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1550     }
1551
1552     /*
1553      * set the SDRAM TR1 RDCLT value
1554      */
1555     tr1 &= ~SDRAM_TR1_RDCT_MASK;
1556     while (max_end >= (dly_val<<1)) {
1557         max_end -= (dly_val<<1);
1558         max_start -= (dly_val<<1);
1559     }
1560
1561     rdclt_average = ((max_start + max_end) >> 1);
1562     if (rdclt_average >= 0x60)
1563         while(1);
1564
1565     if (rdclt_average < 0) {
1566         rdclt_average = 0;
1567     }
1568
1569     if (rdclt_average >= dly_val) {
1570         rdclt_average -= dly_val;
1571         tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1572     }
1573     tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1574
1575 #if 0
1576     printf("tr1: %x\n", tr1);
1577 #endif
1578     /*
1579      * program SDRAM Timing Register 1 TR1
1580      */
1581     mtsdram(mem_tr1, tr1);
1582 }
1583
1584 unsigned long program_bxcr(unsigned long* dimm_populated,
1585                            unsigned char* iic0_dimm_addr,
1586                            unsigned long  num_dimm_banks)
1587 {
1588     unsigned long dimm_num;
1589     unsigned long bxcr_num;
1590     unsigned long bank_base_addr;
1591     unsigned long bank_size_bytes;
1592     unsigned long cr;
1593     unsigned long i;
1594     unsigned long temp;
1595     unsigned char num_row_addr;
1596     unsigned char num_col_addr;
1597     unsigned char num_banks;
1598     unsigned char bank_size_id;
1599
1600
1601     /*
1602      * Set the BxCR regs.  First, wipe out the bank config registers.
1603      */
1604     for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1605         mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1606         mtdcr(memcfgd, 0x00000000);
1607     }
1608
1609     /*
1610      * reset the bank_base address
1611      */
1612     bank_base_addr = CFG_SDRAM_BASE;
1613
1614     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1615         if (dimm_populated[dimm_num] == TRUE) {
1616             num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1617             num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1618             num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1619             bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1620
1621             /*
1622              * Set the SDRAM0_BxCR regs
1623              */
1624             cr = 0;
1625             bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
1626             switch (bank_size_id) {
1627             case 0x02:
1628                 cr |= SDRAM_BXCR_SDSZ_8;
1629                 break;
1630             case 0x04:
1631                 cr |= SDRAM_BXCR_SDSZ_16;
1632                 break;
1633             case 0x08:
1634                 cr |= SDRAM_BXCR_SDSZ_32;
1635                 break;
1636             case 0x10:
1637                 cr |= SDRAM_BXCR_SDSZ_64;
1638                 break;
1639             case 0x20:
1640                 cr |= SDRAM_BXCR_SDSZ_128;
1641                 break;
1642             case 0x40:
1643                 cr |= SDRAM_BXCR_SDSZ_256;
1644                 break;
1645             case 0x80:
1646                 cr |= SDRAM_BXCR_SDSZ_512;
1647                 break;
1648             default:
1649                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1650                     dimm_num);
1651                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1652                    bank_size_id);
1653                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1654                 hang();
1655             }
1656
1657             switch (num_col_addr) {
1658             case 0x08:
1659                 cr |= SDRAM_BXCR_SDAM_1;
1660                 break;
1661             case 0x09:
1662                 cr |= SDRAM_BXCR_SDAM_2;
1663                 break;
1664             case 0x0A:
1665                 cr |= SDRAM_BXCR_SDAM_3;
1666                 break;
1667             case 0x0B:
1668                 cr |= SDRAM_BXCR_SDAM_4;
1669                 break;
1670             default:
1671                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1672                    dimm_num);
1673                 printf("ERROR: Unsupported value for number of "
1674                    "column addresses: %d.\n", num_col_addr);
1675                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1676                 hang();
1677             }
1678
1679             /*
1680              * enable the bank
1681              */
1682             cr |= SDRAM_BXCR_SDBE;
1683
1684             /*------------------------------------------------------------------
1685             | This next section is hardware dependent and must be programmed
1686             | to match the hardware.
1687             +-----------------------------------------------------------------*/
1688             if (dimm_num == 0) {
1689                 for (i = 0; i < num_banks; i++) {
1690                     mtdcr(memcfga, mem_b0cr + (i << 2));
1691                     temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1692                                               SDRAM_BXCR_SDSZ_MASK |
1693                                               SDRAM_BXCR_SDAM_MASK |
1694                                               SDRAM_BXCR_SDBE);
1695                     cr |= temp;
1696                     cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1697                     mtdcr(memcfgd, cr);
1698                     bank_base_addr += bank_size_bytes;
1699                 }
1700             }
1701             else {
1702                 for (i = 0; i < num_banks; i++) {
1703                     mtdcr(memcfga, mem_b2cr + (i << 2));
1704                     temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1705                                               SDRAM_BXCR_SDSZ_MASK |
1706                                               SDRAM_BXCR_SDAM_MASK |
1707                                               SDRAM_BXCR_SDBE);
1708                     cr |= temp;
1709                     cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1710                     mtdcr(memcfgd, cr);
1711                     bank_base_addr += bank_size_bytes;
1712                 }
1713             }
1714         }
1715     }
1716
1717     return(bank_base_addr);
1718 }
1719
1720 void program_ecc (unsigned long  num_bytes)
1721 {
1722     unsigned long bank_base_addr;
1723     unsigned long current_address;
1724     unsigned long end_address;
1725     unsigned long address_increment;
1726     unsigned long cfg0;
1727
1728     /*
1729      * get Memory Controller Options 0 data
1730      */
1731     mfsdram(mem_cfg0, cfg0);
1732
1733     /*
1734      * reset the bank_base address
1735      */
1736     bank_base_addr = CFG_SDRAM_BASE;
1737
1738     if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1739         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1740             SDRAM_CFG0_MCHK_GEN);
1741
1742         if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1743             address_increment = 4;
1744         }
1745         else {
1746             address_increment = 8;
1747         }
1748
1749         current_address = (unsigned long)(bank_base_addr);
1750         end_address = (unsigned long)(bank_base_addr) + num_bytes;
1751
1752         while (current_address < end_address) {
1753             *((unsigned long*)current_address) = 0x00000000;
1754             current_address += address_increment;
1755         }
1756
1757         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1758             SDRAM_CFG0_MCHK_CHK);
1759     }
1760 }
1761
1762 #endif /* CONFIG_440 */
1763
1764 #endif /* CONFIG_SPD_EEPROM */