cpu/pxa/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (C) 2001  Alex Züpke <azu@sysgo.de>
   8  *  Copyright (C) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
  10  *  Copyright (C) 2003  Kai-Uwe Bloehm <kai-uwe.bloem@auerswald.de>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33
  34 .globl _start
  35 _start: b       reset
  36         ldr     pc, _undefined_instruction
  37         ldr     pc, _software_interrupt
  38         ldr     pc, _prefetch_abort
  39         ldr     pc, _data_abort
  40         ldr     pc, _not_used
  41         ldr     pc, _irq
  42         ldr     pc, _fiq
  43
  44 _undefined_instruction: .word undefined_instruction
  45 _software_interrupt:    .word software_interrupt
  46 _prefetch_abort:        .word prefetch_abort
  47 _data_abort:            .word data_abort
  48 _not_used:              .word not_used
  49 _irq:                   .word irq
  50 _fiq:                   .word fiq
  51
  52         .balignl 16,0xdeadbeef
  53
  54
  55 /*
  56  * Startup Code (reset vector)
  57  *
  58  * do important init only if we don't start from memory!
  59  * - relocate armboot to ram
  60  * - setup stack
  61  * - jump to second stage
  62  */
  63
  64 /*
  65  * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
  66  */
  67 _TEXT_BASE:
  68         .word   TEXT_BASE
  69
  70 .globl _armboot_start
  71 _armboot_start:
  72         .word _start
  73
  74 /*
  75  * Note: _armboot_end_data and _armboot_end are defined
  76  * by the (board-dependent) linker script.
  77  * _armboot_end_data is the first usable FLASH address after armboot
  78  */
  79 .globl _armboot_end_data
  80 _armboot_end_data:
  81         .word armboot_end_data
  82 .globl _armboot_end
  83 _armboot_end:
  84         .word armboot_end
  85
  86 /*
  87  * This is defined in the board specific linker script
  88  */
  89 .globl _bss_start
  90 _bss_start:
  91         .word bss_start
  92
  93 .globl _bss_end
  94 _bss_end:
  95         .word bss_end
  96
  97 /*
  98  * _armboot_real_end is the first usable RAM address behind armboot
  99  * and the various stacks
 100  */
 101 .globl _armboot_real_end
 102 _armboot_real_end:
 103         .word 0x0badc0de
 104
 105 /*
 106  * We relocate uboot to this address (end of RAM - 128 KiB)
 107  */
 108 .globl _uboot_reloc
 109 _uboot_reloc:
 110         .word TEXT_BASE
 111
 112 #ifdef CONFIG_USE_IRQ
 113 /* IRQ stack memory (calculated at run-time) */
 114 .globl IRQ_STACK_START
 115 IRQ_STACK_START:
 116         .word   0x0badc0de
 117
 118 /* IRQ stack memory (calculated at run-time) */
 119 .globl FIQ_STACK_START
 120 FIQ_STACK_START:
 121         .word 0x0badc0de
 122 #endif
 123
 124
 125 /****************************************************************************/
 126 /*                                                                          */
 127 /* the actual reset code                                                    */
 128 /*                                                                          */
 129 /****************************************************************************/
 130
 131 reset:
 132         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 133         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 134         orr     r0,r0,#0x13
 135         msr     cpsr,r0
 136
 137         bl      cpu_init_crit           /* we do sys-critical inits         */
 138
 139 relocate:                               /* relocate U-Boot to RAM           */
 140         adr     r0, _start              /* r0 <- current position of code   */
 141         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 142         cmp     r0, r1                  /* don't reloc during debug         */
 143         beq     stack_setup
 144
 145         ldr     r2, _armboot_start
 146         ldr     r3, _armboot_end
 147         sub     r2, r3, r2              /* r2 <- size of armboot            */
 148         add     r2, r0, r2              /* r2 <- source end address         */
 149
 150 copy_loop:
 151         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 152         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 153         cmp     r0, r2                  /* until source end addreee [r2]    */
 154         ble     copy_loop
 155
 156         /* Set up the stack                                                 */
 157
 158 stack_setup:
 159
 160         ldr     r0, _uboot_reloc        /* upper 128 KiB: relocated uboot   */
 161         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 162                                         /* FIXME: bdinfo should be here     */
 163         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 164
 165 clear_bss:
 166
 167         ldr     r0, _bss_start          /* find start of bss segment        */
 168         add     r0, r0, #4              /* start at first byte of bss       */
 169         ldr     r1, _bss_end            /* stop here                        */
 170         mov     r2, #0x00000000         /* clear                            */
 171
 172 clbss_l:str     r2, [r0]                /* clear loop...                    */
 173         add     r0, r0, #4
 174         cmp     r0, r1
 175         bne     clbss_l
 176
 177
 178         ldr     pc, _start_armboot
 179
 180 _start_armboot: .word start_armboot
 181
 182
 183 /****************************************************************************/
 184 /*                                                                          */
 185 /* CPU_init_critical registers                                              */
 186 /*                                                                          */
 187 /* - setup important registers                                              */
 188 /* - setup memory timing                                                    */
 189 /*                                                                          */
 190 /****************************************************************************/
 191
 192 /* Interrupt-Controller base address                                        */
 193 IC_BASE:           .word           0x40d00000
 194 #define ICMR    0x04
 195
 196 /* Reset-Controller */
 197 RST_BASE:       .word   0x40f00030
 198 #define RCSR    0x00
 199
 200 /* Operating System Timer */
 201 OSTIMER_BASE:   .word   0x40a00000
 202 #define OSMR3   0x0C
 203 #define OSCR    0x10
 204 #define OWER    0x18
 205 #define OIER    0x1C
 206
 207 /* Clock Manager Registers                                                  */
 208 CC_BASE:        .word   0x41300000
 209 #define CCCR    0x00
 210 cpuspeed:       .word   CFG_CPUSPEED
 211
 212
 213         /* RS: ???                                                          */
 214         .macro CPWAIT
 215         mrc  p15,0,r0,c2,c0,0
 216         mov  r0,r0
 217         sub  pc,pc,#4
 218         .endm
 219
 220
 221 cpu_init_crit:
 222
 223         /* mask all IRQs                                                    */
 224         ldr     r0, IC_BASE
 225         mov     r1, #0x00
 226         str     r1, [r0, #ICMR]
 227
 228 #if defined(CFG_CPUSPEED)
 229
 230         /* set clock speed */
 231         ldr     r0, CC_BASE
 232         ldr     r1, cpuspeed
 233         str     r1, [r0, #CCCR]
 234         mov     r0, #2
 235         mcr     p14, 0, r0, c6, c0, 0
 236
 237 setspeed_done:
 238 #endif
 239
 240         /*
 241          * before relocating, we have to setup RAM timing
 242          * because memory timing is board-dependend, you will
 243          * find a memsetup.S in your board directory.
 244          */
 245         mov     ip,     lr
 246         bl      memsetup
 247         mov     lr,     ip
 248
 249         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 250
 251         ldr     r0, =0x2001             /* enable access to all coproc.     */
 252         mcr     p15, 0, r0, c15, c1, 0
 253         CPWAIT
 254
 255         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 256         CPWAIT
 257
 258         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 259         CPWAIT
 260
 261         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 262         CPWAIT
 263
 264         /* Enable the Icache                                                */
 265 /*
 266         mrc     p15, 0, r0, c1, c0, 0
 267         orr     r0, r0, #0x1800
 268         mcr     p15, 0, r0, c1, c0, 0
 269         CPWAIT
 270 */
 271         mov     pc, lr
 272
 273
 274 /****************************************************************************/
 275 /*                                                                          */
 276 /* Interrupt handling                                                       */
 277 /*                                                                          */
 278 /****************************************************************************/
 279
 280 /* IRQ stack frame                                                          */
 281
 282 #define S_FRAME_SIZE    72
 283
 284 #define S_OLD_R0        68
 285 #define S_PSR           64
 286 #define S_PC            60
 287 #define S_LR            56
 288 #define S_SP            52
 289
 290 #define S_IP            48
 291 #define S_FP            44
 292 #define S_R10           40
 293 #define S_R9            36
 294 #define S_R8            32
 295 #define S_R7            28
 296 #define S_R6            24
 297 #define S_R5            20
 298 #define S_R4            16
 299 #define S_R3            12
 300 #define S_R2            8
 301 #define S_R1            4
 302 #define S_R0            0
 303
 304 #define MODE_SVC 0x13
 305
 306         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 307
 308         .macro  bad_save_user_regs
 309         sub     sp, sp, #S_FRAME_SIZE
 310         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 311         add     r8, sp, #S_PC
 312
 313         ldr     r2, _armboot_end
 314         add     r2, r2, #CONFIG_STACKSIZE
 315         sub     r2, r2, #8
 316         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 317         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 318
 319         add     r5, sp, #S_SP
 320         mov     r1, lr
 321         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 322         mov     r0, sp
 323         .endm
 324
 325
 326         /* use irq_save_user_regs / irq_restore_user_regs for                */
 327         /* IRQ/FIQ handling                                                  */
 328
 329         .macro  irq_save_user_regs
 330         sub     sp, sp, #S_FRAME_SIZE
 331         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 332         add     r8, sp, #S_PC
 333         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 334         str     lr, [r8, #0]                    /* Save calling PC           */
 335         mrs     r6, spsr
 336         str     r6, [r8, #4]                    /* Save CPSR                 */
 337         str     r0, [r8, #8]                    /* Save OLD_R0               */
 338         mov     r0, sp
 339         .endm
 340
 341         .macro  irq_restore_user_regs
 342         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 343         mov     r0, r0
 344         ldr     lr, [sp, #S_PC]                 @ Get PC
 345         add     sp, sp, #S_FRAME_SIZE
 346         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 347         .endm
 348
 349         .macro get_bad_stack
 350         ldr     r13, _armboot_end               @ setup our mode stack
 351         add     r13, r13, #CONFIG_STACKSIZE     @ resides at top of normal stack
 352         sub     r13, r13, #8
 353
 354         str     lr, [r13]                       @ save caller lr / spsr
 355         mrs     lr, spsr
 356         str     lr, [r13, #4]
 357
 358         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 359         msr     spsr_c, r13
 360         mov     lr, pc
 361         movs    pc, lr
 362         .endm
 363
 364         .macro get_irq_stack                    @ setup IRQ stack
 365         ldr     sp, IRQ_STACK_START
 366         .endm
 367
 368         .macro get_fiq_stack                    @ setup FIQ stack
 369         ldr     sp, FIQ_STACK_START
 370         .endm
 371
 372
 373 /****************************************************************************/
 374 /*                                                                          */
 375 /* exception handlers                                                       */
 376 /*                                                                          */
 377 /****************************************************************************/
 378
 379         .align  5
 380 undefined_instruction:
 381         get_bad_stack
 382         bad_save_user_regs
 383         bl      do_undefined_instruction
 384
 385         .align  5
 386 software_interrupt:
 387         get_bad_stack
 388         bad_save_user_regs
 389         bl      do_software_interrupt
 390
 391         .align  5
 392 prefetch_abort:
 393         get_bad_stack
 394         bad_save_user_regs
 395         bl      do_prefetch_abort
 396
 397         .align  5
 398 data_abort:
 399         get_bad_stack
 400         bad_save_user_regs
 401         bl      do_data_abort
 402
 403         .align  5
 404 not_used:
 405         get_bad_stack
 406         bad_save_user_regs
 407         bl      do_not_used
 408
 409 #ifdef CONFIG_USE_IRQ
 410
 411         .align  5
 412 irq:
 413         get_irq_stack
 414         irq_save_user_regs
 415         bl      do_irq
 416         irq_restore_user_regs
 417
 418         .align  5
 419 fiq:
 420         get_fiq_stack
 421         irq_save_user_regs              /* someone ought to write a more    */
 422         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 423         irq_restore_user_regs
 424
 425 #else
 426
 427         .align  5
 428 irq:
 429         get_bad_stack
 430         bad_save_user_regs
 431         bl      do_irq
 432
 433         .align  5
 434 fiq:
 435         get_bad_stack
 436         bad_save_user_regs
 437         bl      do_fiq
 438
 439 #endif
 440
 441 /****************************************************************************/
 442 /*                                                                          */
 443 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
 444 /* perform a watchdog timeout for a soft reset.                             */
 445 /*                                                                          */
 446 /****************************************************************************/
 447
 448         .align  5
 449 .globl reset_cpu
 450
 451         /* FIXME: this code is PXA250 specific. How is this handled on      */
 452         /*        other XScale processors?                                  */
 453
 454 reset_cpu:
 455
 456         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 457
 458         ldr     r0, OSTIMER_BASE
 459         ldr     r1, [r0, #OWER]
 460         orr     r1, r1, #0x0001                 /* bit0: WME                */
 461         str     r1, [r0, #OWER]
 462
 463         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 464         /* the match register as well.                                      */
 465
 466         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 467         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 468         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 469         str     r1, [r0, #OSMR3]
 470
 471 reset_endless:
 472
 473         b       reset_endless
 474