cpu/xscale/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (c) 2001  Alex Züpke <azu@sysgo.de>
   8  *  Copyright (c) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29
  30
  31 #include <config.h>
  32 #include <version.h>
  33
  34 .globl _start
  35 _start: b       reset
  36         ldr     pc, _undefined_instruction
  37         ldr     pc, _software_interrupt
  38         ldr     pc, _prefetch_abort
  39         ldr     pc, _data_abort
  40         ldr     pc, _not_used
  41         ldr     pc, _irq
  42         ldr     pc, _fiq
  43
  44 _undefined_instruction: .word undefined_instruction
  45 _software_interrupt:    .word software_interrupt
  46 _prefetch_abort:        .word prefetch_abort
  47 _data_abort:            .word data_abort
  48 _not_used:              .word not_used
  49 _irq:                   .word irq
  50 _fiq:                   .word fiq
  51
  52         .balignl 16,0xdeadbeef
  53
  54
  55 /*
  56  * Startup Code (reset vector)
  57  *
  58  * do important init only if we don't start from memory!
  59  * - relocate armboot to ram
  60  * - setup stack
  61  * - jump to second stage
  62  */
  63
  64 /*
  65  * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
  66  */
  67 _TEXT_BASE:
  68         .word   TEXT_BASE
  69
  70 .globl _armboot_start
  71 _armboot_start:
  72         .word _start
  73
  74 /*
  75  * Note: _armboot_end_data and _armboot_end are defined
  76  * by the (board-dependent) linker script.
  77  * _armboot_end_data is the first usable FLASH address after armboot
  78  */
  79 .globl _armboot_end_data
  80 _armboot_end_data:
  81         .word armboot_end_data
  82 .globl _armboot_end
  83 _armboot_end:
  84         .word armboot_end
  85
  86 /*
  87  * _armboot_real_end is the first usable RAM address behind armboot
  88  * and the various stacks
  89  */
  90 .globl _armboot_real_end
  91 _armboot_real_end:
  92         .word 0x0badc0de
  93
  94 /*
  95  * We relocate uboot to this address (end of RAM - 128 KiB)
  96  */
  97 .globl _uboot_reloc
  98 _uboot_reloc:
  99         .word TEXT_BASE
 100
 101 #ifdef CONFIG_USE_IRQ
 102 /* IRQ stack memory (calculated at run-time) */
 103 .globl IRQ_STACK_START
 104 IRQ_STACK_START:
 105         .word   0x0badc0de
 106
 107 /* IRQ stack memory (calculated at run-time) */
 108 .globl FIQ_STACK_START
 109 FIQ_STACK_START:
 110         .word 0x0badc0de
 111 #endif
 112
 113
 114 /****************************************************************************/
 115 /*                                                                          */
 116 /* the actual reset code                                                    */
 117 /*                                                                          */
 118 /****************************************************************************/
 119
 120 reset:
 121         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 122         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 123         orr     r0,r0,#0x13
 124         msr     cpsr,r0
 125
 126         bl      cpu_init_crit           /* we do sys-critical inits         */
 127
 128 relocate:                               /* relocate U-Boot to RAM          */
 129         adr     r0, _start              /* r0 <- current position of code */
 130         ldr     r2, _armboot_start
 131         ldr     r3, _armboot_end
 132         sub     r2, r3, r2              /* r2 <- size of armboot */
 133         ldr     r1, _TEXT_BASE
 134         add     r2, r0, r2              /* r2 <- source end address */
 135
 136 copy_loop:
 137         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 138         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 139         cmp     r0, r2                  /* until source end addreee [r2]    */
 140         ble     copy_loop
 141
 142         /* Set up the stack                                                 */
 143         ldr     r0, _uboot_reloc        /* upper 128 KiB: relocated uboot   */
 144         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 145                                         /* FIXME: bdinfo should be here     */
 146         sub     sp, r0, #12             /* leave 3 words for abort-stack */
 147
 148         ldr     pc, _start_armboot
 149
 150 _start_armboot: .word start_armboot
 151
 152
 153 /****************************************************************************/
 154 /*                                                                          */
 155 /* CPU_init_critical registers                                              */
 156 /*                                                                          */
 157 /* - setup important registers                                              */
 158 /* - setup memory timing                                                    */
 159 /*                                                                          */
 160 /****************************************************************************/
 161
 162         /* Interrupt-Controller base address                                */
 163 IC_BASE:           .word           0x40d00000
 164 #define ICMR    0x04
 165
 166 /* Reset-Controller */
 167 RST_BASE:       .word   0x40f00030
 168 #define RCSR    0x00
 169
 170         /* Operating System Timer */
 171 OSTIMER_BASE:   .word   0x40a00000
 172 #define OSMR3   0x0C
 173 #define OSCR    0x10
 174 #define OWER    0x18
 175 #define OIER    0x1C
 176
 177         /* Clock Manager Registers                                          */
 178 CC_BASE:        .word   0x41300000
 179 #define CCCR    0x00
 180 cpuspeed:       .word   CFG_CPUSPEED
 181
 182         /* RS: ???                                                          */
 183         .macro CPWAIT
 184         mrc  p15,0,r0,c2,c0,0
 185         mov  r0,r0
 186         sub  pc,pc,#4
 187         .endm
 188
 189
 190 cpu_init_crit:
 191
 192         /* mask all IRQs                                                    */
 193         ldr     r0, IC_BASE
 194         mov     r1, #0x00
 195         str     r1, [r0, #ICMR]
 196
 197         /* set clock speed */
 198         ldr     r0, CC_BASE
 199         ldr     r1, cpuspeed
 200         str     r1, [r0, #CCCR]
 201
 202         /*
 203          * before relocating, we have to setup RAM timing
 204          * because memory timing is board-dependend, you will
 205          * find a memsetup.S in your board directory.
 206          */
 207         mov     ip,     lr
 208         bl      memsetup
 209         mov     lr,     ip
 210
 211         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 212
 213         ldr     r0, =0x2001             /* enable access to all coproc.     */
 214         mcr     p15, 0, r0, c15, c1, 0
 215         CPWAIT
 216
 217         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 218         CPWAIT
 219
 220         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 221         CPWAIT
 222
 223         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 224         CPWAIT
 225
 226         /* Enable the Icache                                                */
 227 /*
 228         mrc     p15, 0, r0, c1, c0, 0
 229         orr     r0, r0, #0x1800
 230         mcr     p15, 0, r0, c1, c0, 0
 231         CPWAIT
 232 */
 233         mov     pc, lr
 234
 235
 236 /****************************************************************************/
 237 /*                                                                          */
 238 /* Interrupt handling                                                       */
 239 /*                                                                          */
 240 /****************************************************************************/
 241
 242 /* IRQ stack frame                                                          */
 243
 244 #define S_FRAME_SIZE    72
 245
 246 #define S_OLD_R0        68
 247 #define S_PSR           64
 248 #define S_PC            60
 249 #define S_LR            56
 250 #define S_SP            52
 251
 252 #define S_IP            48
 253 #define S_FP            44
 254 #define S_R10           40
 255 #define S_R9            36
 256 #define S_R8            32
 257 #define S_R7            28
 258 #define S_R6            24
 259 #define S_R5            20
 260 #define S_R4            16
 261 #define S_R3            12
 262 #define S_R2            8
 263 #define S_R1            4
 264 #define S_R0            0
 265
 266 #define MODE_SVC 0x13
 267
 268         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 269
 270         .macro  bad_save_user_regs
 271         sub     sp, sp, #S_FRAME_SIZE
 272         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 273         add     r8, sp, #S_PC
 274
 275         ldr     r2, _armboot_end
 276         add     r2, r2, #CONFIG_STACKSIZE
 277         sub     r2, r2, #8
 278         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 279         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 280
 281         add     r5, sp, #S_SP
 282         mov     r1, lr
 283         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 284         mov     r0, sp
 285         .endm
 286
 287
 288         /* use irq_save_user_regs / irq_restore_user_regs for                */
 289         /* IRQ/FIQ handling                                                  */
 290
 291         .macro  irq_save_user_regs
 292         sub     sp, sp, #S_FRAME_SIZE
 293         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 294         add     r8, sp, #S_PC
 295         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 296         str     lr, [r8, #0]                    /* Save calling PC           */
 297         mrs     r6, spsr
 298         str     r6, [r8, #4]                    /* Save CPSR                 */
 299         str     r0, [r8, #8]                    /* Save OLD_R0               */
 300         mov     r0, sp
 301         .endm
 302
 303         .macro  irq_restore_user_regs
 304         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 305         mov     r0, r0
 306         ldr     lr, [sp, #S_PC]                 @ Get PC
 307         add     sp, sp, #S_FRAME_SIZE
 308         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 309         .endm
 310
 311         .macro get_bad_stack
 312         ldr     r13, _armboot_end               @ setup our mode stack
 313         add     r13, r13, #CONFIG_STACKSIZE     @ resides at top of normal stack
 314         sub     r13, r13, #8
 315
 316         str     lr, [r13]                       @ save caller lr / spsr
 317         mrs     lr, spsr
 318         str     lr, [r13, #4]
 319
 320         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 321         msr     spsr_c, r13
 322         mov     lr, pc
 323         movs    pc, lr
 324         .endm
 325
 326         .macro get_irq_stack                    @ setup IRQ stack
 327         ldr     sp, IRQ_STACK_START
 328         .endm
 329
 330         .macro get_fiq_stack                    @ setup FIQ stack
 331         ldr     sp, FIQ_STACK_START
 332         .endm
 333
 334
 335 /****************************************************************************/
 336 /*                                                                          */
 337 /* exception handlers                                                       */
 338 /*                                                                          */
 339 /****************************************************************************/
 340
 341         .align  5
 342 undefined_instruction:
 343         get_bad_stack
 344         bad_save_user_regs
 345         bl      do_undefined_instruction
 346
 347         .align  5
 348 software_interrupt:
 349         get_bad_stack
 350         bad_save_user_regs
 351         bl      do_software_interrupt
 352
 353         .align  5
 354 prefetch_abort:
 355         get_bad_stack
 356         bad_save_user_regs
 357         bl      do_prefetch_abort
 358
 359         .align  5
 360 data_abort:
 361         get_bad_stack
 362         bad_save_user_regs
 363         bl      do_data_abort
 364
 365         .align  5
 366 not_used:
 367         get_bad_stack
 368         bad_save_user_regs
 369         bl      do_not_used
 370
 371 #ifdef CONFIG_USE_IRQ
 372
 373         .align  5
 374 irq:
 375         get_irq_stack
 376         irq_save_user_regs
 377         bl      do_irq
 378         irq_restore_user_regs
 379
 380         .align  5
 381 fiq:
 382         get_fiq_stack
 383         irq_save_user_regs              /* someone ought to write a more    */
 384         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 385         irq_restore_user_regs
 386
 387 #else
 388
 389         .align  5
 390 irq:
 391         get_bad_stack
 392         bad_save_user_regs
 393         bl      do_irq
 394
 395         .align  5
 396 fiq:
 397         get_bad_stack
 398         bad_save_user_regs
 399         bl      do_fiq
 400
 401 #endif
 402
 403 /************************************************************************/
 404 /*                                                                      */
 405 /* Reset function: the PXA250 has no reset function, so we have to      */
 406 /* perform a watchdog timeout to cause a reset.                         */
 407 /*                                                                      */
 408 /************************************************************************/
 409         .align  5
 410 .globl reset_cpu
 411 reset_cpu:
 412         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 413
 414         ldr     r0, OSTIMER_BASE
 415         ldr     r1, [r0, #OWER]
 416         orr     r1, r1, #0x0001                 /* bit0: WME                */
 417         str     r1, [r0, #OWER]
 418
 419         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 420         /* the match register as well.                                      */
 421
 422         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 423         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 424         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 425         str     r1, [r0, #OSMR3]
 426
 427 reset_endless:
 428
 429         b       reset_endless