cpu/xscale/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (c) 2001  Alex Züpke <azu@sysgo.de>
   8  *  Copyright (c) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29
  30
  31 #include <config.h>
  32 #include <version.h>
  33
  34 .globl _start
  35 _start: b       reset
  36         ldr     pc, _undefined_instruction
  37         ldr     pc, _software_interrupt
  38         ldr     pc, _prefetch_abort
  39         ldr     pc, _data_abort
  40         ldr     pc, _not_used
  41         ldr     pc, _irq
  42         ldr     pc, _fiq
  43
  44 _undefined_instruction: .word undefined_instruction
  45 _software_interrupt:    .word software_interrupt
  46 _prefetch_abort:        .word prefetch_abort
  47 _data_abort:            .word data_abort
  48 _not_used:              .word not_used
  49 _irq:                   .word irq
  50 _fiq:                   .word fiq
  51
  52         .balignl 16,0xdeadbeef
  53
  54
  55 /*
  56  * Startup Code (reset vector)
  57  *
  58  * do important init only if we don't start from memory!
  59  * - relocate armboot to ram
  60  * - setup stack
  61  * - jump to second stage
  62  */
  63
  64 /*
  65  * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
  66  */
  67 _TEXT_BASE:
  68         .word   TEXT_BASE
  69
  70 .globl _armboot_start
  71 _armboot_start:
  72         .word _start
  73
  74 /*
  75  * Note: _armboot_end_data and _armboot_end are defined
  76  * by the (board-dependent) linker script.
  77  * _armboot_end_data is the first usable FLASH address after armboot
  78  */
  79 .globl _armboot_end_data
  80 _armboot_end_data:
  81         .word armboot_end_data
  82 .globl _armboot_end
  83 _armboot_end:
  84         .word armboot_end
  85
  86 /*
  87  * _armboot_real_end is the first usable RAM address behind armboot
  88  * and the various stacks
  89  */
  90 .globl _armboot_real_end
  91 _armboot_real_end:
  92         .word 0x0badc0de
  93
  94 /*
  95  * We relocate uboot to this address (end of RAM - 128 KiB)
  96  */
  97 .globl _uboot_reloc
  98 _uboot_reloc:
  99         .word TEXT_BASE
 100
 101 #ifdef CONFIG_USE_IRQ
 102 /* IRQ stack memory (calculated at run-time) */
 103 .globl IRQ_STACK_START
 104 IRQ_STACK_START:
 105         .word   0x0badc0de
 106
 107 /* IRQ stack memory (calculated at run-time) */
 108 .globl FIQ_STACK_START
 109 FIQ_STACK_START:
 110         .word 0x0badc0de
 111 #endif
 112
 113
 114 /****************************************************************************/
 115 /*                                                                          */
 116 /* the actual reset code                                                    */
 117 /*                                                                          */
 118 /****************************************************************************/
 119
 120 reset:
 121         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 122         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 123         orr     r0,r0,#0x13
 124         msr     cpsr,r0
 125
 126         bl      cpu_init_crit           /* we do sys-critical inits         */
 127
 128 relocate:                               /* relocate U-Boot to RAM          */
 129         adr     r0, _start              /* r0 <- current position of code */
 130         ldr     r2, _armboot_start
 131         ldr     r3, _armboot_end
 132         sub     r2, r3, r2              /* r2 <- size of armboot */
 133         ldr     r1, _TEXT_BASE
 134         add     r2, r0, r2              /* r2 <- source end address */
 135
 136 copy_loop:
 137         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 138         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 139         cmp     r0, r2                  /* until source end addreee [r2]    */
 140         ble     copy_loop
 141
 142         /* Set up the stack                                                 */
 143         ldr     r0, _uboot_reloc        /* upper 128 KiB: relocated uboot   */
 144         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 145                                         /* FIXME: bdinfo should be here     */
 146         sub     sp, r0, #12             /* leave 3 words for abort-stack */
 147
 148         ldr     pc, _start_armboot
 149
 150 _start_armboot: .word start_armboot
 151
 152
 153 /****************************************************************************/
 154 /*                                                                          */
 155 /* CPU_init_critical registers                                              */
 156 /*                                                                          */
 157 /* - setup important registers                                              */
 158 /* - setup memory timing                                                    */
 159 /*                                                                          */
 160 /****************************************************************************/
 161
 162         /* Interrupt-Controller base address                                */
 163 IC_BASE:           .word           0x40d00000
 164 #define ICMR    0x04
 165
 166 /* Reset-Controller */
 167 RST_BASE:       .word   0x40f00030
 168 #define RCSR    0x00
 169
 170         /* Operating System Timer */
 171 OSTIMER_BASE:   .word   0x40a00000
 172 #define OSMR3   0x0C
 173 #define OSCR    0x10
 174 #define OWER    0x18
 175 #define OIER    0x1C
 176
 177         /* Clock Manager Registers                                          */
 178 #ifdef CFG_CPUSPEED
 179 CC_BASE:        .word   0x41300000
 180 #define CCCR    0x00
 181 cpuspeed:       .word   CFG_CPUSPEED
 182 #endif
 183         /* RS: ???                                                          */
 184         .macro CPWAIT
 185         mrc  p15,0,r0,c2,c0,0
 186         mov  r0,r0
 187         sub  pc,pc,#4
 188         .endm
 189
 190
 191 cpu_init_crit:
 192
 193         /* mask all IRQs                                                    */
 194         ldr     r0, IC_BASE
 195         mov     r1, #0x00
 196         str     r1, [r0, #ICMR]
 197
 198 #ifdef CFG_CPUSPEED
 199         /* set clock speed */
 200         ldr     r0, CC_BASE
 201         ldr     r1, cpuspeed
 202         str     r1, [r0, #CCCR]
 203         mov     r0, #3
 204         mcr     p14, 0, r0, c6, c0, 0
 205 #endif
 206
 207         /*
 208          * before relocating, we have to setup RAM timing
 209          * because memory timing is board-dependend, you will
 210          * find a memsetup.S in your board directory.
 211          */
 212         mov     ip,     lr
 213         bl      memsetup
 214         mov     lr,     ip
 215
 216         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 217
 218         ldr     r0, =0x2001             /* enable access to all coproc.     */
 219         mcr     p15, 0, r0, c15, c1, 0
 220         CPWAIT
 221
 222         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 223         CPWAIT
 224
 225         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 226         CPWAIT
 227
 228         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 229         CPWAIT
 230
 231         /* Enable the Icache                                                */
 232 /*
 233         mrc     p15, 0, r0, c1, c0, 0
 234         orr     r0, r0, #0x1800
 235         mcr     p15, 0, r0, c1, c0, 0
 236         CPWAIT
 237 */
 238         mov     pc, lr
 239
 240
 241 /****************************************************************************/
 242 /*                                                                          */
 243 /* Interrupt handling                                                       */
 244 /*                                                                          */
 245 /****************************************************************************/
 246
 247 /* IRQ stack frame                                                          */
 248
 249 #define S_FRAME_SIZE    72
 250
 251 #define S_OLD_R0        68
 252 #define S_PSR           64
 253 #define S_PC            60
 254 #define S_LR            56
 255 #define S_SP            52
 256
 257 #define S_IP            48
 258 #define S_FP            44
 259 #define S_R10           40
 260 #define S_R9            36
 261 #define S_R8            32
 262 #define S_R7            28
 263 #define S_R6            24
 264 #define S_R5            20
 265 #define S_R4            16
 266 #define S_R3            12
 267 #define S_R2            8
 268 #define S_R1            4
 269 #define S_R0            0
 270
 271 #define MODE_SVC 0x13
 272
 273         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 274
 275         .macro  bad_save_user_regs
 276         sub     sp, sp, #S_FRAME_SIZE
 277         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 278         add     r8, sp, #S_PC
 279
 280         ldr     r2, _armboot_end
 281         add     r2, r2, #CONFIG_STACKSIZE
 282         sub     r2, r2, #8
 283         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 284         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 285
 286         add     r5, sp, #S_SP
 287         mov     r1, lr
 288         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 289         mov     r0, sp
 290         .endm
 291
 292
 293         /* use irq_save_user_regs / irq_restore_user_regs for                */
 294         /* IRQ/FIQ handling                                                  */
 295
 296         .macro  irq_save_user_regs
 297         sub     sp, sp, #S_FRAME_SIZE
 298         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 299         add     r8, sp, #S_PC
 300         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 301         str     lr, [r8, #0]                    /* Save calling PC           */
 302         mrs     r6, spsr
 303         str     r6, [r8, #4]                    /* Save CPSR                 */
 304         str     r0, [r8, #8]                    /* Save OLD_R0               */
 305         mov     r0, sp
 306         .endm
 307
 308         .macro  irq_restore_user_regs
 309         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 310         mov     r0, r0
 311         ldr     lr, [sp, #S_PC]                 @ Get PC
 312         add     sp, sp, #S_FRAME_SIZE
 313         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 314         .endm
 315
 316         .macro get_bad_stack
 317         ldr     r13, _armboot_end               @ setup our mode stack
 318         add     r13, r13, #CONFIG_STACKSIZE     @ resides at top of normal stack
 319         sub     r13, r13, #8
 320
 321         str     lr, [r13]                       @ save caller lr / spsr
 322         mrs     lr, spsr
 323         str     lr, [r13, #4]
 324
 325         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 326         msr     spsr_c, r13
 327         mov     lr, pc
 328         movs    pc, lr
 329         .endm
 330
 331         .macro get_irq_stack                    @ setup IRQ stack
 332         ldr     sp, IRQ_STACK_START
 333         .endm
 334
 335         .macro get_fiq_stack                    @ setup FIQ stack
 336         ldr     sp, FIQ_STACK_START
 337         .endm
 338
 339
 340 /****************************************************************************/
 341 /*                                                                          */
 342 /* exception handlers                                                       */
 343 /*                                                                          */
 344 /****************************************************************************/
 345
 346         .align  5
 347 undefined_instruction:
 348         get_bad_stack
 349         bad_save_user_regs
 350         bl      do_undefined_instruction
 351
 352         .align  5
 353 software_interrupt:
 354         get_bad_stack
 355         bad_save_user_regs
 356         bl      do_software_interrupt
 357
 358         .align  5
 359 prefetch_abort:
 360         get_bad_stack
 361         bad_save_user_regs
 362         bl      do_prefetch_abort
 363
 364         .align  5
 365 data_abort:
 366         get_bad_stack
 367         bad_save_user_regs
 368         bl      do_data_abort
 369
 370         .align  5
 371 not_used:
 372         get_bad_stack
 373         bad_save_user_regs
 374         bl      do_not_used
 375
 376 #ifdef CONFIG_USE_IRQ
 377
 378         .align  5
 379 irq:
 380         get_irq_stack
 381         irq_save_user_regs
 382         bl      do_irq
 383         irq_restore_user_regs
 384
 385         .align  5
 386 fiq:
 387         get_fiq_stack
 388         irq_save_user_regs              /* someone ought to write a more    */
 389         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 390         irq_restore_user_regs
 391
 392 #else
 393
 394         .align  5
 395 irq:
 396         get_bad_stack
 397         bad_save_user_regs
 398         bl      do_irq
 399
 400         .align  5
 401 fiq:
 402         get_bad_stack
 403         bad_save_user_regs
 404         bl      do_fiq
 405
 406 #endif
 407
 408 /************************************************************************/
 409 /*                                                                      */
 410 /* Reset function: the PXA250 has no reset function, so we have to      */
 411 /* perform a watchdog timeout to cause a reset.                         */
 412 /*                                                                      */
 413 /************************************************************************/
 414         .align  5
 415 .globl reset_cpu
 416 reset_cpu:
 417         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 418
 419         ldr     r0, OSTIMER_BASE
 420         ldr     r1, [r0, #OWER]
 421         orr     r1, r1, #0x0001                 /* bit0: WME                */
 422         str     r1, [r0, #OWER]
 423
 424         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 425         /* the match register as well.                                      */
 426
 427         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 428         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 429         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 430         str     r1, [r0, #OSMR3]
 431
 432 reset_endless:
 433
 434         b       reset_endless