drivers/block/mxc_ata.h

   1 #ifndef _MXC_ATA_H_
   2 #define _MXC_ATA_H_
   3
   4 /*
   5  * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #define MXC_ATA_TIMING_REGS                             0x00
  27 #define MXC_ATA_FIFO_FILL                                   0x20
  28 #define MXC_ATA_CONTROL                                     0x24
  29 #define MXC_ATA_INT_PEND                                   0x28
  30 #define MXC_ATA_INT_EN                                       0x2C
  31 #define MXC_ATA_INT_CLEAR                                 0x30
  32 #define MXC_ATA_FIFO_ALARM                              0x34
  33 #define MXC_ATA_ADMA_ERROR_STATUS               0x38
  34 #define MXC_ATA_SYS_DMA_BADDR                       0x3C
  35 #define MXC_ATA_ADMA_SYS_ADDR                       0x40
  36 #define MXC_ATA_BLOCK_COUNT                            0x48
  37 #define MXC_ATA_BURST_LENGTH                          0x4C
  38 #define MXC_ATA_SECTOR_SIZE                             0x50
  39 #define MXC_ATA_DRIVE_DATA                              0xA0
  40 #define MXC_ATA_DFTR                                          0xA4
  41 #define MXC_ATA_DSCR                                          0xA8
  42 #define MXC_ATA_DSNR                                          0xAC
  43 #define MXC_ATA_DCLR                                           0xB0
  44 #define MXC_ATA_DCHR                                          0xB4
  45 #define MXC_ATA_DDHR                                          0xB8
  46 #define MXC_ATA_DCDR                                          0xBC
  47 #define MXC_ATA_DRIVE_CONTROL                         0xD8
  48
  49 /* bits within MXC_ATA_CONTROL */
  50 #define MXC_ATA_CTRL_DMA_SRST                         0x1000
  51 #define MXC_ATA_CTRL_DMA_64ADMA                    0x800
  52 #define MXC_ATA_CTRL_DMA_32ADMA                    0x400
  53 #define MXC_ATA_CTRL_DMA_STAT_STOP               0x200
  54 #define MXC_ATA_CTRL_DMA_ENABLE                     0x100
  55 #define MXC_ATA_CTRL_FIFO_RST_B                       0x80
  56 #define MXC_ATA_CTRL_ATA_RST_B                        0x40
  57 #define MXC_ATA_CTRL_FIFO_TX_EN                      0x20
  58 #define MXC_ATA_CTRL_FIFO_RCV_EN                    0x10
  59 #define MXC_ATA_CTRL_DMA_PENDING                   0x08
  60 #define MXC_ATA_CTRL_DMA_ULTRA                       0x04
  61 #define MXC_ATA_CTRL_DMA_WRITE                       0x02
  62 #define MXC_ATA_CTRL_IORDY_EN                          0x01
  63
  64 /* bits within the interrupt control registers */
  65 #define MXC_ATA_INTR_ATA_INTRQ1                      0x80
  66 #define MXC_ATA_INTR_FIFO_UNDERFLOW             0x40
  67 #define MXC_ATA_INTR_FIFO_OVERFLOW               0x20
  68 #define MXC_ATA_INTR_CTRL_IDLE                         0x10
  69 #define MXC_ATA_INTR_ATA_INTRQ2                      0x08
  70 #define MXC_ATA_INTR_DMA_ERR                           0x04
  71 #define MXC_ATA_INTR_DMA_TRANS_OVER            0x02
  72
  73 /* ADMA Addr Descriptor Attribute Filed */
  74 #define MXC_ADMA_DES_ATTR_VALID                     0x01
  75 #define MXC_ADMA_DES_ATTR_END                        0x02
  76 #define MXC_ADMA_DES_ATTR_INT                         0x04
  77 #define MXC_ADMA_DES_ATTR_SET                         0x10
  78 #define MXC_ADMA_DES_ATTR_TRAN                      0x20
  79 #define MXC_ADMA_DES_ATTR_LINK                       0x30
  80
  81 #define PIO_XFER_MODE_0                                     0
  82 #define PIO_XFER_MODE_1                                     1
  83 #define PIO_XFER_MODE_2                                     2
  84 #define PIO_XFER_MODE_3                                     3
  85 #define PIO_XFER_MODE_4                                     4
  86
  87 #define ATA_SECTOR_SIZE                                     512
  88 #define MAX_SECTORS                       256
  89
  90 #endif /* _IMX_ATA_H_ */