drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <div64.h>
   8 #include <watchdog.h>
   9 #include <asm/arch/fpga_manager.h>
  10 #include <asm/arch/sdram.h>
  11 #include <asm/arch/system_manager.h>
  12 #include <asm/io.h>
  13
  14 /*
  15  * FIXME: This path is temporary until the SDRAM driver gets
  16  *        a proper thorough cleanup.
  17  */
  18 #include "../../../board/altera/socfpga/qts/sdram_config.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct sdram_prot_rule {
  23         u64     sdram_start;    /* SDRAM start address */
  24         u64     sdram_end;      /* SDRAM end address */
  25         u32     rule;           /* SDRAM protection rule number: 0-19 */
  26         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  27
  28         u32     security;
  29         u32     portmask;
  30         u32     result;
  31         u32     lo_prot_id;
  32         u32     hi_prot_id;
  33 };
  34
  35 static struct socfpga_system_manager *sysmgr_regs =
  36         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  37 static struct socfpga_sdr_ctrl *sdr_ctrl =
  38         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  39
  40 static struct socfpga_sdram_config {
  41         u32     ctrl_cfg;
  42         u32     dram_timing1;
  43         u32     dram_timing2;
  44         u32     dram_timing3;
  45         u32     dram_timing4;
  46         u32     lowpwr_timing;
  47         u32     dram_addrw;
  48         u32     static_cfg;
  49         u32     fifo_cfg;
  50         u32     mp_weight0;
  51         u32     mp_weight1;
  52         u32     mp_weight2;
  53         u32     mp_weight3;
  54         u32     mp_pacing0;
  55         u32     mp_pacing1;
  56         u32     mp_pacing2;
  57         u32     mp_pacing3;
  58         u32     mp_threshold0;
  59         u32     mp_threshold1;
  60         u32     mp_threshold2;
  61 } sdram_config = {
  62         .ctrl_cfg =
  63                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
  64                         SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)                |
  65                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
  66                         SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)                  |
  67                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
  68                         SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)                  |
  69                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
  70                         SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)              |
  71                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
  72                         SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)              |
  73                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
  74                         SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)            |
  75                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
  76                         SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)               |
  77                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
  78                         SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
  79         .dram_timing1 =
  80                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
  81                         SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)               |
  82                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
  83                         SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)                |
  84                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
  85                         SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)                |
  86                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
  87                         SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)               |
  88                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
  89                         SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)               |
  90                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
  91                         SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
  92         .dram_timing2 =
  93                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
  94                         SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)              |
  95                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
  96                         SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)               |
  97                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
  98                         SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)                |
  99                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
 100                         SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)                |
 101                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
 102                         SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
 103         .dram_timing3 =
 104                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
 105                         SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)               |
 106                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
 107                         SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)               |
 108                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
 109                         SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)                |
 110                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
 111                         SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)               |
 112                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
 113                         SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
 114         .dram_timing4 =
 115                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
 116                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)       |
 117                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
 118                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
 119         .lowpwr_timing =
 120                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
 121                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)      |
 122                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
 123                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
 124         .dram_addrw =
 125                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
 126                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)              |
 127                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
 128                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)             |
 129                 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
 130                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
 131         .static_cfg =
 132                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 133                         SDR_CTRLGRP_STATICCFG_MEMBL_LSB)                |
 134                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 135                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
 136         .fifo_cfg =
 137                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 138                         SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)               |
 139                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 140                         SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
 141         .mp_weight0 =
 142                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 143                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
 144         .mp_weight1 =
 145                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 146                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
 147                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 148                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
 149         .mp_weight2 =
 150                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 151                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
 152         .mp_weight3 =
 153                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 154                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
 155         .mp_pacing0 =
 156                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 157                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
 158         .mp_pacing1 =
 159                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 160                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
 161                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 162                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
 163         .mp_pacing2 =
 164                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 165                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
 166         .mp_pacing3 =
 167                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 168                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
 169         .mp_threshold0 =
 170                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 171                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
 172         .mp_threshold1 =
 173                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 174                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
 175         .mp_threshold2 =
 176                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 177                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
 178 };
 179
 180 /**
 181  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
 182  *
 183  * SDRAM Failure happens when accessing non-existent memory. Artificially
 184  * increase the number of rows so that the memory controller thinks it has
 185  * 4GB of RAM. This function returns such amount of rows.
 186  */
 187 static int get_errata_rows(void)
 188 {
 189         /* Define constant for 4G memory - used for SDRAM errata workaround */
 190 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
 191         const unsigned long long memsize = MEMSIZE_4G;
 192         const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 193         const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 194         const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
 195         const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
 196         const unsigned int width = 8;
 197
 198         unsigned long long newrows;
 199         int bits, inewrowslog2;
 200
 201         debug("workaround rows - memsize %lld\n", memsize);
 202         debug("workaround rows - cs        %d\n", cs);
 203         debug("workaround rows - width     %d\n", width);
 204         debug("workaround rows - rows      %d\n", rows);
 205         debug("workaround rows - banks     %d\n", banks);
 206         debug("workaround rows - cols      %d\n", cols);
 207
 208         newrows = lldiv(memsize, cs * (width / 8));
 209         debug("rows workaround - term1 %lld\n", newrows);
 210
 211         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
 212         debug("rows workaround - term2 %lld\n", newrows);
 213
 214         /*
 215          * Compute the hamming weight - same as number of bits set.
 216          * Need to see if result is ordinal power of 2 before
 217          * attempting log2 of result.
 218          */
 219         bits = generic_hweight32(newrows);
 220
 221         debug("rows workaround - bits %d\n", bits);
 222
 223         if (bits != 1) {
 224                 printf("SDRAM workaround failed, bits set %d\n", bits);
 225                 return rows;
 226         }
 227
 228         if (newrows > UINT_MAX) {
 229                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
 230                 return rows;
 231         }
 232
 233         inewrowslog2 = __ilog2(newrows);
 234
 235         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 236
 237         if (inewrowslog2 == -1) {
 238                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 239                 return rows;
 240         }
 241
 242         return inewrowslog2;
 243 }
 244
 245 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 246 static void sdram_set_rule(struct sdram_prot_rule *prule)
 247 {
 248         uint32_t lo_addr_bits;
 249         uint32_t hi_addr_bits;
 250         int ruleno = prule->rule;
 251
 252         /* Select the rule */
 253         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 254
 255         /* Obtain the address bits */
 256         lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
 257         hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
 258
 259         debug("sdram set rule start %x, %lld\n", lo_addr_bits,
 260               prule->sdram_start);
 261         debug("sdram set rule end   %x, %lld\n", hi_addr_bits,
 262               prule->sdram_end);
 263
 264         /* Set rule addresses */
 265         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 266
 267         /* Set rule protection ids */
 268         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 269                &sdr_ctrl->prot_rule_id);
 270
 271         /* Set the rule data */
 272         writel(prule->security | (prule->valid << 2) |
 273                (prule->portmask << 3) | (prule->result << 13),
 274                &sdr_ctrl->prot_rule_data);
 275
 276         /* write the rule */
 277         writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
 278
 279         /* Set rule number to 0 by default */
 280         writel(0, &sdr_ctrl->prot_rule_rdwr);
 281 }
 282
 283 static void sdram_get_rule(struct sdram_prot_rule *prule)
 284 {
 285         uint32_t addr;
 286         uint32_t id;
 287         uint32_t data;
 288         int ruleno = prule->rule;
 289
 290         /* Read the rule */
 291         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 292         writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
 293
 294         /* Get the addresses */
 295         addr = readl(&sdr_ctrl->prot_rule_addr);
 296         prule->sdram_start = (addr & 0xFFF) << 20;
 297         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 298
 299         /* Get the configured protection IDs */
 300         id = readl(&sdr_ctrl->prot_rule_id);
 301         prule->lo_prot_id = id & 0xFFF;
 302         prule->hi_prot_id = (id >> 12) & 0xFFF;
 303
 304         /* Get protection data */
 305         data = readl(&sdr_ctrl->prot_rule_data);
 306
 307         prule->security = data & 0x3;
 308         prule->valid = (data >> 2) & 0x1;
 309         prule->portmask = (data >> 3) & 0x3FF;
 310         prule->result = (data >> 13) & 0x1;
 311 }
 312
 313 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
 314 {
 315         struct sdram_prot_rule rule;
 316         int rules;
 317
 318         /* Start with accepting all SDRAM transaction */
 319         writel(0x0, &sdr_ctrl->protport_default);
 320
 321         /* Clear all protection rules for warm boot case */
 322         memset(&rule, 0, sizeof(struct sdram_prot_rule));
 323
 324         for (rules = 0; rules < 20; rules++) {
 325                 rule.rule = rules;
 326                 sdram_set_rule(&rule);
 327         }
 328
 329         /* new rule: accept SDRAM */
 330         rule.sdram_start = sdram_start;
 331         rule.sdram_end = sdram_end;
 332         rule.lo_prot_id = 0x0;
 333         rule.hi_prot_id = 0xFFF;
 334         rule.portmask = 0x3FF;
 335         rule.security = 0x3;
 336         rule.result = 0;
 337         rule.valid = 1;
 338         rule.rule = 0;
 339
 340         /* set new rule */
 341         sdram_set_rule(&rule);
 342
 343         /* default rule: reject everything */
 344         writel(0x3ff, &sdr_ctrl->protport_default);
 345 }
 346
 347 static void sdram_dump_protection_config(void)
 348 {
 349         struct sdram_prot_rule rule;
 350         int rules;
 351
 352         debug("SDRAM Prot rule, default %x\n",
 353               readl(&sdr_ctrl->protport_default));
 354
 355         for (rules = 0; rules < 20; rules++) {
 356                 sdram_get_rule(&rule);
 357                 debug("Rule %d, rules ...\n", rules);
 358                 debug("    sdram start %llx\n", rule.sdram_start);
 359                 debug("    sdram end   %llx\n", rule.sdram_end);
 360                 debug("    low prot id %d, hi prot id %d\n",
 361                       rule.lo_prot_id,
 362                       rule.hi_prot_id);
 363                 debug("    portmask %x\n", rule.portmask);
 364                 debug("    security %d\n", rule.security);
 365                 debug("    result %d\n", rule.result);
 366                 debug("    valid %d\n", rule.valid);
 367         }
 368 }
 369
 370 /* Function to write to register and verify the write */
 371 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
 372 {
 373 #ifndef SDRAM_MMR_SKIP_VERIFY
 374         unsigned reg_value1;
 375 #endif
 376         debug("   Write - Address ");
 377         debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
 378         /* Write to register */
 379         writel(reg_value, addr);
 380 #ifndef SDRAM_MMR_SKIP_VERIFY
 381         debug("   Read and verify...");
 382         /* Read back the wrote value */
 383         reg_value1 = readl(addr);
 384         /* Indicate failure if value not matched */
 385         if (reg_value1 != reg_value) {
 386                 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
 387                       (u32)addr, reg_value, reg_value1);
 388                 return 1;
 389         }
 390         debug("correct!\n");
 391 #endif  /* SDRAM_MMR_SKIP_VERIFY */
 392         return 0;
 393 }
 394
 395 static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
 396 {
 397         u32 addrorder;
 398         u32 ctrl_cfg = cfg->ctrl_cfg;
 399
 400         debug("\nConfiguring CTRLCFG\n");
 401
 402         /*
 403          * SDRAM Failure When Accessing Non-Existent Memory
 404          * Set the addrorder field of the SDRAM control register
 405          * based on the CSBITs setting.
 406          */
 407         switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
 408         case 1:
 409                 addrorder = 0; /* chip, row, bank, column */
 410                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
 411                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 412                 break;
 413         case 2:
 414                 addrorder = 2; /* row, chip, bank, column */
 415                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
 416                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 417                 break;
 418         default:
 419                 addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
 420                 break;
 421         }
 422
 423         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 424
 425         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 426 }
 427
 428 static void set_sdr_dram_timing(struct socfpga_sdram_config *cfg)
 429 {
 430         debug("Configuring DRAMTIMING1\n");
 431         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 432
 433         debug("Configuring DRAMTIMING2\n");
 434         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 435
 436         debug("Configuring DRAMTIMING3\n");
 437         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 438
 439         debug("Configuring DRAMTIMING4\n");
 440         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 441
 442         debug("Configuring LOWPWRTIMING\n");
 443         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 444 }
 445
 446 static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg)
 447 {
 448         /*
 449          * SDRAM Failure When Accessing Non-Existent Memory
 450          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 451          * log2(number of chip select bits). Since there's only
 452          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 453          * which is the same as "chip selects" - 1.
 454          */
 455         const int rows = get_errata_rows();
 456
 457         debug("Configuring DRAMADDRW\n");
 458         writel(cfg->dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB),
 459                &sdr_ctrl->dram_addrw);
 460 }
 461
 462 static void set_sdr_static_cfg(struct socfpga_sdram_config *cfg)
 463 {
 464         debug("Configuring STATICCFG\n");
 465         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 466 }
 467
 468 static void set_sdr_fifo_cfg(struct socfpga_sdram_config *cfg)
 469 {
 470         debug("Configuring FIFOCFG\n");
 471         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 472 }
 473
 474 static void set_sdr_mp_weight(struct socfpga_sdram_config *cfg)
 475 {
 476         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 477         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 478         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 479         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 480         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 481 }
 482
 483 static void set_sdr_mp_pacing(struct socfpga_sdram_config *cfg)
 484 {
 485         debug("Configuring MPPACING_MPPACING_0\n");
 486         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 487         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 488         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 489         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 490 }
 491
 492 static void set_sdr_mp_threshold(struct socfpga_sdram_config *cfg)
 493 {
 494         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 495         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 496         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 497         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 498 }
 499
 500 /* Function to initialize SDRAM MMR */
 501 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
 502 {
 503         unsigned long status = 0;
 504         struct socfpga_sdram_config *cfg = &sdram_config;
 505
 506 #if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
 507 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
 508 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
 509 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
 510 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
 511
 512         writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
 513                &sysmgr_regs->iswgrp_handoff[4]);
 514 #endif
 515         set_sdr_ctrlcfg(cfg);
 516         set_sdr_dram_timing(cfg);
 517         set_sdr_addr_rw(cfg);
 518
 519         debug("Configuring DRAMIFWIDTH\n");
 520         clrsetbits_le32(&sdr_ctrl->dram_if_width,
 521                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK,
 522                         CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
 523                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB);
 524
 525         debug("Configuring DRAMDEVWIDTH\n");
 526         clrsetbits_le32(&sdr_ctrl->dram_dev_width,
 527                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK,
 528                         CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
 529                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB);
 530
 531         debug("Configuring LOWPWREQ\n");
 532         clrsetbits_le32(&sdr_ctrl->lowpwr_eq,
 533                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK,
 534                         CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 535                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB);
 536
 537         debug("Configuring DRAMINTR\n");
 538         clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK,
 539                         CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 540                         SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
 541
 542         set_sdr_static_cfg(cfg);
 543
 544         debug("Configuring CTRLWIDTH\n");
 545         clrsetbits_le32(&sdr_ctrl->ctrl_width,
 546                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK,
 547                         CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 548                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB);
 549
 550         debug("Configuring PORTCFG\n");
 551         clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK,
 552                         CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 553                         SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
 554
 555         set_sdr_fifo_cfg(cfg);
 556
 557         debug("Configuring MPPRIORITY\n");
 558         clrsetbits_le32(&sdr_ctrl->mp_priority,
 559                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK,
 560                         CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 561                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
 562
 563         set_sdr_mp_weight(cfg);
 564         set_sdr_mp_pacing(cfg);
 565         set_sdr_mp_threshold(cfg);
 566
 567         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 568         setbits_le32(&sdr_ctrl->phy_ctrl0,
 569                      CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0);
 570
 571         debug("Configuring CPORTWIDTH\n");
 572         clrsetbits_le32(&sdr_ctrl->cport_width,
 573                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK,
 574                         CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 575                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB);
 576
 577         debug("Configuring CPORTWMAP\n");
 578         clrsetbits_le32(&sdr_ctrl->cport_wmap,
 579                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK,
 580                         CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 581                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB);
 582
 583         debug("Configuring CPORTRMAP\n");
 584         clrsetbits_le32(&sdr_ctrl->cport_rmap,
 585                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK,
 586                         CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 587                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB);
 588
 589         debug("Configuring RFIFOCMAP\n");
 590         clrsetbits_le32(&sdr_ctrl->rfifo_cmap,
 591                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK,
 592                         CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 593                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB);
 594
 595         debug("Configuring WFIFOCMAP\n");
 596         clrsetbits_le32(&sdr_ctrl->wfifo_cmap,
 597                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK,
 598                         CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 599                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB);
 600
 601         debug("Configuring CPORTRDWR\n");
 602         clrsetbits_le32(&sdr_ctrl->cport_rdwr,
 603                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK,
 604                         CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 605                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB);
 606
 607         debug("Configuring DRAMODT\n");
 608         clrsetbits_le32(&sdr_ctrl->dram_odt,
 609                         SDR_CTRLGRP_DRAMODT_READ_MASK,
 610                         CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
 611                         SDR_CTRLGRP_DRAMODT_READ_LSB);
 612
 613         clrsetbits_le32(&sdr_ctrl->dram_odt,
 614                         SDR_CTRLGRP_DRAMODT_WRITE_MASK,
 615                         CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
 616                         SDR_CTRLGRP_DRAMODT_WRITE_LSB);
 617
 618         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 619         writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 620                &sysmgr_regs->iswgrp_handoff[3]);
 621
 622         /* only enable if the FPGA is programmed */
 623         if (fpgamgr_test_fpga_ready()) {
 624                 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 625                     CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) {
 626                         status = 1;
 627                         return 1;
 628                 }
 629         }
 630
 631         /* Restore the SDR PHY Register if valid */
 632         if (sdr_phy_reg != 0xffffffff)
 633                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 634
 635 /***** Final step - apply configuration changes *****/
 636         debug("Configuring STATICCFG_\n");
 637         clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 638                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 639
 640         sdram_set_protection_config(0, sdram_calculate_size());
 641
 642         sdram_dump_protection_config();
 643
 644         return status;
 645 }
 646
 647 /*
 648  * To calculate SDRAM device size based on SDRAM controller parameters.
 649  * Size is specified in bytes.
 650  *
 651  * NOTE:
 652  * This function is compiled and linked into the preloader and
 653  * Uboot (there may be others). So if this function changes, the Preloader
 654  * and UBoot must be updated simultaneously.
 655  */
 656 unsigned long sdram_calculate_size(void)
 657 {
 658         unsigned long temp;
 659         unsigned long row, bank, col, cs, width;
 660
 661         temp = readl(&sdr_ctrl->dram_addrw);
 662         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 663                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 664
 665         /* SDRAM Failure When Accessing Non-Existent Memory
 666          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 667          * since the FB specifies we modify ROWBITs to work around SDRAM
 668          * controller issue.
 669          *
 670          * If the stored handoff value for rows is 0, it probably means
 671          * the preloader is older than UBoot. Use the
 672          * #define from the SOCEDS Tools per Crucible review
 673          * uboot-socfpga-204. Note that this is not a supported
 674          * configuration and is not tested. The customer
 675          * should be using preloader and uboot built from the
 676          * same tag.
 677          */
 678         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 679         if (row == 0)
 680                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 681         /* If the stored handoff value for rows is greater than
 682          * the field width in the sdr.dramaddrw register then
 683          * something is very wrong. Revert to using the the #define
 684          * value handed off by the SOCEDS tool chain instead of
 685          * using a broken value.
 686          */
 687         if (row > 31)
 688                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 689
 690         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 691                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 692
 693         /* SDRAM Failure When Accessing Non-Existent Memory
 694          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 695          * since the FB specifies we modify CSBITs to work around SDRAM
 696          * controller issue.
 697          */
 698         cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 699               SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
 700         cs += 1;
 701
 702         cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 703
 704         width = readl(&sdr_ctrl->dram_if_width);
 705         /* ECC would not be calculated as its not addressible */
 706         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 707                 width = 32;
 708         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 709                 width = 16;
 710
 711         /* calculate the SDRAM size base on this info */
 712         temp = 1 << (row + bank + col);
 713         temp = temp * cs * (width  / 8);
 714
 715         debug("sdram_calculate_memory returns %ld\n", temp);
 716
 717         return temp;
 718 }