drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <div64.h>
   8 #include <watchdog.h>
   9 #include <asm/arch/fpga_manager.h>
  10 #include <asm/arch/sdram.h>
  11 #include <asm/arch/system_manager.h>
  12 #include <asm/io.h>
  13
  14 /*
  15  * FIXME: This path is temporary until the SDRAM driver gets
  16  *        a proper thorough cleanup.
  17  */
  18 #include "../../../board/altera/socfpga/qts/sdram_config.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct sdram_prot_rule {
  23         u64     sdram_start;    /* SDRAM start address */
  24         u64     sdram_end;      /* SDRAM end address */
  25         u32     rule;           /* SDRAM protection rule number: 0-19 */
  26         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  27
  28         u32     security;
  29         u32     portmask;
  30         u32     result;
  31         u32     lo_prot_id;
  32         u32     hi_prot_id;
  33 };
  34
  35 static struct socfpga_system_manager *sysmgr_regs =
  36         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  37 static struct socfpga_sdr_ctrl *sdr_ctrl =
  38         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  39
  40 static struct socfpga_sdram_config {
  41         u32     ctrl_cfg;
  42         u32     dram_timing1;
  43         u32     dram_timing2;
  44         u32     dram_timing3;
  45         u32     dram_timing4;
  46         u32     lowpwr_timing;
  47         u32     dram_odt;
  48         u32     dram_addrw;
  49         u32     dram_if_width;
  50         u32     dram_dev_width;
  51         u32     dram_intr;
  52         u32     lowpwr_eq;
  53         u32     static_cfg;
  54         u32     ctrl_width;
  55         u32     cport_width;
  56         u32     cport_wmap;
  57         u32     cport_rmap;
  58         u32     rfifo_cmap;
  59         u32     wfifo_cmap;
  60         u32     cport_rdwr;
  61         u32     port_cfg;
  62         u32     fpgaport_rst;
  63         u32     fifo_cfg;
  64         u32     mp_priority;
  65         u32     mp_weight0;
  66         u32     mp_weight1;
  67         u32     mp_weight2;
  68         u32     mp_weight3;
  69         u32     mp_pacing0;
  70         u32     mp_pacing1;
  71         u32     mp_pacing2;
  72         u32     mp_pacing3;
  73         u32     mp_threshold0;
  74         u32     mp_threshold1;
  75         u32     mp_threshold2;
  76         u32     phy_ctrl0;
  77 } sdram_config = {
  78         .ctrl_cfg =
  79                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
  80                         SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)                |
  81                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
  82                         SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)                  |
  83                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
  84                         SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)                  |
  85                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
  86                         SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)              |
  87                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
  88                         SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)              |
  89                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
  90                         SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)            |
  91                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
  92                         SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)               |
  93                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
  94                         SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
  95         .dram_timing1 =
  96                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
  97                         SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)               |
  98                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
  99                         SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)                |
 100                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
 101                         SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)                |
 102                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
 103                         SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)               |
 104                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
 105                         SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)               |
 106                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
 107                         SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
 108         .dram_timing2 =
 109                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
 110                         SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)              |
 111                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
 112                         SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)               |
 113                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
 114                         SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)                |
 115                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
 116                         SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)                |
 117                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
 118                         SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
 119         .dram_timing3 =
 120                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
 121                         SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)               |
 122                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
 123                         SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)               |
 124                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
 125                         SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)                |
 126                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
 127                         SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)               |
 128                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
 129                         SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
 130         .dram_timing4 =
 131                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
 132                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)       |
 133                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
 134                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
 135         .lowpwr_timing =
 136                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
 137                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)      |
 138                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
 139                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
 140         .dram_odt =
 141                 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
 142                         SDR_CTRLGRP_DRAMODT_READ_LSB)                   |
 143                 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
 144                         SDR_CTRLGRP_DRAMODT_WRITE_LSB),
 145         .dram_addrw =
 146                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
 147                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)              |
 148                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
 149                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)             |
 150                 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
 151                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
 152         .dram_if_width =
 153                 (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
 154                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
 155         .dram_dev_width =
 156                 (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
 157                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
 158         .dram_intr =
 159                 (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 160                         SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
 161         .lowpwr_eq =
 162                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 163                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
 164         .static_cfg =
 165                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 166                         SDR_CTRLGRP_STATICCFG_MEMBL_LSB)                |
 167                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 168                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
 169         .ctrl_width =
 170                 (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 171                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
 172         .cport_width =
 173                 (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 174                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
 175         .cport_wmap =
 176                 (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 177                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
 178         .cport_rmap =
 179                 (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 180                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
 181         .rfifo_cmap =
 182                 (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 183                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
 184         .wfifo_cmap =
 185                 (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 186                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
 187         .cport_rdwr =
 188                 (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 189                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
 190         .port_cfg =
 191                 (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 192                         SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
 193         .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 194         .fifo_cfg =
 195                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 196                         SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)               |
 197                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 198                         SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
 199         .mp_priority =
 200                 (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 201                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
 202         .mp_weight0 =
 203                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 204                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
 205         .mp_weight1 =
 206                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 207                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
 208                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 209                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
 210         .mp_weight2 =
 211                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 212                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
 213         .mp_weight3 =
 214                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 215                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
 216         .mp_pacing0 =
 217                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 218                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
 219         .mp_pacing1 =
 220                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 221                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
 222                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 223                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
 224         .mp_pacing2 =
 225                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 226                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
 227         .mp_pacing3 =
 228                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 229                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
 230         .mp_threshold0 =
 231                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 232                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
 233         .mp_threshold1 =
 234                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 235                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
 236         .mp_threshold2 =
 237                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 238                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
 239         .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
 240 };
 241
 242 /**
 243  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
 244  *
 245  * SDRAM Failure happens when accessing non-existent memory. Artificially
 246  * increase the number of rows so that the memory controller thinks it has
 247  * 4GB of RAM. This function returns such amount of rows.
 248  */
 249 static int get_errata_rows(void)
 250 {
 251         /* Define constant for 4G memory - used for SDRAM errata workaround */
 252 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
 253         const unsigned long long memsize = MEMSIZE_4G;
 254         const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 255         const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 256         const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
 257         const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
 258         const unsigned int width = 8;
 259
 260         unsigned long long newrows;
 261         int bits, inewrowslog2;
 262
 263         debug("workaround rows - memsize %lld\n", memsize);
 264         debug("workaround rows - cs        %d\n", cs);
 265         debug("workaround rows - width     %d\n", width);
 266         debug("workaround rows - rows      %d\n", rows);
 267         debug("workaround rows - banks     %d\n", banks);
 268         debug("workaround rows - cols      %d\n", cols);
 269
 270         newrows = lldiv(memsize, cs * (width / 8));
 271         debug("rows workaround - term1 %lld\n", newrows);
 272
 273         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
 274         debug("rows workaround - term2 %lld\n", newrows);
 275
 276         /*
 277          * Compute the hamming weight - same as number of bits set.
 278          * Need to see if result is ordinal power of 2 before
 279          * attempting log2 of result.
 280          */
 281         bits = generic_hweight32(newrows);
 282
 283         debug("rows workaround - bits %d\n", bits);
 284
 285         if (bits != 1) {
 286                 printf("SDRAM workaround failed, bits set %d\n", bits);
 287                 return rows;
 288         }
 289
 290         if (newrows > UINT_MAX) {
 291                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
 292                 return rows;
 293         }
 294
 295         inewrowslog2 = __ilog2(newrows);
 296
 297         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 298
 299         if (inewrowslog2 == -1) {
 300                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 301                 return rows;
 302         }
 303
 304         return inewrowslog2;
 305 }
 306
 307 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 308 static void sdram_set_rule(struct sdram_prot_rule *prule)
 309 {
 310         uint32_t lo_addr_bits;
 311         uint32_t hi_addr_bits;
 312         int ruleno = prule->rule;
 313
 314         /* Select the rule */
 315         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 316
 317         /* Obtain the address bits */
 318         lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
 319         hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
 320
 321         debug("sdram set rule start %x, %lld\n", lo_addr_bits,
 322               prule->sdram_start);
 323         debug("sdram set rule end   %x, %lld\n", hi_addr_bits,
 324               prule->sdram_end);
 325
 326         /* Set rule addresses */
 327         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 328
 329         /* Set rule protection ids */
 330         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 331                &sdr_ctrl->prot_rule_id);
 332
 333         /* Set the rule data */
 334         writel(prule->security | (prule->valid << 2) |
 335                (prule->portmask << 3) | (prule->result << 13),
 336                &sdr_ctrl->prot_rule_data);
 337
 338         /* write the rule */
 339         writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
 340
 341         /* Set rule number to 0 by default */
 342         writel(0, &sdr_ctrl->prot_rule_rdwr);
 343 }
 344
 345 static void sdram_get_rule(struct sdram_prot_rule *prule)
 346 {
 347         uint32_t addr;
 348         uint32_t id;
 349         uint32_t data;
 350         int ruleno = prule->rule;
 351
 352         /* Read the rule */
 353         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 354         writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
 355
 356         /* Get the addresses */
 357         addr = readl(&sdr_ctrl->prot_rule_addr);
 358         prule->sdram_start = (addr & 0xFFF) << 20;
 359         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 360
 361         /* Get the configured protection IDs */
 362         id = readl(&sdr_ctrl->prot_rule_id);
 363         prule->lo_prot_id = id & 0xFFF;
 364         prule->hi_prot_id = (id >> 12) & 0xFFF;
 365
 366         /* Get protection data */
 367         data = readl(&sdr_ctrl->prot_rule_data);
 368
 369         prule->security = data & 0x3;
 370         prule->valid = (data >> 2) & 0x1;
 371         prule->portmask = (data >> 3) & 0x3FF;
 372         prule->result = (data >> 13) & 0x1;
 373 }
 374
 375 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
 376 {
 377         struct sdram_prot_rule rule;
 378         int rules;
 379
 380         /* Start with accepting all SDRAM transaction */
 381         writel(0x0, &sdr_ctrl->protport_default);
 382
 383         /* Clear all protection rules for warm boot case */
 384         memset(&rule, 0, sizeof(struct sdram_prot_rule));
 385
 386         for (rules = 0; rules < 20; rules++) {
 387                 rule.rule = rules;
 388                 sdram_set_rule(&rule);
 389         }
 390
 391         /* new rule: accept SDRAM */
 392         rule.sdram_start = sdram_start;
 393         rule.sdram_end = sdram_end;
 394         rule.lo_prot_id = 0x0;
 395         rule.hi_prot_id = 0xFFF;
 396         rule.portmask = 0x3FF;
 397         rule.security = 0x3;
 398         rule.result = 0;
 399         rule.valid = 1;
 400         rule.rule = 0;
 401
 402         /* set new rule */
 403         sdram_set_rule(&rule);
 404
 405         /* default rule: reject everything */
 406         writel(0x3ff, &sdr_ctrl->protport_default);
 407 }
 408
 409 static void sdram_dump_protection_config(void)
 410 {
 411         struct sdram_prot_rule rule;
 412         int rules;
 413
 414         debug("SDRAM Prot rule, default %x\n",
 415               readl(&sdr_ctrl->protport_default));
 416
 417         for (rules = 0; rules < 20; rules++) {
 418                 sdram_get_rule(&rule);
 419                 debug("Rule %d, rules ...\n", rules);
 420                 debug("    sdram start %llx\n", rule.sdram_start);
 421                 debug("    sdram end   %llx\n", rule.sdram_end);
 422                 debug("    low prot id %d, hi prot id %d\n",
 423                       rule.lo_prot_id,
 424                       rule.hi_prot_id);
 425                 debug("    portmask %x\n", rule.portmask);
 426                 debug("    security %d\n", rule.security);
 427                 debug("    result %d\n", rule.result);
 428                 debug("    valid %d\n", rule.valid);
 429         }
 430 }
 431
 432 /* Function to write to register and verify the write */
 433 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
 434 {
 435 #ifndef SDRAM_MMR_SKIP_VERIFY
 436         unsigned reg_value1;
 437 #endif
 438         debug("   Write - Address ");
 439         debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
 440         /* Write to register */
 441         writel(reg_value, addr);
 442 #ifndef SDRAM_MMR_SKIP_VERIFY
 443         debug("   Read and verify...");
 444         /* Read back the wrote value */
 445         reg_value1 = readl(addr);
 446         /* Indicate failure if value not matched */
 447         if (reg_value1 != reg_value) {
 448                 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
 449                       (u32)addr, reg_value, reg_value1);
 450                 return 1;
 451         }
 452         debug("correct!\n");
 453 #endif  /* SDRAM_MMR_SKIP_VERIFY */
 454         return 0;
 455 }
 456
 457 static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
 458 {
 459         u32 addrorder;
 460         u32 ctrl_cfg = cfg->ctrl_cfg;
 461
 462         debug("\nConfiguring CTRLCFG\n");
 463
 464         /*
 465          * SDRAM Failure When Accessing Non-Existent Memory
 466          * Set the addrorder field of the SDRAM control register
 467          * based on the CSBITs setting.
 468          */
 469         switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
 470         case 1:
 471                 addrorder = 0; /* chip, row, bank, column */
 472                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
 473                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 474                 break;
 475         case 2:
 476                 addrorder = 2; /* row, chip, bank, column */
 477                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
 478                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 479                 break;
 480         default:
 481                 addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
 482                 break;
 483         }
 484
 485         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 486
 487         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 488 }
 489
 490 static void set_sdr_dram_timing(struct socfpga_sdram_config *cfg)
 491 {
 492         debug("Configuring DRAMTIMING1\n");
 493         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 494
 495         debug("Configuring DRAMTIMING2\n");
 496         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 497
 498         debug("Configuring DRAMTIMING3\n");
 499         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 500
 501         debug("Configuring DRAMTIMING4\n");
 502         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 503
 504         debug("Configuring LOWPWRTIMING\n");
 505         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 506 }
 507
 508 static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg)
 509 {
 510         /*
 511          * SDRAM Failure When Accessing Non-Existent Memory
 512          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 513          * log2(number of chip select bits). Since there's only
 514          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 515          * which is the same as "chip selects" - 1.
 516          */
 517         const int rows = get_errata_rows();
 518
 519         debug("Configuring DRAMADDRW\n");
 520         writel(cfg->dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB),
 521                &sdr_ctrl->dram_addrw);
 522 }
 523
 524 static void set_sdr_static_cfg(struct socfpga_sdram_config *cfg)
 525 {
 526         debug("Configuring STATICCFG\n");
 527         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 528 }
 529
 530 static void set_sdr_fifo_cfg(struct socfpga_sdram_config *cfg)
 531 {
 532         debug("Configuring FIFOCFG\n");
 533         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 534 }
 535
 536 static void set_sdr_mp_weight(struct socfpga_sdram_config *cfg)
 537 {
 538         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 539         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 540         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 541         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 542         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 543 }
 544
 545 static void set_sdr_mp_pacing(struct socfpga_sdram_config *cfg)
 546 {
 547         debug("Configuring MPPACING_MPPACING_0\n");
 548         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 549         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 550         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 551         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 552 }
 553
 554 static void set_sdr_mp_threshold(struct socfpga_sdram_config *cfg)
 555 {
 556         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 557         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 558         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 559         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 560 }
 561
 562 /* Function to initialize SDRAM MMR */
 563 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
 564 {
 565         unsigned long status = 0;
 566         struct socfpga_sdram_config *cfg = &sdram_config;
 567
 568 #if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
 569 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
 570 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
 571 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
 572 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
 573
 574         writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
 575                &sysmgr_regs->iswgrp_handoff[4]);
 576 #endif
 577         set_sdr_ctrlcfg(cfg);
 578         set_sdr_dram_timing(cfg);
 579         set_sdr_addr_rw(cfg);
 580
 581         debug("Configuring DRAMIFWIDTH\n");
 582         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 583
 584         debug("Configuring DRAMDEVWIDTH\n");
 585         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 586
 587         debug("Configuring LOWPWREQ\n");
 588         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 589
 590         debug("Configuring DRAMINTR\n");
 591         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 592
 593         set_sdr_static_cfg(cfg);
 594
 595         debug("Configuring CTRLWIDTH\n");
 596         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 597
 598         debug("Configuring PORTCFG\n");
 599         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 600
 601         set_sdr_fifo_cfg(cfg);
 602
 603         debug("Configuring MPPRIORITY\n");
 604         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 605
 606         set_sdr_mp_weight(cfg);
 607         set_sdr_mp_pacing(cfg);
 608         set_sdr_mp_threshold(cfg);
 609
 610         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 611         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 612
 613         debug("Configuring CPORTWIDTH\n");
 614         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 615
 616         debug("Configuring CPORTWMAP\n");
 617         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 618
 619         debug("Configuring CPORTRMAP\n");
 620         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 621
 622         debug("Configuring RFIFOCMAP\n");
 623         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 624
 625         debug("Configuring WFIFOCMAP\n");
 626         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 627
 628         debug("Configuring CPORTRDWR\n");
 629         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 630
 631         debug("Configuring DRAMODT\n");
 632         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 633
 634         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 635         writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
 636
 637         /* only enable if the FPGA is programmed */
 638         if (fpgamgr_test_fpga_ready()) {
 639                 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 640                     cfg->fpgaport_rst) == 1) {
 641                         status = 1;
 642                         return 1;
 643                 }
 644         }
 645
 646         /* Restore the SDR PHY Register if valid */
 647         if (sdr_phy_reg != 0xffffffff)
 648                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 649
 650         /* Final step - apply configuration changes */
 651         debug("Configuring STATICCFG\n");
 652         clrsetbits_le32(&sdr_ctrl->static_cfg,
 653                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 654                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 655
 656         sdram_set_protection_config(0, sdram_calculate_size());
 657
 658         sdram_dump_protection_config();
 659
 660         return status;
 661 }
 662
 663 /*
 664  * To calculate SDRAM device size based on SDRAM controller parameters.
 665  * Size is specified in bytes.
 666  *
 667  * NOTE:
 668  * This function is compiled and linked into the preloader and
 669  * Uboot (there may be others). So if this function changes, the Preloader
 670  * and UBoot must be updated simultaneously.
 671  */
 672 unsigned long sdram_calculate_size(void)
 673 {
 674         unsigned long temp;
 675         unsigned long row, bank, col, cs, width;
 676
 677         temp = readl(&sdr_ctrl->dram_addrw);
 678         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 679                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 680
 681         /* SDRAM Failure When Accessing Non-Existent Memory
 682          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 683          * since the FB specifies we modify ROWBITs to work around SDRAM
 684          * controller issue.
 685          *
 686          * If the stored handoff value for rows is 0, it probably means
 687          * the preloader is older than UBoot. Use the
 688          * #define from the SOCEDS Tools per Crucible review
 689          * uboot-socfpga-204. Note that this is not a supported
 690          * configuration and is not tested. The customer
 691          * should be using preloader and uboot built from the
 692          * same tag.
 693          */
 694         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 695         if (row == 0)
 696                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 697         /* If the stored handoff value for rows is greater than
 698          * the field width in the sdr.dramaddrw register then
 699          * something is very wrong. Revert to using the the #define
 700          * value handed off by the SOCEDS tool chain instead of
 701          * using a broken value.
 702          */
 703         if (row > 31)
 704                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 705
 706         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 707                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 708
 709         /* SDRAM Failure When Accessing Non-Existent Memory
 710          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 711          * since the FB specifies we modify CSBITs to work around SDRAM
 712          * controller issue.
 713          */
 714         cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 715               SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
 716         cs += 1;
 717
 718         cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 719
 720         width = readl(&sdr_ctrl->dram_if_width);
 721         /* ECC would not be calculated as its not addressible */
 722         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 723                 width = 32;
 724         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 725                 width = 16;
 726
 727         /* calculate the SDRAM size base on this info */
 728         temp = 1 << (row + bank + col);
 729         temp = temp * cs * (width  / 8);
 730
 731         debug("sdram_calculate_memory returns %ld\n", temp);
 732
 733         return temp;
 734 }