drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <div64.h>
   9 #include <watchdog.h>
  10 #include <asm/arch/fpga_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/system_manager.h>
  13 #include <asm/io.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 struct sdram_prot_rule {
  18         u64     sdram_start;    /* SDRAM start address */
  19         u64     sdram_end;      /* SDRAM end address */
  20         u32     rule;           /* SDRAM protection rule number: 0-19 */
  21         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  22
  23         u32     security;
  24         u32     portmask;
  25         u32     result;
  26         u32     lo_prot_id;
  27         u32     hi_prot_id;
  28 };
  29
  30 static struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32 static struct socfpga_sdr_ctrl *sdr_ctrl =
  33         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  34
  35 /**
  36  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  37  * @cfg:        SDRAM controller configuration data
  38  *
  39  * SDRAM Failure happens when accessing non-existent memory. Artificially
  40  * increase the number of rows so that the memory controller thinks it has
  41  * 4GB of RAM. This function returns such amount of rows.
  42  */
  43 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  44 {
  45         /* Define constant for 4G memory - used for SDRAM errata workaround */
  46 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  47         const unsigned long long memsize = MEMSIZE_4G;
  48         const unsigned int cs =
  49                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  50                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  51         const unsigned int rows =
  52                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  53                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  54         const unsigned int banks =
  55                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  56                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  57         const unsigned int cols =
  58                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  59                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  60         const unsigned int width = 8;
  61
  62         unsigned long long newrows;
  63         int bits, inewrowslog2;
  64
  65         debug("workaround rows - memsize %lld\n", memsize);
  66         debug("workaround rows - cs        %d\n", cs);
  67         debug("workaround rows - width     %d\n", width);
  68         debug("workaround rows - rows      %d\n", rows);
  69         debug("workaround rows - banks     %d\n", banks);
  70         debug("workaround rows - cols      %d\n", cols);
  71
  72         newrows = lldiv(memsize, cs * (width / 8));
  73         debug("rows workaround - term1 %lld\n", newrows);
  74
  75         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  76         debug("rows workaround - term2 %lld\n", newrows);
  77
  78         /*
  79          * Compute the hamming weight - same as number of bits set.
  80          * Need to see if result is ordinal power of 2 before
  81          * attempting log2 of result.
  82          */
  83         bits = generic_hweight32(newrows);
  84
  85         debug("rows workaround - bits %d\n", bits);
  86
  87         if (bits != 1) {
  88                 printf("SDRAM workaround failed, bits set %d\n", bits);
  89                 return rows;
  90         }
  91
  92         if (newrows > UINT_MAX) {
  93                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  94                 return rows;
  95         }
  96
  97         inewrowslog2 = __ilog2(newrows);
  98
  99         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 100
 101         if (inewrowslog2 == -1) {
 102                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 103                 return rows;
 104         }
 105
 106         return inewrowslog2;
 107 }
 108
 109 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 110 static void sdram_set_rule(struct sdram_prot_rule *prule)
 111 {
 112         uint32_t lo_addr_bits;
 113         uint32_t hi_addr_bits;
 114         int ruleno = prule->rule;
 115
 116         /* Select the rule */
 117         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 118
 119         /* Obtain the address bits */
 120         lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
 121         hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
 122
 123         debug("sdram set rule start %x, %lld\n", lo_addr_bits,
 124               prule->sdram_start);
 125         debug("sdram set rule end   %x, %lld\n", hi_addr_bits,
 126               prule->sdram_end);
 127
 128         /* Set rule addresses */
 129         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 130
 131         /* Set rule protection ids */
 132         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 133                &sdr_ctrl->prot_rule_id);
 134
 135         /* Set the rule data */
 136         writel(prule->security | (prule->valid << 2) |
 137                (prule->portmask << 3) | (prule->result << 13),
 138                &sdr_ctrl->prot_rule_data);
 139
 140         /* write the rule */
 141         writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
 142
 143         /* Set rule number to 0 by default */
 144         writel(0, &sdr_ctrl->prot_rule_rdwr);
 145 }
 146
 147 static void sdram_get_rule(struct sdram_prot_rule *prule)
 148 {
 149         uint32_t addr;
 150         uint32_t id;
 151         uint32_t data;
 152         int ruleno = prule->rule;
 153
 154         /* Read the rule */
 155         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 156         writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
 157
 158         /* Get the addresses */
 159         addr = readl(&sdr_ctrl->prot_rule_addr);
 160         prule->sdram_start = (addr & 0xFFF) << 20;
 161         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 162
 163         /* Get the configured protection IDs */
 164         id = readl(&sdr_ctrl->prot_rule_id);
 165         prule->lo_prot_id = id & 0xFFF;
 166         prule->hi_prot_id = (id >> 12) & 0xFFF;
 167
 168         /* Get protection data */
 169         data = readl(&sdr_ctrl->prot_rule_data);
 170
 171         prule->security = data & 0x3;
 172         prule->valid = (data >> 2) & 0x1;
 173         prule->portmask = (data >> 3) & 0x3FF;
 174         prule->result = (data >> 13) & 0x1;
 175 }
 176
 177 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
 178 {
 179         struct sdram_prot_rule rule;
 180         int rules;
 181
 182         /* Start with accepting all SDRAM transaction */
 183         writel(0x0, &sdr_ctrl->protport_default);
 184
 185         /* Clear all protection rules for warm boot case */
 186         memset(&rule, 0, sizeof(struct sdram_prot_rule));
 187
 188         for (rules = 0; rules < 20; rules++) {
 189                 rule.rule = rules;
 190                 sdram_set_rule(&rule);
 191         }
 192
 193         /* new rule: accept SDRAM */
 194         rule.sdram_start = sdram_start;
 195         rule.sdram_end = sdram_end;
 196         rule.lo_prot_id = 0x0;
 197         rule.hi_prot_id = 0xFFF;
 198         rule.portmask = 0x3FF;
 199         rule.security = 0x3;
 200         rule.result = 0;
 201         rule.valid = 1;
 202         rule.rule = 0;
 203
 204         /* set new rule */
 205         sdram_set_rule(&rule);
 206
 207         /* default rule: reject everything */
 208         writel(0x3ff, &sdr_ctrl->protport_default);
 209 }
 210
 211 static void sdram_dump_protection_config(void)
 212 {
 213         struct sdram_prot_rule rule;
 214         int rules;
 215
 216         debug("SDRAM Prot rule, default %x\n",
 217               readl(&sdr_ctrl->protport_default));
 218
 219         for (rules = 0; rules < 20; rules++) {
 220                 sdram_get_rule(&rule);
 221                 debug("Rule %d, rules ...\n", rules);
 222                 debug("    sdram start %llx\n", rule.sdram_start);
 223                 debug("    sdram end   %llx\n", rule.sdram_end);
 224                 debug("    low prot id %d, hi prot id %d\n",
 225                       rule.lo_prot_id,
 226                       rule.hi_prot_id);
 227                 debug("    portmask %x\n", rule.portmask);
 228                 debug("    security %d\n", rule.security);
 229                 debug("    result %d\n", rule.result);
 230                 debug("    valid %d\n", rule.valid);
 231         }
 232 }
 233
 234 /* Function to write to register and verify the write */
 235 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
 236 {
 237 #ifndef SDRAM_MMR_SKIP_VERIFY
 238         unsigned reg_value1;
 239 #endif
 240         debug("   Write - Address ");
 241         debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
 242         /* Write to register */
 243         writel(reg_value, addr);
 244 #ifndef SDRAM_MMR_SKIP_VERIFY
 245         debug("   Read and verify...");
 246         /* Read back the wrote value */
 247         reg_value1 = readl(addr);
 248         /* Indicate failure if value not matched */
 249         if (reg_value1 != reg_value) {
 250                 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
 251                       (u32)addr, reg_value, reg_value1);
 252                 return 1;
 253         }
 254         debug("correct!\n");
 255 #endif  /* SDRAM_MMR_SKIP_VERIFY */
 256         return 0;
 257 }
 258
 259 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
 260 {
 261         const u32 csbits =
 262                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 263                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 264         u32 addrorder =
 265                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 266                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 267
 268         u32 ctrl_cfg = cfg->ctrl_cfg;
 269
 270         /*
 271          * SDRAM Failure When Accessing Non-Existent Memory
 272          * Set the addrorder field of the SDRAM control register
 273          * based on the CSBITs setting.
 274          */
 275         if (csbits == 1) {
 276                 if (addrorder != 0)
 277                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 278                 addrorder = 0;
 279         } else if (csbits == 2) {
 280                 if (addrorder != 2)
 281                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 282                 addrorder = 2;
 283         }
 284
 285         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 286         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 287
 288         return ctrl_cfg;
 289 }
 290
 291 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
 292 {
 293         /*
 294          * SDRAM Failure When Accessing Non-Existent Memory
 295          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 296          * log2(number of chip select bits). Since there's only
 297          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 298          * which is the same as "chip selects" - 1.
 299          */
 300         const int rows = get_errata_rows(cfg);
 301         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 302
 303         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 304 }
 305
 306 /**
 307  * sdr_load_regs() - Load SDRAM controller registers
 308  * @cfg:        SDRAM controller configuration data
 309  *
 310  * This function loads the register values into the SDRAM controller block.
 311  */
 312 static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
 313 {
 314         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 315         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 316
 317         debug("\nConfiguring CTRLCFG\n");
 318         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 319
 320         debug("Configuring DRAMTIMING1\n");
 321         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 322
 323         debug("Configuring DRAMTIMING2\n");
 324         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 325
 326         debug("Configuring DRAMTIMING3\n");
 327         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 328
 329         debug("Configuring DRAMTIMING4\n");
 330         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 331
 332         debug("Configuring LOWPWRTIMING\n");
 333         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 334
 335         debug("Configuring DRAMADDRW\n");
 336         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 337
 338         debug("Configuring DRAMIFWIDTH\n");
 339         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 340
 341         debug("Configuring DRAMDEVWIDTH\n");
 342         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 343
 344         debug("Configuring LOWPWREQ\n");
 345         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 346
 347         debug("Configuring DRAMINTR\n");
 348         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 349
 350         debug("Configuring STATICCFG\n");
 351         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 352
 353         debug("Configuring CTRLWIDTH\n");
 354         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 355
 356         debug("Configuring PORTCFG\n");
 357         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 358
 359         debug("Configuring FIFOCFG\n");
 360         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 361
 362         debug("Configuring MPPRIORITY\n");
 363         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 364
 365         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 366         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 367         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 368         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 369         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 370
 371         debug("Configuring MPPACING_MPPACING_0\n");
 372         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 373         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 374         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 375         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 376
 377         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 378         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 379         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 380         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 381
 382         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 383         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 384
 385         debug("Configuring CPORTWIDTH\n");
 386         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 387
 388         debug("Configuring CPORTWMAP\n");
 389         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 390
 391         debug("Configuring CPORTRMAP\n");
 392         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 393
 394         debug("Configuring RFIFOCMAP\n");
 395         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 396
 397         debug("Configuring WFIFOCMAP\n");
 398         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 399
 400         debug("Configuring CPORTRDWR\n");
 401         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 402
 403         debug("Configuring DRAMODT\n");
 404         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 405 }
 406
 407 /**
 408  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 409  * @sdr_phy_reg:        Value of the PHY control register 0
 410  *
 411  * Initialize the SDRAM MMR.
 412  */
 413 int sdram_mmr_init_full(unsigned int sdr_phy_reg)
 414 {
 415         unsigned long status = 0;
 416         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 417         const unsigned int rows =
 418                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 419                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 420
 421         writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
 422
 423         sdr_load_regs(cfg);
 424
 425         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 426         writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
 427
 428         /* only enable if the FPGA is programmed */
 429         if (fpgamgr_test_fpga_ready()) {
 430                 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 431                     cfg->fpgaport_rst) == 1) {
 432                         status = 1;
 433                         return 1;
 434                 }
 435         }
 436
 437         /* Restore the SDR PHY Register if valid */
 438         if (sdr_phy_reg != 0xffffffff)
 439                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 440
 441         /* Final step - apply configuration changes */
 442         debug("Configuring STATICCFG\n");
 443         clrsetbits_le32(&sdr_ctrl->static_cfg,
 444                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 445                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 446
 447         sdram_set_protection_config(0, sdram_calculate_size());
 448
 449         sdram_dump_protection_config();
 450
 451         return status;
 452 }
 453
 454 /**
 455  * sdram_calculate_size() - Calculate SDRAM size
 456  *
 457  * Calculate SDRAM device size based on SDRAM controller parameters.
 458  * Size is specified in bytes.
 459  */
 460 unsigned long sdram_calculate_size(void)
 461 {
 462         unsigned long temp;
 463         unsigned long row, bank, col, cs, width;
 464         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 465         const unsigned int csbits =
 466                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 467                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 468         const unsigned int rowbits =
 469                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 470                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 471
 472         temp = readl(&sdr_ctrl->dram_addrw);
 473         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 474                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 475
 476         /*
 477          * SDRAM Failure When Accessing Non-Existent Memory
 478          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 479          * since the FB specifies we modify ROWBITs to work around SDRAM
 480          * controller issue.
 481          */
 482         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 483         if (row == 0)
 484                 row = rowbits;
 485         /*
 486          * If the stored handoff value for rows is greater than
 487          * the field width in the sdr.dramaddrw register then
 488          * something is very wrong. Revert to using the the #define
 489          * value handed off by the SOCEDS tool chain instead of
 490          * using a broken value.
 491          */
 492         if (row > 31)
 493                 row = rowbits;
 494
 495         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 496                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 497
 498         /*
 499          * SDRAM Failure When Accessing Non-Existent Memory
 500          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 501          * since the FB specifies we modify CSBITs to work around SDRAM
 502          * controller issue.
 503          */
 504         cs = csbits;
 505
 506         width = readl(&sdr_ctrl->dram_if_width);
 507
 508         /* ECC would not be calculated as its not addressible */
 509         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 510                 width = 32;
 511         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 512                 width = 16;
 513
 514         /* calculate the SDRAM size base on this info */
 515         temp = 1 << (row + bank + col);
 516         temp = temp * cs * (width  / 8);
 517
 518         debug("%s returns %ld\n", __func__, temp);
 519
 520         return temp;
 521 }