drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <div64.h>
   9 #include <watchdog.h>
  10 #include <asm/arch/fpga_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/system_manager.h>
  13 #include <asm/io.h>
  14
  15 /*
  16  * FIXME: This path is temporary until the SDRAM driver gets
  17  *        a proper thorough cleanup.
  18  */
  19 #include "../../../board/altera/socfpga/qts/sdram_config.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct sdram_prot_rule {
  24         u64     sdram_start;    /* SDRAM start address */
  25         u64     sdram_end;      /* SDRAM end address */
  26         u32     rule;           /* SDRAM protection rule number: 0-19 */
  27         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  28
  29         u32     security;
  30         u32     portmask;
  31         u32     result;
  32         u32     lo_prot_id;
  33         u32     hi_prot_id;
  34 };
  35
  36 static struct socfpga_system_manager *sysmgr_regs =
  37         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 /**
  42  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  43  * @cfg:        SDRAM controller configuration data
  44  *
  45  * SDRAM Failure happens when accessing non-existent memory. Artificially
  46  * increase the number of rows so that the memory controller thinks it has
  47  * 4GB of RAM. This function returns such amount of rows.
  48  */
  49 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  50 {
  51         /* Define constant for 4G memory - used for SDRAM errata workaround */
  52 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  53         const unsigned long long memsize = MEMSIZE_4G;
  54         const unsigned int cs =
  55                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  56                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  57         const unsigned int rows =
  58                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  59                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  60         const unsigned int banks =
  61                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  62                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  63         const unsigned int cols =
  64                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  65                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  66         const unsigned int width = 8;
  67
  68         unsigned long long newrows;
  69         int bits, inewrowslog2;
  70
  71         debug("workaround rows - memsize %lld\n", memsize);
  72         debug("workaround rows - cs        %d\n", cs);
  73         debug("workaround rows - width     %d\n", width);
  74         debug("workaround rows - rows      %d\n", rows);
  75         debug("workaround rows - banks     %d\n", banks);
  76         debug("workaround rows - cols      %d\n", cols);
  77
  78         newrows = lldiv(memsize, cs * (width / 8));
  79         debug("rows workaround - term1 %lld\n", newrows);
  80
  81         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  82         debug("rows workaround - term2 %lld\n", newrows);
  83
  84         /*
  85          * Compute the hamming weight - same as number of bits set.
  86          * Need to see if result is ordinal power of 2 before
  87          * attempting log2 of result.
  88          */
  89         bits = generic_hweight32(newrows);
  90
  91         debug("rows workaround - bits %d\n", bits);
  92
  93         if (bits != 1) {
  94                 printf("SDRAM workaround failed, bits set %d\n", bits);
  95                 return rows;
  96         }
  97
  98         if (newrows > UINT_MAX) {
  99                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
 100                 return rows;
 101         }
 102
 103         inewrowslog2 = __ilog2(newrows);
 104
 105         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 106
 107         if (inewrowslog2 == -1) {
 108                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 109                 return rows;
 110         }
 111
 112         return inewrowslog2;
 113 }
 114
 115 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 116 static void sdram_set_rule(struct sdram_prot_rule *prule)
 117 {
 118         uint32_t lo_addr_bits;
 119         uint32_t hi_addr_bits;
 120         int ruleno = prule->rule;
 121
 122         /* Select the rule */
 123         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 124
 125         /* Obtain the address bits */
 126         lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
 127         hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
 128
 129         debug("sdram set rule start %x, %lld\n", lo_addr_bits,
 130               prule->sdram_start);
 131         debug("sdram set rule end   %x, %lld\n", hi_addr_bits,
 132               prule->sdram_end);
 133
 134         /* Set rule addresses */
 135         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 136
 137         /* Set rule protection ids */
 138         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 139                &sdr_ctrl->prot_rule_id);
 140
 141         /* Set the rule data */
 142         writel(prule->security | (prule->valid << 2) |
 143                (prule->portmask << 3) | (prule->result << 13),
 144                &sdr_ctrl->prot_rule_data);
 145
 146         /* write the rule */
 147         writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
 148
 149         /* Set rule number to 0 by default */
 150         writel(0, &sdr_ctrl->prot_rule_rdwr);
 151 }
 152
 153 static void sdram_get_rule(struct sdram_prot_rule *prule)
 154 {
 155         uint32_t addr;
 156         uint32_t id;
 157         uint32_t data;
 158         int ruleno = prule->rule;
 159
 160         /* Read the rule */
 161         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 162         writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
 163
 164         /* Get the addresses */
 165         addr = readl(&sdr_ctrl->prot_rule_addr);
 166         prule->sdram_start = (addr & 0xFFF) << 20;
 167         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 168
 169         /* Get the configured protection IDs */
 170         id = readl(&sdr_ctrl->prot_rule_id);
 171         prule->lo_prot_id = id & 0xFFF;
 172         prule->hi_prot_id = (id >> 12) & 0xFFF;
 173
 174         /* Get protection data */
 175         data = readl(&sdr_ctrl->prot_rule_data);
 176
 177         prule->security = data & 0x3;
 178         prule->valid = (data >> 2) & 0x1;
 179         prule->portmask = (data >> 3) & 0x3FF;
 180         prule->result = (data >> 13) & 0x1;
 181 }
 182
 183 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
 184 {
 185         struct sdram_prot_rule rule;
 186         int rules;
 187
 188         /* Start with accepting all SDRAM transaction */
 189         writel(0x0, &sdr_ctrl->protport_default);
 190
 191         /* Clear all protection rules for warm boot case */
 192         memset(&rule, 0, sizeof(struct sdram_prot_rule));
 193
 194         for (rules = 0; rules < 20; rules++) {
 195                 rule.rule = rules;
 196                 sdram_set_rule(&rule);
 197         }
 198
 199         /* new rule: accept SDRAM */
 200         rule.sdram_start = sdram_start;
 201         rule.sdram_end = sdram_end;
 202         rule.lo_prot_id = 0x0;
 203         rule.hi_prot_id = 0xFFF;
 204         rule.portmask = 0x3FF;
 205         rule.security = 0x3;
 206         rule.result = 0;
 207         rule.valid = 1;
 208         rule.rule = 0;
 209
 210         /* set new rule */
 211         sdram_set_rule(&rule);
 212
 213         /* default rule: reject everything */
 214         writel(0x3ff, &sdr_ctrl->protport_default);
 215 }
 216
 217 static void sdram_dump_protection_config(void)
 218 {
 219         struct sdram_prot_rule rule;
 220         int rules;
 221
 222         debug("SDRAM Prot rule, default %x\n",
 223               readl(&sdr_ctrl->protport_default));
 224
 225         for (rules = 0; rules < 20; rules++) {
 226                 sdram_get_rule(&rule);
 227                 debug("Rule %d, rules ...\n", rules);
 228                 debug("    sdram start %llx\n", rule.sdram_start);
 229                 debug("    sdram end   %llx\n", rule.sdram_end);
 230                 debug("    low prot id %d, hi prot id %d\n",
 231                       rule.lo_prot_id,
 232                       rule.hi_prot_id);
 233                 debug("    portmask %x\n", rule.portmask);
 234                 debug("    security %d\n", rule.security);
 235                 debug("    result %d\n", rule.result);
 236                 debug("    valid %d\n", rule.valid);
 237         }
 238 }
 239
 240 /* Function to write to register and verify the write */
 241 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
 242 {
 243 #ifndef SDRAM_MMR_SKIP_VERIFY
 244         unsigned reg_value1;
 245 #endif
 246         debug("   Write - Address ");
 247         debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
 248         /* Write to register */
 249         writel(reg_value, addr);
 250 #ifndef SDRAM_MMR_SKIP_VERIFY
 251         debug("   Read and verify...");
 252         /* Read back the wrote value */
 253         reg_value1 = readl(addr);
 254         /* Indicate failure if value not matched */
 255         if (reg_value1 != reg_value) {
 256                 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
 257                       (u32)addr, reg_value, reg_value1);
 258                 return 1;
 259         }
 260         debug("correct!\n");
 261 #endif  /* SDRAM_MMR_SKIP_VERIFY */
 262         return 0;
 263 }
 264
 265 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
 266 {
 267         const u32 csbits =
 268                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 269                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 270         u32 addrorder =
 271                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 272                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 273
 274         u32 ctrl_cfg = cfg->ctrl_cfg;
 275
 276         /*
 277          * SDRAM Failure When Accessing Non-Existent Memory
 278          * Set the addrorder field of the SDRAM control register
 279          * based on the CSBITs setting.
 280          */
 281         if (csbits == 1) {
 282                 if (addrorder != 0)
 283                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 284                 addrorder = 0;
 285         } else if (csbits == 2) {
 286                 if (addrorder != 2)
 287                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 288                 addrorder = 2;
 289         }
 290
 291         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 292         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 293
 294         return ctrl_cfg;
 295 }
 296
 297 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
 298 {
 299         /*
 300          * SDRAM Failure When Accessing Non-Existent Memory
 301          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 302          * log2(number of chip select bits). Since there's only
 303          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 304          * which is the same as "chip selects" - 1.
 305          */
 306         const int rows = get_errata_rows(cfg);
 307         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 308
 309         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 310 }
 311
 312 /**
 313  * sdr_load_regs() - Load SDRAM controller registers
 314  * @cfg:        SDRAM controller configuration data
 315  *
 316  * This function loads the register values into the SDRAM controller block.
 317  */
 318 static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
 319 {
 320         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 321         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 322
 323         debug("\nConfiguring CTRLCFG\n");
 324         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 325
 326         debug("Configuring DRAMTIMING1\n");
 327         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 328
 329         debug("Configuring DRAMTIMING2\n");
 330         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 331
 332         debug("Configuring DRAMTIMING3\n");
 333         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 334
 335         debug("Configuring DRAMTIMING4\n");
 336         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 337
 338         debug("Configuring LOWPWRTIMING\n");
 339         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 340
 341         debug("Configuring DRAMADDRW\n");
 342         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 343
 344         debug("Configuring DRAMIFWIDTH\n");
 345         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 346
 347         debug("Configuring DRAMDEVWIDTH\n");
 348         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 349
 350         debug("Configuring LOWPWREQ\n");
 351         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 352
 353         debug("Configuring DRAMINTR\n");
 354         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 355
 356         debug("Configuring STATICCFG\n");
 357         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 358
 359         debug("Configuring CTRLWIDTH\n");
 360         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 361
 362         debug("Configuring PORTCFG\n");
 363         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 364
 365         debug("Configuring FIFOCFG\n");
 366         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 367
 368         debug("Configuring MPPRIORITY\n");
 369         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 370
 371         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 372         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 373         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 374         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 375         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 376
 377         debug("Configuring MPPACING_MPPACING_0\n");
 378         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 379         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 380         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 381         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 382
 383         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 384         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 385         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 386         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 387
 388         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 389         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 390
 391         debug("Configuring CPORTWIDTH\n");
 392         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 393
 394         debug("Configuring CPORTWMAP\n");
 395         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 396
 397         debug("Configuring CPORTRMAP\n");
 398         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 399
 400         debug("Configuring RFIFOCMAP\n");
 401         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 402
 403         debug("Configuring WFIFOCMAP\n");
 404         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 405
 406         debug("Configuring CPORTRDWR\n");
 407         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 408
 409         debug("Configuring DRAMODT\n");
 410         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 411 }
 412
 413 /**
 414  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 415  * @sdr_phy_reg:        Value of the PHY control register 0
 416  *
 417  * Initialize the SDRAM MMR.
 418  */
 419 int sdram_mmr_init_full(unsigned int sdr_phy_reg)
 420 {
 421         unsigned long status = 0;
 422         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 423         const unsigned int rows =
 424                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 425                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 426
 427         writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
 428
 429         sdr_load_regs(cfg);
 430
 431         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 432         writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
 433
 434         /* only enable if the FPGA is programmed */
 435         if (fpgamgr_test_fpga_ready()) {
 436                 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 437                     cfg->fpgaport_rst) == 1) {
 438                         status = 1;
 439                         return 1;
 440                 }
 441         }
 442
 443         /* Restore the SDR PHY Register if valid */
 444         if (sdr_phy_reg != 0xffffffff)
 445                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 446
 447         /* Final step - apply configuration changes */
 448         debug("Configuring STATICCFG\n");
 449         clrsetbits_le32(&sdr_ctrl->static_cfg,
 450                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 451                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 452
 453         sdram_set_protection_config(0, sdram_calculate_size());
 454
 455         sdram_dump_protection_config();
 456
 457         return status;
 458 }
 459
 460 /*
 461  * To calculate SDRAM device size based on SDRAM controller parameters.
 462  * Size is specified in bytes.
 463  *
 464  * NOTE:
 465  * This function is compiled and linked into the preloader and
 466  * Uboot (there may be others). So if this function changes, the Preloader
 467  * and UBoot must be updated simultaneously.
 468  */
 469 unsigned long sdram_calculate_size(void)
 470 {
 471         unsigned long temp;
 472         unsigned long row, bank, col, cs, width;
 473
 474         temp = readl(&sdr_ctrl->dram_addrw);
 475         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 476                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 477
 478         /* SDRAM Failure When Accessing Non-Existent Memory
 479          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 480          * since the FB specifies we modify ROWBITs to work around SDRAM
 481          * controller issue.
 482          *
 483          * If the stored handoff value for rows is 0, it probably means
 484          * the preloader is older than UBoot. Use the
 485          * #define from the SOCEDS Tools per Crucible review
 486          * uboot-socfpga-204. Note that this is not a supported
 487          * configuration and is not tested. The customer
 488          * should be using preloader and uboot built from the
 489          * same tag.
 490          */
 491         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 492         if (row == 0)
 493                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 494         /* If the stored handoff value for rows is greater than
 495          * the field width in the sdr.dramaddrw register then
 496          * something is very wrong. Revert to using the the #define
 497          * value handed off by the SOCEDS tool chain instead of
 498          * using a broken value.
 499          */
 500         if (row > 31)
 501                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 502
 503         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 504                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 505
 506         /* SDRAM Failure When Accessing Non-Existent Memory
 507          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 508          * since the FB specifies we modify CSBITs to work around SDRAM
 509          * controller issue.
 510          */
 511         cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 512               SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
 513         cs += 1;
 514
 515         cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 516
 517         width = readl(&sdr_ctrl->dram_if_width);
 518         /* ECC would not be calculated as its not addressible */
 519         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 520                 width = 32;
 521         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 522                 width = 16;
 523
 524         /* calculate the SDRAM size base on this info */
 525         temp = 1 << (row + bank + col);
 526         temp = temp * cs * (width  / 8);
 527
 528         debug("sdram_calculate_memory returns %ld\n", temp);
 529
 530         return temp;
 531 }