drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <div64.h>
   9 #include <watchdog.h>
  10 #include <asm/arch/fpga_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/system_manager.h>
  13 #include <asm/io.h>
  14
  15 /*
  16  * FIXME: This path is temporary until the SDRAM driver gets
  17  *        a proper thorough cleanup.
  18  */
  19 #include "../../../board/altera/socfpga/qts/sdram_config.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct sdram_prot_rule {
  24         u64     sdram_start;    /* SDRAM start address */
  25         u64     sdram_end;      /* SDRAM end address */
  26         u32     rule;           /* SDRAM protection rule number: 0-19 */
  27         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  28
  29         u32     security;
  30         u32     portmask;
  31         u32     result;
  32         u32     lo_prot_id;
  33         u32     hi_prot_id;
  34 };
  35
  36 static struct socfpga_system_manager *sysmgr_regs =
  37         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 static struct socfpga_sdram_config {
  42         u32     ctrl_cfg;
  43         u32     dram_timing1;
  44         u32     dram_timing2;
  45         u32     dram_timing3;
  46         u32     dram_timing4;
  47         u32     lowpwr_timing;
  48         u32     dram_odt;
  49         u32     dram_addrw;
  50         u32     dram_if_width;
  51         u32     dram_dev_width;
  52         u32     dram_intr;
  53         u32     lowpwr_eq;
  54         u32     static_cfg;
  55         u32     ctrl_width;
  56         u32     cport_width;
  57         u32     cport_wmap;
  58         u32     cport_rmap;
  59         u32     rfifo_cmap;
  60         u32     wfifo_cmap;
  61         u32     cport_rdwr;
  62         u32     port_cfg;
  63         u32     fpgaport_rst;
  64         u32     fifo_cfg;
  65         u32     mp_priority;
  66         u32     mp_weight0;
  67         u32     mp_weight1;
  68         u32     mp_weight2;
  69         u32     mp_weight3;
  70         u32     mp_pacing0;
  71         u32     mp_pacing1;
  72         u32     mp_pacing2;
  73         u32     mp_pacing3;
  74         u32     mp_threshold0;
  75         u32     mp_threshold1;
  76         u32     mp_threshold2;
  77         u32     phy_ctrl0;
  78 } sdram_config = {
  79         .ctrl_cfg =
  80                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
  81                         SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)                |
  82                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
  83                         SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)                  |
  84                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
  85                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)              |
  86                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
  87                         SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)                  |
  88                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
  89                         SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)              |
  90                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
  91                         SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)              |
  92                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
  93                         SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)            |
  94                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
  95                         SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)               |
  96                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
  97                         SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
  98         .dram_timing1 =
  99                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
 100                         SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)               |
 101                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
 102                         SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)                |
 103                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
 104                         SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)                |
 105                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
 106                         SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)               |
 107                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
 108                         SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)               |
 109                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
 110                         SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
 111         .dram_timing2 =
 112                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
 113                         SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)              |
 114                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
 115                         SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)               |
 116                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
 117                         SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)                |
 118                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
 119                         SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)                |
 120                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
 121                         SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
 122         .dram_timing3 =
 123                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
 124                         SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)               |
 125                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
 126                         SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)               |
 127                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
 128                         SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)                |
 129                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
 130                         SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)               |
 131                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
 132                         SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
 133         .dram_timing4 =
 134                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
 135                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)       |
 136                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
 137                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
 138         .lowpwr_timing =
 139                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
 140                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)      |
 141                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
 142                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
 143         .dram_odt =
 144                 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
 145                         SDR_CTRLGRP_DRAMODT_READ_LSB)                   |
 146                 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
 147                         SDR_CTRLGRP_DRAMODT_WRITE_LSB),
 148         .dram_addrw =
 149                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
 150                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)              |
 151                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
 152                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)              |
 153                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
 154                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)             |
 155                 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
 156                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
 157         .dram_if_width =
 158                 (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
 159                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
 160         .dram_dev_width =
 161                 (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
 162                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
 163         .dram_intr =
 164                 (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 165                         SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
 166         .lowpwr_eq =
 167                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 168                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
 169         .static_cfg =
 170                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 171                         SDR_CTRLGRP_STATICCFG_MEMBL_LSB)                |
 172                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 173                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
 174         .ctrl_width =
 175                 (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 176                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
 177         .cport_width =
 178                 (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 179                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
 180         .cport_wmap =
 181                 (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 182                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
 183         .cport_rmap =
 184                 (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 185                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
 186         .rfifo_cmap =
 187                 (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 188                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
 189         .wfifo_cmap =
 190                 (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 191                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
 192         .cport_rdwr =
 193                 (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 194                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
 195         .port_cfg =
 196                 (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 197                         SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
 198         .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 199         .fifo_cfg =
 200                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 201                         SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)               |
 202                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 203                         SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
 204         .mp_priority =
 205                 (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 206                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
 207         .mp_weight0 =
 208                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 209                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
 210         .mp_weight1 =
 211                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 212                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
 213                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 214                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
 215         .mp_weight2 =
 216                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 217                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
 218         .mp_weight3 =
 219                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 220                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
 221         .mp_pacing0 =
 222                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 223                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
 224         .mp_pacing1 =
 225                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 226                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
 227                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 228                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
 229         .mp_pacing2 =
 230                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 231                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
 232         .mp_pacing3 =
 233                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 234                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
 235         .mp_threshold0 =
 236                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 237                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
 238         .mp_threshold1 =
 239                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 240                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
 241         .mp_threshold2 =
 242                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 243                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
 244         .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
 245 };
 246
 247 /**
 248  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
 249  * @cfg:        SDRAM controller configuration data
 250  *
 251  * SDRAM Failure happens when accessing non-existent memory. Artificially
 252  * increase the number of rows so that the memory controller thinks it has
 253  * 4GB of RAM. This function returns such amount of rows.
 254  */
 255 static int get_errata_rows(struct socfpga_sdram_config *cfg)
 256 {
 257         /* Define constant for 4G memory - used for SDRAM errata workaround */
 258 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
 259         const unsigned long long memsize = MEMSIZE_4G;
 260         const unsigned int cs =
 261                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 262                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 263         const unsigned int rows =
 264                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 265                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 266         const unsigned int banks =
 267                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 268                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 269         const unsigned int cols =
 270                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 271                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 272         const unsigned int width = 8;
 273
 274         unsigned long long newrows;
 275         int bits, inewrowslog2;
 276
 277         debug("workaround rows - memsize %lld\n", memsize);
 278         debug("workaround rows - cs        %d\n", cs);
 279         debug("workaround rows - width     %d\n", width);
 280         debug("workaround rows - rows      %d\n", rows);
 281         debug("workaround rows - banks     %d\n", banks);
 282         debug("workaround rows - cols      %d\n", cols);
 283
 284         newrows = lldiv(memsize, cs * (width / 8));
 285         debug("rows workaround - term1 %lld\n", newrows);
 286
 287         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
 288         debug("rows workaround - term2 %lld\n", newrows);
 289
 290         /*
 291          * Compute the hamming weight - same as number of bits set.
 292          * Need to see if result is ordinal power of 2 before
 293          * attempting log2 of result.
 294          */
 295         bits = generic_hweight32(newrows);
 296
 297         debug("rows workaround - bits %d\n", bits);
 298
 299         if (bits != 1) {
 300                 printf("SDRAM workaround failed, bits set %d\n", bits);
 301                 return rows;
 302         }
 303
 304         if (newrows > UINT_MAX) {
 305                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
 306                 return rows;
 307         }
 308
 309         inewrowslog2 = __ilog2(newrows);
 310
 311         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 312
 313         if (inewrowslog2 == -1) {
 314                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 315                 return rows;
 316         }
 317
 318         return inewrowslog2;
 319 }
 320
 321 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 322 static void sdram_set_rule(struct sdram_prot_rule *prule)
 323 {
 324         uint32_t lo_addr_bits;
 325         uint32_t hi_addr_bits;
 326         int ruleno = prule->rule;
 327
 328         /* Select the rule */
 329         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 330
 331         /* Obtain the address bits */
 332         lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
 333         hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
 334
 335         debug("sdram set rule start %x, %lld\n", lo_addr_bits,
 336               prule->sdram_start);
 337         debug("sdram set rule end   %x, %lld\n", hi_addr_bits,
 338               prule->sdram_end);
 339
 340         /* Set rule addresses */
 341         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 342
 343         /* Set rule protection ids */
 344         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 345                &sdr_ctrl->prot_rule_id);
 346
 347         /* Set the rule data */
 348         writel(prule->security | (prule->valid << 2) |
 349                (prule->portmask << 3) | (prule->result << 13),
 350                &sdr_ctrl->prot_rule_data);
 351
 352         /* write the rule */
 353         writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
 354
 355         /* Set rule number to 0 by default */
 356         writel(0, &sdr_ctrl->prot_rule_rdwr);
 357 }
 358
 359 static void sdram_get_rule(struct sdram_prot_rule *prule)
 360 {
 361         uint32_t addr;
 362         uint32_t id;
 363         uint32_t data;
 364         int ruleno = prule->rule;
 365
 366         /* Read the rule */
 367         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 368         writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
 369
 370         /* Get the addresses */
 371         addr = readl(&sdr_ctrl->prot_rule_addr);
 372         prule->sdram_start = (addr & 0xFFF) << 20;
 373         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 374
 375         /* Get the configured protection IDs */
 376         id = readl(&sdr_ctrl->prot_rule_id);
 377         prule->lo_prot_id = id & 0xFFF;
 378         prule->hi_prot_id = (id >> 12) & 0xFFF;
 379
 380         /* Get protection data */
 381         data = readl(&sdr_ctrl->prot_rule_data);
 382
 383         prule->security = data & 0x3;
 384         prule->valid = (data >> 2) & 0x1;
 385         prule->portmask = (data >> 3) & 0x3FF;
 386         prule->result = (data >> 13) & 0x1;
 387 }
 388
 389 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
 390 {
 391         struct sdram_prot_rule rule;
 392         int rules;
 393
 394         /* Start with accepting all SDRAM transaction */
 395         writel(0x0, &sdr_ctrl->protport_default);
 396
 397         /* Clear all protection rules for warm boot case */
 398         memset(&rule, 0, sizeof(struct sdram_prot_rule));
 399
 400         for (rules = 0; rules < 20; rules++) {
 401                 rule.rule = rules;
 402                 sdram_set_rule(&rule);
 403         }
 404
 405         /* new rule: accept SDRAM */
 406         rule.sdram_start = sdram_start;
 407         rule.sdram_end = sdram_end;
 408         rule.lo_prot_id = 0x0;
 409         rule.hi_prot_id = 0xFFF;
 410         rule.portmask = 0x3FF;
 411         rule.security = 0x3;
 412         rule.result = 0;
 413         rule.valid = 1;
 414         rule.rule = 0;
 415
 416         /* set new rule */
 417         sdram_set_rule(&rule);
 418
 419         /* default rule: reject everything */
 420         writel(0x3ff, &sdr_ctrl->protport_default);
 421 }
 422
 423 static void sdram_dump_protection_config(void)
 424 {
 425         struct sdram_prot_rule rule;
 426         int rules;
 427
 428         debug("SDRAM Prot rule, default %x\n",
 429               readl(&sdr_ctrl->protport_default));
 430
 431         for (rules = 0; rules < 20; rules++) {
 432                 sdram_get_rule(&rule);
 433                 debug("Rule %d, rules ...\n", rules);
 434                 debug("    sdram start %llx\n", rule.sdram_start);
 435                 debug("    sdram end   %llx\n", rule.sdram_end);
 436                 debug("    low prot id %d, hi prot id %d\n",
 437                       rule.lo_prot_id,
 438                       rule.hi_prot_id);
 439                 debug("    portmask %x\n", rule.portmask);
 440                 debug("    security %d\n", rule.security);
 441                 debug("    result %d\n", rule.result);
 442                 debug("    valid %d\n", rule.valid);
 443         }
 444 }
 445
 446 /* Function to write to register and verify the write */
 447 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
 448 {
 449 #ifndef SDRAM_MMR_SKIP_VERIFY
 450         unsigned reg_value1;
 451 #endif
 452         debug("   Write - Address ");
 453         debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
 454         /* Write to register */
 455         writel(reg_value, addr);
 456 #ifndef SDRAM_MMR_SKIP_VERIFY
 457         debug("   Read and verify...");
 458         /* Read back the wrote value */
 459         reg_value1 = readl(addr);
 460         /* Indicate failure if value not matched */
 461         if (reg_value1 != reg_value) {
 462                 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
 463                       (u32)addr, reg_value, reg_value1);
 464                 return 1;
 465         }
 466         debug("correct!\n");
 467 #endif  /* SDRAM_MMR_SKIP_VERIFY */
 468         return 0;
 469 }
 470
 471 static u32 sdr_get_ctrlcfg(struct socfpga_sdram_config *cfg)
 472 {
 473         const u32 csbits =
 474                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 475                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 476         u32 addrorder =
 477                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 478                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 479
 480         u32 ctrl_cfg = cfg->ctrl_cfg;
 481
 482         /*
 483          * SDRAM Failure When Accessing Non-Existent Memory
 484          * Set the addrorder field of the SDRAM control register
 485          * based on the CSBITs setting.
 486          */
 487         if (csbits == 1) {
 488                 if (addrorder != 0)
 489                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 490                 addrorder = 0;
 491         } else if (csbits == 2) {
 492                 if (addrorder != 2)
 493                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 494                 addrorder = 2;
 495         }
 496
 497         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 498         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 499
 500         return ctrl_cfg;
 501 }
 502
 503 static u32 sdr_get_addr_rw(struct socfpga_sdram_config *cfg)
 504 {
 505         /*
 506          * SDRAM Failure When Accessing Non-Existent Memory
 507          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 508          * log2(number of chip select bits). Since there's only
 509          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 510          * which is the same as "chip selects" - 1.
 511          */
 512         const int rows = get_errata_rows(cfg);
 513         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 514
 515         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 516 }
 517
 518 /**
 519  * sdr_load_regs() - Load SDRAM controller registers
 520  * @cfg:        SDRAM controller configuration data
 521  *
 522  * This function loads the register values into the SDRAM controller block.
 523  */
 524 static void sdr_load_regs(struct socfpga_sdram_config *cfg)
 525 {
 526         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 527         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 528
 529         debug("\nConfiguring CTRLCFG\n");
 530         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 531
 532         debug("Configuring DRAMTIMING1\n");
 533         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 534
 535         debug("Configuring DRAMTIMING2\n");
 536         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 537
 538         debug("Configuring DRAMTIMING3\n");
 539         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 540
 541         debug("Configuring DRAMTIMING4\n");
 542         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 543
 544         debug("Configuring LOWPWRTIMING\n");
 545         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 546
 547         debug("Configuring DRAMADDRW\n");
 548         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 549
 550         debug("Configuring DRAMIFWIDTH\n");
 551         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 552
 553         debug("Configuring DRAMDEVWIDTH\n");
 554         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 555
 556         debug("Configuring LOWPWREQ\n");
 557         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 558
 559         debug("Configuring DRAMINTR\n");
 560         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 561
 562         debug("Configuring STATICCFG\n");
 563         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 564
 565         debug("Configuring CTRLWIDTH\n");
 566         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 567
 568         debug("Configuring PORTCFG\n");
 569         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 570
 571         debug("Configuring FIFOCFG\n");
 572         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 573
 574         debug("Configuring MPPRIORITY\n");
 575         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 576
 577         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 578         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 579         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 580         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 581         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 582
 583         debug("Configuring MPPACING_MPPACING_0\n");
 584         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 585         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 586         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 587         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 588
 589         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 590         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 591         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 592         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 593
 594         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 595         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 596
 597         debug("Configuring CPORTWIDTH\n");
 598         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 599
 600         debug("Configuring CPORTWMAP\n");
 601         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 602
 603         debug("Configuring CPORTRMAP\n");
 604         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 605
 606         debug("Configuring RFIFOCMAP\n");
 607         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 608
 609         debug("Configuring WFIFOCMAP\n");
 610         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 611
 612         debug("Configuring CPORTRDWR\n");
 613         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 614
 615         debug("Configuring DRAMODT\n");
 616         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 617 }
 618
 619 /**
 620  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 621  * @sdr_phy_reg:        Value of the PHY control register 0
 622  *
 623  * Initialize the SDRAM MMR.
 624  */
 625 int sdram_mmr_init_full(unsigned int sdr_phy_reg)
 626 {
 627         unsigned long status = 0;
 628         struct socfpga_sdram_config *cfg = &sdram_config;
 629         const unsigned int rows =
 630                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 631                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 632
 633         writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
 634
 635         sdr_load_regs(cfg);
 636
 637         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 638         writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
 639
 640         /* only enable if the FPGA is programmed */
 641         if (fpgamgr_test_fpga_ready()) {
 642                 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 643                     cfg->fpgaport_rst) == 1) {
 644                         status = 1;
 645                         return 1;
 646                 }
 647         }
 648
 649         /* Restore the SDR PHY Register if valid */
 650         if (sdr_phy_reg != 0xffffffff)
 651                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 652
 653         /* Final step - apply configuration changes */
 654         debug("Configuring STATICCFG\n");
 655         clrsetbits_le32(&sdr_ctrl->static_cfg,
 656                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 657                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 658
 659         sdram_set_protection_config(0, sdram_calculate_size());
 660
 661         sdram_dump_protection_config();
 662
 663         return status;
 664 }
 665
 666 /*
 667  * To calculate SDRAM device size based on SDRAM controller parameters.
 668  * Size is specified in bytes.
 669  *
 670  * NOTE:
 671  * This function is compiled and linked into the preloader and
 672  * Uboot (there may be others). So if this function changes, the Preloader
 673  * and UBoot must be updated simultaneously.
 674  */
 675 unsigned long sdram_calculate_size(void)
 676 {
 677         unsigned long temp;
 678         unsigned long row, bank, col, cs, width;
 679
 680         temp = readl(&sdr_ctrl->dram_addrw);
 681         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 682                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 683
 684         /* SDRAM Failure When Accessing Non-Existent Memory
 685          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 686          * since the FB specifies we modify ROWBITs to work around SDRAM
 687          * controller issue.
 688          *
 689          * If the stored handoff value for rows is 0, it probably means
 690          * the preloader is older than UBoot. Use the
 691          * #define from the SOCEDS Tools per Crucible review
 692          * uboot-socfpga-204. Note that this is not a supported
 693          * configuration and is not tested. The customer
 694          * should be using preloader and uboot built from the
 695          * same tag.
 696          */
 697         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 698         if (row == 0)
 699                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 700         /* If the stored handoff value for rows is greater than
 701          * the field width in the sdr.dramaddrw register then
 702          * something is very wrong. Revert to using the the #define
 703          * value handed off by the SOCEDS tool chain instead of
 704          * using a broken value.
 705          */
 706         if (row > 31)
 707                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 708
 709         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 710                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 711
 712         /* SDRAM Failure When Accessing Non-Existent Memory
 713          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 714          * since the FB specifies we modify CSBITs to work around SDRAM
 715          * controller issue.
 716          */
 717         cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 718               SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
 719         cs += 1;
 720
 721         cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 722
 723         width = readl(&sdr_ctrl->dram_if_width);
 724         /* ECC would not be calculated as its not addressible */
 725         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 726                 width = 32;
 727         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 728                 width = 16;
 729
 730         /* calculate the SDRAM size base on this info */
 731         temp = 1 << (row + bank + col);
 732         temp = temp * cs * (width  / 8);
 733
 734         debug("sdram_calculate_memory returns %ld\n", temp);
 735
 736         return temp;
 737 }