drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <div64.h>
   8 #include <watchdog.h>
   9 #include <asm/arch/fpga_manager.h>
  10 #include <asm/arch/sdram.h>
  11 #include <asm/arch/system_manager.h>
  12 #include <asm/io.h>
  13
  14 /*
  15  * FIXME: This path is temporary until the SDRAM driver gets
  16  *        a proper thorough cleanup.
  17  */
  18 #include "../../../board/altera/socfpga/qts/sdram_config.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct sdram_prot_rule {
  23         u64     sdram_start;    /* SDRAM start address */
  24         u64     sdram_end;      /* SDRAM end address */
  25         u32     rule;           /* SDRAM protection rule number: 0-19 */
  26         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  27
  28         u32     security;
  29         u32     portmask;
  30         u32     result;
  31         u32     lo_prot_id;
  32         u32     hi_prot_id;
  33 };
  34
  35 static struct socfpga_system_manager *sysmgr_regs =
  36         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  37 static struct socfpga_sdr_ctrl *sdr_ctrl =
  38         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  39
  40 /**
  41  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  42  *
  43  * SDRAM Failure happens when accessing non-existent memory. Artificially
  44  * increase the number of rows so that the memory controller thinks it has
  45  * 4GB of RAM. This function returns such amount of rows.
  46  */
  47 static int get_errata_rows(void)
  48 {
  49         /* Define constant for 4G memory - used for SDRAM errata workaround */
  50 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  51         const unsigned long long memsize = MEMSIZE_4G;
  52         const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
  53         const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
  54         const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
  55         const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
  56         const unsigned int width = 8;
  57
  58         unsigned long long newrows;
  59         int bits, inewrowslog2;
  60
  61         debug("workaround rows - memsize %lld\n", memsize);
  62         debug("workaround rows - cs        %d\n", cs);
  63         debug("workaround rows - width     %d\n", width);
  64         debug("workaround rows - rows      %d\n", rows);
  65         debug("workaround rows - banks     %d\n", banks);
  66         debug("workaround rows - cols      %d\n", cols);
  67
  68         newrows = lldiv(memsize, cs * (width / 8));
  69         debug("rows workaround - term1 %lld\n", newrows);
  70
  71         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  72         debug("rows workaround - term2 %lld\n", newrows);
  73
  74         /*
  75          * Compute the hamming weight - same as number of bits set.
  76          * Need to see if result is ordinal power of 2 before
  77          * attempting log2 of result.
  78          */
  79         bits = generic_hweight32(newrows);
  80
  81         debug("rows workaround - bits %d\n", bits);
  82
  83         if (bits != 1) {
  84                 printf("SDRAM workaround failed, bits set %d\n", bits);
  85                 return rows;
  86         }
  87
  88         if (newrows > UINT_MAX) {
  89                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  90                 return rows;
  91         }
  92
  93         inewrowslog2 = __ilog2(newrows);
  94
  95         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
  96
  97         if (inewrowslog2 == -1) {
  98                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
  99                 return rows;
 100         }
 101
 102         return inewrowslog2;
 103 }
 104
 105 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 106 static void sdram_set_rule(struct sdram_prot_rule *prule)
 107 {
 108         uint32_t lo_addr_bits;
 109         uint32_t hi_addr_bits;
 110         int ruleno = prule->rule;
 111
 112         /* Select the rule */
 113         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 114
 115         /* Obtain the address bits */
 116         lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
 117         hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
 118
 119         debug("sdram set rule start %x, %lld\n", lo_addr_bits,
 120               prule->sdram_start);
 121         debug("sdram set rule end   %x, %lld\n", hi_addr_bits,
 122               prule->sdram_end);
 123
 124         /* Set rule addresses */
 125         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 126
 127         /* Set rule protection ids */
 128         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 129                &sdr_ctrl->prot_rule_id);
 130
 131         /* Set the rule data */
 132         writel(prule->security | (prule->valid << 2) |
 133                (prule->portmask << 3) | (prule->result << 13),
 134                &sdr_ctrl->prot_rule_data);
 135
 136         /* write the rule */
 137         writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
 138
 139         /* Set rule number to 0 by default */
 140         writel(0, &sdr_ctrl->prot_rule_rdwr);
 141 }
 142
 143 static void sdram_get_rule(struct sdram_prot_rule *prule)
 144 {
 145         uint32_t addr;
 146         uint32_t id;
 147         uint32_t data;
 148         int ruleno = prule->rule;
 149
 150         /* Read the rule */
 151         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 152         writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
 153
 154         /* Get the addresses */
 155         addr = readl(&sdr_ctrl->prot_rule_addr);
 156         prule->sdram_start = (addr & 0xFFF) << 20;
 157         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 158
 159         /* Get the configured protection IDs */
 160         id = readl(&sdr_ctrl->prot_rule_id);
 161         prule->lo_prot_id = id & 0xFFF;
 162         prule->hi_prot_id = (id >> 12) & 0xFFF;
 163
 164         /* Get protection data */
 165         data = readl(&sdr_ctrl->prot_rule_data);
 166
 167         prule->security = data & 0x3;
 168         prule->valid = (data >> 2) & 0x1;
 169         prule->portmask = (data >> 3) & 0x3FF;
 170         prule->result = (data >> 13) & 0x1;
 171 }
 172
 173 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
 174 {
 175         struct sdram_prot_rule rule;
 176         int rules;
 177
 178         /* Start with accepting all SDRAM transaction */
 179         writel(0x0, &sdr_ctrl->protport_default);
 180
 181         /* Clear all protection rules for warm boot case */
 182         memset(&rule, 0, sizeof(struct sdram_prot_rule));
 183
 184         for (rules = 0; rules < 20; rules++) {
 185                 rule.rule = rules;
 186                 sdram_set_rule(&rule);
 187         }
 188
 189         /* new rule: accept SDRAM */
 190         rule.sdram_start = sdram_start;
 191         rule.sdram_end = sdram_end;
 192         rule.lo_prot_id = 0x0;
 193         rule.hi_prot_id = 0xFFF;
 194         rule.portmask = 0x3FF;
 195         rule.security = 0x3;
 196         rule.result = 0;
 197         rule.valid = 1;
 198         rule.rule = 0;
 199
 200         /* set new rule */
 201         sdram_set_rule(&rule);
 202
 203         /* default rule: reject everything */
 204         writel(0x3ff, &sdr_ctrl->protport_default);
 205 }
 206
 207 static void sdram_dump_protection_config(void)
 208 {
 209         struct sdram_prot_rule rule;
 210         int rules;
 211
 212         debug("SDRAM Prot rule, default %x\n",
 213               readl(&sdr_ctrl->protport_default));
 214
 215         for (rules = 0; rules < 20; rules++) {
 216                 sdram_get_rule(&rule);
 217                 debug("Rule %d, rules ...\n", rules);
 218                 debug("    sdram start %llx\n", rule.sdram_start);
 219                 debug("    sdram end   %llx\n", rule.sdram_end);
 220                 debug("    low prot id %d, hi prot id %d\n",
 221                       rule.lo_prot_id,
 222                       rule.hi_prot_id);
 223                 debug("    portmask %x\n", rule.portmask);
 224                 debug("    security %d\n", rule.security);
 225                 debug("    result %d\n", rule.result);
 226                 debug("    valid %d\n", rule.valid);
 227         }
 228 }
 229
 230 /* Function to write to register and verify the write */
 231 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
 232 {
 233 #ifndef SDRAM_MMR_SKIP_VERIFY
 234         unsigned reg_value1;
 235 #endif
 236         debug("   Write - Address ");
 237         debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
 238         /* Write to register */
 239         writel(reg_value, addr);
 240 #ifndef SDRAM_MMR_SKIP_VERIFY
 241         debug("   Read and verify...");
 242         /* Read back the wrote value */
 243         reg_value1 = readl(addr);
 244         /* Indicate failure if value not matched */
 245         if (reg_value1 != reg_value) {
 246                 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
 247                       (u32)addr, reg_value, reg_value1);
 248                 return 1;
 249         }
 250         debug("correct!\n");
 251 #endif  /* SDRAM_MMR_SKIP_VERIFY */
 252         return 0;
 253 }
 254
 255 static void set_sdr_ctrlcfg(void)
 256 {
 257         int addrorder;
 258
 259         debug("\nConfiguring CTRLCFG\n");
 260         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK,
 261                    CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
 262                    SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB);
 263         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK,
 264                    CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
 265                    SDR_CTRLGRP_CTRLCFG_MEMBL_LSB);
 266
 267
 268         /* SDRAM Failure When Accessing Non-Existent Memory
 269          * Set the addrorder field of the SDRAM control register
 270          * based on the CSBITs setting.
 271          */
 272         switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
 273         case 1:
 274                 addrorder = 0; /* chip, row, bank, column */
 275                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
 276                         debug("INFO: Changing address order to 0 (chip, row, \
 277                               bank, column)\n");
 278                 break;
 279         case 2:
 280                 addrorder = 2; /* row, chip, bank, column */
 281                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
 282                         debug("INFO: Changing address order to 2 (row, chip, \
 283                               bank, column)\n");
 284                 break;
 285         default:
 286                 addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
 287                 break;
 288         }
 289
 290         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK,
 291                         addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB);
 292
 293         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK,
 294                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
 295                         SDR_CTRLGRP_CTRLCFG_ECCEN_LSB);
 296
 297         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK,
 298                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
 299                         SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB);
 300
 301         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK,
 302                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
 303                         SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB);
 304
 305         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK,
 306                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
 307                         SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB);
 308
 309         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
 310                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
 311                         SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB);
 312
 313         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK,
 314                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
 315                         SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
 316 }
 317
 318 static void set_sdr_dram_timing1(void)
 319 {
 320         debug("Configuring DRAMTIMING1\n");
 321         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK,
 322                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
 323                         SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB);
 324
 325         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK,
 326                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
 327                         SDR_CTRLGRP_DRAMTIMING1_TAL_LSB);
 328
 329         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK,
 330                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
 331                         SDR_CTRLGRP_DRAMTIMING1_TCL_LSB);
 332
 333         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK,
 334                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
 335                         SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB);
 336
 337         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK,
 338                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
 339                         SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB);
 340
 341         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK,
 342                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
 343                         SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
 344 }
 345
 346 static void set_sdr_dram_timing2(void)
 347 {
 348         debug("Configuring DRAMTIMING2\n");
 349         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK,
 350                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
 351                         SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB);
 352
 353         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK,
 354                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
 355                         SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB);
 356
 357         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK,
 358                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
 359                         SDR_CTRLGRP_DRAMTIMING2_TRP_LSB);
 360
 361         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK,
 362                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
 363                         SDR_CTRLGRP_DRAMTIMING2_TWR_LSB);
 364
 365         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK,
 366                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
 367                         SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
 368 }
 369
 370 static void set_sdr_dram_timing3(void)
 371 {
 372         debug("Configuring DRAMTIMING3\n");
 373         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK,
 374                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
 375                         SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB);
 376
 377         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK,
 378                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
 379                         SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB);
 380
 381         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK,
 382                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
 383                         SDR_CTRLGRP_DRAMTIMING3_TRC_LSB);
 384
 385         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK,
 386                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
 387                         SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB);
 388
 389         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK,
 390                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
 391                         SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
 392 }
 393
 394 static void set_sdr_dram_timing4(void)
 395 {
 396         debug("Configuring DRAMTIMING4\n");
 397         clrsetbits_le32(&sdr_ctrl->dram_timing4,
 398                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK,
 399                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
 400                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB);
 401
 402         clrsetbits_le32(&sdr_ctrl->dram_timing4,
 403                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK,
 404                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
 405                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
 406 }
 407
 408 static void set_sdr_dram_lowpwr_timing(void)
 409 {
 410         debug("Configuring LOWPWRTIMING\n");
 411         clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
 412                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK,
 413                         CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
 414                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB);
 415
 416         clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
 417                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK,
 418                         CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
 419                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
 420 }
 421
 422 static void set_sdr_addr_rw(void)
 423 {
 424         int rows;
 425
 426         debug("Configuring DRAMADDRW\n");
 427         clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK,
 428                         CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
 429                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB);
 430         /*
 431          * SDRAM Failure When Accessing Non-Existent Memory
 432          * Update Preloader to artificially increase the number of rows so
 433          * that the memory thinks it has 4GB of RAM.
 434          */
 435         rows = get_errata_rows();
 436
 437         clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK,
 438                         rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 439
 440         clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK,
 441                         CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
 442                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB);
 443         /* SDRAM Failure When Accessing Non-Existent Memory
 444          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 445          * log2(number of chip select bits). Since there's only
 446          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 447          * which is the same as "chip selects" - 1.
 448          */
 449         clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK,
 450                         (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
 451                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
 452 }
 453
 454 static void set_sdr_static_cfg(void)
 455 {
 456         debug("Configuring STATICCFG\n");
 457         clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_MEMBL_MASK,
 458                         CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 459                         SDR_CTRLGRP_STATICCFG_MEMBL_LSB);
 460
 461         clrsetbits_le32(&sdr_ctrl->static_cfg,
 462                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK,
 463                         CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 464                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB);
 465 }
 466
 467 static void set_sdr_fifo_cfg(void)
 468 {
 469         debug("Configuring FIFOCFG\n");
 470         clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK,
 471                         CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 472                         SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB);
 473
 474         clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK,
 475                         CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 476                         SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB);
 477 }
 478
 479 static void set_sdr_mp_weight(void)
 480 {
 481         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 482         clrsetbits_le32(&sdr_ctrl->mp_weight0,
 483                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK,
 484                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 485                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
 486
 487         clrsetbits_le32(&sdr_ctrl->mp_weight1,
 488                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK,
 489                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 490                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB);
 491
 492         clrsetbits_le32(&sdr_ctrl->mp_weight1,
 493                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK,
 494                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 495                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
 496
 497         clrsetbits_le32(&sdr_ctrl->mp_weight2,
 498                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK,
 499                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 500                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
 501
 502         clrsetbits_le32(&sdr_ctrl->mp_weight3,
 503                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK,
 504                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 505                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
 506 }
 507
 508 static void set_sdr_mp_pacing(void)
 509 {
 510         debug("Configuring MPPACING_MPPACING_0\n");
 511         clrsetbits_le32(&sdr_ctrl->mp_pacing0,
 512                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
 513                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 514                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
 515
 516         clrsetbits_le32(&sdr_ctrl->mp_pacing1,
 517                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
 518                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 519                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
 520
 521         clrsetbits_le32(&sdr_ctrl->mp_pacing1,
 522                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
 523                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 524                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
 525
 526         clrsetbits_le32(&sdr_ctrl->mp_pacing2,
 527                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
 528                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 529                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
 530
 531         clrsetbits_le32(&sdr_ctrl->mp_pacing3,
 532                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
 533                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 534                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
 535 }
 536
 537 static void set_sdr_mp_threshold(void)
 538 {
 539         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 540         clrsetbits_le32(&sdr_ctrl->mp_threshold0,
 541                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
 542                         CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 543                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
 544
 545         clrsetbits_le32(&sdr_ctrl->mp_threshold1,
 546                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
 547                         CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 548                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
 549
 550         clrsetbits_le32(&sdr_ctrl->mp_threshold2,
 551                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
 552                         CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 553                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
 554 }
 555
 556
 557 /* Function to initialize SDRAM MMR */
 558 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
 559 {
 560         unsigned long reg_value;
 561         unsigned long status = 0;
 562
 563 #if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
 564 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
 565 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
 566 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
 567 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
 568
 569         writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
 570                &sysmgr_regs->iswgrp_handoff[4]);
 571 #endif
 572         set_sdr_ctrlcfg();
 573         set_sdr_dram_timing1();
 574         set_sdr_dram_timing2();
 575         set_sdr_dram_timing3();
 576         set_sdr_dram_timing4();
 577         set_sdr_dram_lowpwr_timing();
 578         set_sdr_addr_rw();
 579
 580         debug("Configuring DRAMIFWIDTH\n");
 581         clrsetbits_le32(&sdr_ctrl->dram_if_width,
 582                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK,
 583                         CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
 584                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB);
 585
 586         debug("Configuring DRAMDEVWIDTH\n");
 587         clrsetbits_le32(&sdr_ctrl->dram_dev_width,
 588                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK,
 589                         CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
 590                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB);
 591
 592         debug("Configuring LOWPWREQ\n");
 593         clrsetbits_le32(&sdr_ctrl->lowpwr_eq,
 594                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK,
 595                         CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 596                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB);
 597
 598         debug("Configuring DRAMINTR\n");
 599         clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK,
 600                         CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 601                         SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
 602
 603         set_sdr_static_cfg();
 604
 605         debug("Configuring CTRLWIDTH\n");
 606         clrsetbits_le32(&sdr_ctrl->ctrl_width,
 607                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK,
 608                         CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 609                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB);
 610
 611         debug("Configuring PORTCFG\n");
 612         clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK,
 613                         CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 614                         SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
 615
 616         set_sdr_fifo_cfg();
 617
 618         debug("Configuring MPPRIORITY\n");
 619         clrsetbits_le32(&sdr_ctrl->mp_priority,
 620                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK,
 621                         CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 622                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
 623
 624         set_sdr_mp_weight();
 625         set_sdr_mp_pacing();
 626         set_sdr_mp_threshold();
 627
 628         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 629         setbits_le32(&sdr_ctrl->phy_ctrl0,
 630                      CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0);
 631
 632         debug("Configuring CPORTWIDTH\n");
 633         clrsetbits_le32(&sdr_ctrl->cport_width,
 634                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK,
 635                         CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 636                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB);
 637         debug("   Write - Address ");
 638         debug("0x%08x Data 0x%08x\n",
 639                 (unsigned)(&sdr_ctrl->cport_width),
 640                 (unsigned)reg_value);
 641         reg_value = readl(&sdr_ctrl->cport_width);
 642         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 643
 644         debug("Configuring CPORTWMAP\n");
 645         clrsetbits_le32(&sdr_ctrl->cport_wmap,
 646                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK,
 647                         CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 648                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB);
 649         debug("   Write - Address ");
 650         debug("0x%08x Data 0x%08x\n",
 651                 (unsigned)(&sdr_ctrl->cport_wmap),
 652                 (unsigned)reg_value);
 653         reg_value = readl(&sdr_ctrl->cport_wmap);
 654         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 655
 656         debug("Configuring CPORTRMAP\n");
 657         clrsetbits_le32(&sdr_ctrl->cport_rmap,
 658                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK,
 659                         CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 660                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB);
 661         debug("   Write - Address ");
 662         debug("0x%08x Data 0x%08x\n",
 663                 (unsigned)(&sdr_ctrl->cport_rmap),
 664                 (unsigned)reg_value);
 665         reg_value = readl(&sdr_ctrl->cport_rmap);
 666         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 667
 668         debug("Configuring RFIFOCMAP\n");
 669         clrsetbits_le32(&sdr_ctrl->rfifo_cmap,
 670                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK,
 671                         CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 672                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB);
 673         debug("   Write - Address ");
 674         debug("0x%08x Data 0x%08x\n",
 675                 (unsigned)(&sdr_ctrl->rfifo_cmap),
 676                 (unsigned)reg_value);
 677         reg_value = readl(&sdr_ctrl->rfifo_cmap);
 678         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 679
 680         debug("Configuring WFIFOCMAP\n");
 681         reg_value = readl(&sdr_ctrl->wfifo_cmap);
 682         clrsetbits_le32(&sdr_ctrl->wfifo_cmap,
 683                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK,
 684                         CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 685                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB);
 686         debug("   Write - Address ");
 687         debug("0x%08x Data 0x%08x\n",
 688                 (unsigned)(&sdr_ctrl->wfifo_cmap),
 689                 (unsigned)reg_value);
 690         reg_value = readl(&sdr_ctrl->wfifo_cmap);
 691         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 692
 693         debug("Configuring CPORTRDWR\n");
 694         clrsetbits_le32(&sdr_ctrl->cport_rdwr,
 695                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK,
 696                         CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 697                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB);
 698         debug("   Write - Address ");
 699         debug("0x%08x Data 0x%08x\n",
 700                 (unsigned)(&sdr_ctrl->cport_rdwr),
 701                 (unsigned)reg_value);
 702         reg_value = readl(&sdr_ctrl->cport_rdwr);
 703         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 704
 705         debug("Configuring DRAMODT\n");
 706         clrsetbits_le32(&sdr_ctrl->dram_odt,
 707                         SDR_CTRLGRP_DRAMODT_READ_MASK,
 708                         CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
 709                         SDR_CTRLGRP_DRAMODT_READ_LSB);
 710
 711         clrsetbits_le32(&sdr_ctrl->dram_odt,
 712                         SDR_CTRLGRP_DRAMODT_WRITE_MASK,
 713                         CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
 714                         SDR_CTRLGRP_DRAMODT_WRITE_LSB);
 715
 716         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 717         writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 718                &sysmgr_regs->iswgrp_handoff[3]);
 719
 720         /* only enable if the FPGA is programmed */
 721         if (fpgamgr_test_fpga_ready()) {
 722                 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 723                     CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) {
 724                         status = 1;
 725                         return 1;
 726                 }
 727         }
 728
 729         /* Restore the SDR PHY Register if valid */
 730         if (sdr_phy_reg != 0xffffffff)
 731                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 732
 733 /***** Final step - apply configuration changes *****/
 734         debug("Configuring STATICCFG_\n");
 735         clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 736                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 737         debug("   Write - Address ");
 738         debug("0x%08x Data 0x%08x\n",
 739                 (unsigned)(&sdr_ctrl->static_cfg),
 740                 (unsigned)reg_value);
 741         reg_value = readl(&sdr_ctrl->static_cfg);
 742         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 743
 744         sdram_set_protection_config(0, sdram_calculate_size());
 745
 746         sdram_dump_protection_config();
 747
 748         return status;
 749 }
 750
 751 /*
 752  * To calculate SDRAM device size based on SDRAM controller parameters.
 753  * Size is specified in bytes.
 754  *
 755  * NOTE:
 756  * This function is compiled and linked into the preloader and
 757  * Uboot (there may be others). So if this function changes, the Preloader
 758  * and UBoot must be updated simultaneously.
 759  */
 760 unsigned long sdram_calculate_size(void)
 761 {
 762         unsigned long temp;
 763         unsigned long row, bank, col, cs, width;
 764
 765         temp = readl(&sdr_ctrl->dram_addrw);
 766         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 767                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 768
 769         /* SDRAM Failure When Accessing Non-Existent Memory
 770          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 771          * since the FB specifies we modify ROWBITs to work around SDRAM
 772          * controller issue.
 773          *
 774          * If the stored handoff value for rows is 0, it probably means
 775          * the preloader is older than UBoot. Use the
 776          * #define from the SOCEDS Tools per Crucible review
 777          * uboot-socfpga-204. Note that this is not a supported
 778          * configuration and is not tested. The customer
 779          * should be using preloader and uboot built from the
 780          * same tag.
 781          */
 782         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 783         if (row == 0)
 784                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 785         /* If the stored handoff value for rows is greater than
 786          * the field width in the sdr.dramaddrw register then
 787          * something is very wrong. Revert to using the the #define
 788          * value handed off by the SOCEDS tool chain instead of
 789          * using a broken value.
 790          */
 791         if (row > 31)
 792                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 793
 794         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 795                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 796
 797         /* SDRAM Failure When Accessing Non-Existent Memory
 798          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 799          * since the FB specifies we modify CSBITs to work around SDRAM
 800          * controller issue.
 801          */
 802         cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 803               SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
 804         cs += 1;
 805
 806         cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 807
 808         width = readl(&sdr_ctrl->dram_if_width);
 809         /* ECC would not be calculated as its not addressible */
 810         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 811                 width = 32;
 812         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 813                 width = 16;
 814
 815         /* calculate the SDRAM size base on this info */
 816         temp = 1 << (row + bank + col);
 817         temp = temp * cs * (width  / 8);
 818
 819         debug("sdram_calculate_memory returns %ld\n", temp);
 820
 821         return temp;
 822 }