drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <div64.h>
   8 #include <watchdog.h>
   9 #include <asm/arch/fpga_manager.h>
  10 #include <asm/arch/sdram.h>
  11 #include <asm/arch/system_manager.h>
  12 #include <asm/io.h>
  13
  14 /*
  15  * FIXME: This path is temporary until the SDRAM driver gets
  16  *        a proper thorough cleanup.
  17  */
  18 #include "../../../board/altera/socfpga/qts/sdram_config.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct sdram_prot_rule {
  23         u64     sdram_start;    /* SDRAM start address */
  24         u64     sdram_end;      /* SDRAM end address */
  25         u32     rule;           /* SDRAM protection rule number: 0-19 */
  26         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  27
  28         u32     security;
  29         u32     portmask;
  30         u32     result;
  31         u32     lo_prot_id;
  32         u32     hi_prot_id;
  33 };
  34
  35 static struct socfpga_system_manager *sysmgr_regs =
  36         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  37 static struct socfpga_sdr_ctrl *sdr_ctrl =
  38         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  39
  40 /**
  41  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  42  *
  43  * SDRAM Failure happens when accessing non-existent memory. Artificially
  44  * increase the number of rows so that the memory controller thinks it has
  45  * 4GB of RAM. This function returns such amount of rows.
  46  */
  47 static int get_errata_rows(void)
  48 {
  49         /* Define constant for 4G memory - used for SDRAM errata workaround */
  50 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  51         const unsigned long long memsize = MEMSIZE_4G;
  52         const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
  53         const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
  54         const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
  55         const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
  56         const unsigned int width = 8;
  57
  58         unsigned long long newrows;
  59         int bits, inewrowslog2;
  60
  61         debug("workaround rows - memsize %lld\n", memsize);
  62         debug("workaround rows - cs        %d\n", cs);
  63         debug("workaround rows - width     %d\n", width);
  64         debug("workaround rows - rows      %d\n", rows);
  65         debug("workaround rows - banks     %d\n", banks);
  66         debug("workaround rows - cols      %d\n", cols);
  67
  68         newrows = lldiv(memsize, cs * (width / 8));
  69         debug("rows workaround - term1 %lld\n", newrows);
  70
  71         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  72         debug("rows workaround - term2 %lld\n", newrows);
  73
  74         /*
  75          * Compute the hamming weight - same as number of bits set.
  76          * Need to see if result is ordinal power of 2 before
  77          * attempting log2 of result.
  78          */
  79         bits = generic_hweight32(newrows);
  80
  81         debug("rows workaround - bits %d\n", bits);
  82
  83         if (bits != 1) {
  84                 printf("SDRAM workaround failed, bits set %d\n", bits);
  85                 return rows;
  86         }
  87
  88         if (newrows > UINT_MAX) {
  89                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  90                 return rows;
  91         }
  92
  93         inewrowslog2 = __ilog2(newrows);
  94
  95         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
  96
  97         if (inewrowslog2 == -1) {
  98                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
  99                 return rows;
 100         }
 101
 102         return inewrowslog2;
 103 }
 104
 105 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 106 static void sdram_set_rule(struct sdram_prot_rule *prule)
 107 {
 108         uint32_t lo_addr_bits;
 109         uint32_t hi_addr_bits;
 110         int ruleno = prule->rule;
 111
 112         /* Select the rule */
 113         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 114
 115         /* Obtain the address bits */
 116         lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
 117         hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
 118
 119         debug("sdram set rule start %x, %lld\n", lo_addr_bits,
 120               prule->sdram_start);
 121         debug("sdram set rule end   %x, %lld\n", hi_addr_bits,
 122               prule->sdram_end);
 123
 124         /* Set rule addresses */
 125         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 126
 127         /* Set rule protection ids */
 128         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 129                &sdr_ctrl->prot_rule_id);
 130
 131         /* Set the rule data */
 132         writel(prule->security | (prule->valid << 2) |
 133                (prule->portmask << 3) | (prule->result << 13),
 134                &sdr_ctrl->prot_rule_data);
 135
 136         /* write the rule */
 137         writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
 138
 139         /* Set rule number to 0 by default */
 140         writel(0, &sdr_ctrl->prot_rule_rdwr);
 141 }
 142
 143 static void sdram_get_rule(struct sdram_prot_rule *prule)
 144 {
 145         uint32_t addr;
 146         uint32_t id;
 147         uint32_t data;
 148         int ruleno = prule->rule;
 149
 150         /* Read the rule */
 151         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 152         writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
 153
 154         /* Get the addresses */
 155         addr = readl(&sdr_ctrl->prot_rule_addr);
 156         prule->sdram_start = (addr & 0xFFF) << 20;
 157         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 158
 159         /* Get the configured protection IDs */
 160         id = readl(&sdr_ctrl->prot_rule_id);
 161         prule->lo_prot_id = id & 0xFFF;
 162         prule->hi_prot_id = (id >> 12) & 0xFFF;
 163
 164         /* Get protection data */
 165         data = readl(&sdr_ctrl->prot_rule_data);
 166
 167         prule->security = data & 0x3;
 168         prule->valid = (data >> 2) & 0x1;
 169         prule->portmask = (data >> 3) & 0x3FF;
 170         prule->result = (data >> 13) & 0x1;
 171 }
 172
 173 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
 174 {
 175         struct sdram_prot_rule rule;
 176         int rules;
 177
 178         /* Start with accepting all SDRAM transaction */
 179         writel(0x0, &sdr_ctrl->protport_default);
 180
 181         /* Clear all protection rules for warm boot case */
 182         memset(&rule, 0, sizeof(struct sdram_prot_rule));
 183
 184         for (rules = 0; rules < 20; rules++) {
 185                 rule.rule = rules;
 186                 sdram_set_rule(&rule);
 187         }
 188
 189         /* new rule: accept SDRAM */
 190         rule.sdram_start = sdram_start;
 191         rule.sdram_end = sdram_end;
 192         rule.lo_prot_id = 0x0;
 193         rule.hi_prot_id = 0xFFF;
 194         rule.portmask = 0x3FF;
 195         rule.security = 0x3;
 196         rule.result = 0;
 197         rule.valid = 1;
 198         rule.rule = 0;
 199
 200         /* set new rule */
 201         sdram_set_rule(&rule);
 202
 203         /* default rule: reject everything */
 204         writel(0x3ff, &sdr_ctrl->protport_default);
 205 }
 206
 207 static void sdram_dump_protection_config(void)
 208 {
 209         struct sdram_prot_rule rule;
 210         int rules;
 211
 212         debug("SDRAM Prot rule, default %x\n",
 213               readl(&sdr_ctrl->protport_default));
 214
 215         for (rules = 0; rules < 20; rules++) {
 216                 sdram_get_rule(&rule);
 217                 debug("Rule %d, rules ...\n", rules);
 218                 debug("    sdram start %llx\n", rule.sdram_start);
 219                 debug("    sdram end   %llx\n", rule.sdram_end);
 220                 debug("    low prot id %d, hi prot id %d\n",
 221                       rule.lo_prot_id,
 222                       rule.hi_prot_id);
 223                 debug("    portmask %x\n", rule.portmask);
 224                 debug("    security %d\n", rule.security);
 225                 debug("    result %d\n", rule.result);
 226                 debug("    valid %d\n", rule.valid);
 227         }
 228 }
 229
 230 /* Function to write to register and verify the write */
 231 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
 232 {
 233 #ifndef SDRAM_MMR_SKIP_VERIFY
 234         unsigned reg_value1;
 235 #endif
 236         debug("   Write - Address ");
 237         debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
 238         /* Write to register */
 239         writel(reg_value, addr);
 240 #ifndef SDRAM_MMR_SKIP_VERIFY
 241         debug("   Read and verify...");
 242         /* Read back the wrote value */
 243         reg_value1 = readl(addr);
 244         /* Indicate failure if value not matched */
 245         if (reg_value1 != reg_value) {
 246                 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
 247                       (u32)addr, reg_value, reg_value1);
 248                 return 1;
 249         }
 250         debug("correct!\n");
 251 #endif  /* SDRAM_MMR_SKIP_VERIFY */
 252         return 0;
 253 }
 254
 255 static void set_sdr_ctrlcfg(void)
 256 {
 257         u32 addrorder;
 258         u32 ctrl_cfg =
 259                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
 260                         SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)        |
 261                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
 262                         SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)          |
 263                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
 264                         SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)          |
 265                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
 266                         SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)      |
 267                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
 268                         SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)      |
 269                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
 270                         SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)    |
 271                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
 272                         SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)       |
 273                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
 274                         SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
 275
 276         debug("\nConfiguring CTRLCFG\n");
 277
 278         /*
 279          * SDRAM Failure When Accessing Non-Existent Memory
 280          * Set the addrorder field of the SDRAM control register
 281          * based on the CSBITs setting.
 282          */
 283         switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
 284         case 1:
 285                 addrorder = 0; /* chip, row, bank, column */
 286                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
 287                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 288                 break;
 289         case 2:
 290                 addrorder = 2; /* row, chip, bank, column */
 291                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
 292                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 293                 break;
 294         default:
 295                 addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
 296                 break;
 297         }
 298
 299         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 300
 301         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 302 }
 303
 304 static void set_sdr_dram_timing(void)
 305 {
 306         const u32 dram_timing1 =
 307                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
 308                         SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)       |
 309                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
 310                         SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)        |
 311                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
 312                         SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)        |
 313                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
 314                         SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)       |
 315                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
 316                         SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)       |
 317                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
 318                         SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
 319
 320         const u32 dram_timing2 =
 321                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
 322                         SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)      |
 323                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
 324                         SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)       |
 325                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
 326                         SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)        |
 327                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
 328                         SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)        |
 329                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
 330                         SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
 331
 332         const u32 dram_timing3 =
 333                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
 334                         SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)       |
 335                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
 336                         SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)       |
 337                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
 338                         SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)        |
 339                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
 340                         SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)       |
 341                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
 342                         SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
 343
 344         const u32 dram_timing4 =
 345                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
 346                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)       |
 347                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
 348                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
 349
 350         const u32 lowpwr_timing =
 351                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
 352                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)      |
 353                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
 354                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
 355
 356         debug("Configuring DRAMTIMING1\n");
 357         writel(dram_timing1, &sdr_ctrl->dram_timing1);
 358
 359         debug("Configuring DRAMTIMING2\n");
 360         writel(dram_timing2, &sdr_ctrl->dram_timing2);
 361
 362         debug("Configuring DRAMTIMING3\n");
 363         writel(dram_timing3, &sdr_ctrl->dram_timing3);
 364
 365         debug("Configuring DRAMTIMING4\n");
 366         writel(dram_timing4, &sdr_ctrl->dram_timing4);
 367
 368         debug("Configuring LOWPWRTIMING\n");
 369         writel(lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 370 }
 371
 372 static void set_sdr_addr_rw(void)
 373 {
 374         /*
 375          * SDRAM Failure When Accessing Non-Existent Memory
 376          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 377          * log2(number of chip select bits). Since there's only
 378          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 379          * which is the same as "chip selects" - 1.
 380          */
 381         const int rows = get_errata_rows();
 382         const u32 dram_addrw =
 383                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
 384                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)      |
 385                 (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)     |
 386                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
 387                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)     |
 388                 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
 389                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
 390         debug("Configuring DRAMADDRW\n");
 391         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 392 }
 393
 394 static void set_sdr_static_cfg(void)
 395 {
 396         const u32 static_cfg =
 397                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 398                         SDR_CTRLGRP_STATICCFG_MEMBL_LSB)        |
 399                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 400                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB);
 401
 402         debug("Configuring STATICCFG\n");
 403         writel(static_cfg, &sdr_ctrl->static_cfg);
 404 }
 405
 406 static void set_sdr_fifo_cfg(void)
 407 {
 408         const u32 fifo_cfg =
 409                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 410                         SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)       |
 411                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 412                         SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB);
 413
 414         debug("Configuring FIFOCFG\n");
 415         writel(fifo_cfg, &sdr_ctrl->fifo_cfg);
 416 }
 417
 418 static void set_sdr_mp_weight(void)
 419 {
 420         const u32 mp_weight0 =
 421                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 422                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
 423         const u32 mp_weight1 =
 424                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 425                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
 426                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 427                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
 428         const u32 mp_weight2 =
 429                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 430                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
 431         const u32 mp_weight3 =
 432                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 433                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
 434
 435         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 436         writel(mp_weight0, &sdr_ctrl->mp_weight0);
 437         writel(mp_weight1, &sdr_ctrl->mp_weight1);
 438         writel(mp_weight2, &sdr_ctrl->mp_weight2);
 439         writel(mp_weight3, &sdr_ctrl->mp_weight3);
 440 }
 441
 442 static void set_sdr_mp_pacing(void)
 443 {
 444         debug("Configuring MPPACING_MPPACING_0\n");
 445         clrsetbits_le32(&sdr_ctrl->mp_pacing0,
 446                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
 447                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 448                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
 449
 450         clrsetbits_le32(&sdr_ctrl->mp_pacing1,
 451                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
 452                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 453                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
 454
 455         clrsetbits_le32(&sdr_ctrl->mp_pacing1,
 456                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
 457                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 458                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
 459
 460         clrsetbits_le32(&sdr_ctrl->mp_pacing2,
 461                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
 462                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 463                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
 464
 465         clrsetbits_le32(&sdr_ctrl->mp_pacing3,
 466                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
 467                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 468                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
 469 }
 470
 471 static void set_sdr_mp_threshold(void)
 472 {
 473         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 474         clrsetbits_le32(&sdr_ctrl->mp_threshold0,
 475                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
 476                         CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 477                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
 478
 479         clrsetbits_le32(&sdr_ctrl->mp_threshold1,
 480                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
 481                         CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 482                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
 483
 484         clrsetbits_le32(&sdr_ctrl->mp_threshold2,
 485                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
 486                         CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 487                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
 488 }
 489
 490
 491 /* Function to initialize SDRAM MMR */
 492 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
 493 {
 494         unsigned long reg_value;
 495         unsigned long status = 0;
 496
 497 #if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
 498 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
 499 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
 500 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
 501 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
 502
 503         writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
 504                &sysmgr_regs->iswgrp_handoff[4]);
 505 #endif
 506         set_sdr_ctrlcfg();
 507         set_sdr_dram_timing();
 508         set_sdr_addr_rw();
 509
 510         debug("Configuring DRAMIFWIDTH\n");
 511         clrsetbits_le32(&sdr_ctrl->dram_if_width,
 512                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK,
 513                         CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
 514                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB);
 515
 516         debug("Configuring DRAMDEVWIDTH\n");
 517         clrsetbits_le32(&sdr_ctrl->dram_dev_width,
 518                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK,
 519                         CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
 520                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB);
 521
 522         debug("Configuring LOWPWREQ\n");
 523         clrsetbits_le32(&sdr_ctrl->lowpwr_eq,
 524                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK,
 525                         CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 526                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB);
 527
 528         debug("Configuring DRAMINTR\n");
 529         clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK,
 530                         CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 531                         SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
 532
 533         set_sdr_static_cfg();
 534
 535         debug("Configuring CTRLWIDTH\n");
 536         clrsetbits_le32(&sdr_ctrl->ctrl_width,
 537                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK,
 538                         CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 539                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB);
 540
 541         debug("Configuring PORTCFG\n");
 542         clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK,
 543                         CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 544                         SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
 545
 546         set_sdr_fifo_cfg();
 547
 548         debug("Configuring MPPRIORITY\n");
 549         clrsetbits_le32(&sdr_ctrl->mp_priority,
 550                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK,
 551                         CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 552                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
 553
 554         set_sdr_mp_weight();
 555         set_sdr_mp_pacing();
 556         set_sdr_mp_threshold();
 557
 558         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 559         setbits_le32(&sdr_ctrl->phy_ctrl0,
 560                      CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0);
 561
 562         debug("Configuring CPORTWIDTH\n");
 563         clrsetbits_le32(&sdr_ctrl->cport_width,
 564                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK,
 565                         CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 566                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB);
 567         debug("   Write - Address ");
 568         debug("0x%08x Data 0x%08x\n",
 569                 (unsigned)(&sdr_ctrl->cport_width),
 570                 (unsigned)reg_value);
 571         reg_value = readl(&sdr_ctrl->cport_width);
 572         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 573
 574         debug("Configuring CPORTWMAP\n");
 575         clrsetbits_le32(&sdr_ctrl->cport_wmap,
 576                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK,
 577                         CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 578                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB);
 579         debug("   Write - Address ");
 580         debug("0x%08x Data 0x%08x\n",
 581                 (unsigned)(&sdr_ctrl->cport_wmap),
 582                 (unsigned)reg_value);
 583         reg_value = readl(&sdr_ctrl->cport_wmap);
 584         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 585
 586         debug("Configuring CPORTRMAP\n");
 587         clrsetbits_le32(&sdr_ctrl->cport_rmap,
 588                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK,
 589                         CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 590                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB);
 591         debug("   Write - Address ");
 592         debug("0x%08x Data 0x%08x\n",
 593                 (unsigned)(&sdr_ctrl->cport_rmap),
 594                 (unsigned)reg_value);
 595         reg_value = readl(&sdr_ctrl->cport_rmap);
 596         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 597
 598         debug("Configuring RFIFOCMAP\n");
 599         clrsetbits_le32(&sdr_ctrl->rfifo_cmap,
 600                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK,
 601                         CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 602                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB);
 603         debug("   Write - Address ");
 604         debug("0x%08x Data 0x%08x\n",
 605                 (unsigned)(&sdr_ctrl->rfifo_cmap),
 606                 (unsigned)reg_value);
 607         reg_value = readl(&sdr_ctrl->rfifo_cmap);
 608         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 609
 610         debug("Configuring WFIFOCMAP\n");
 611         reg_value = readl(&sdr_ctrl->wfifo_cmap);
 612         clrsetbits_le32(&sdr_ctrl->wfifo_cmap,
 613                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK,
 614                         CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 615                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB);
 616         debug("   Write - Address ");
 617         debug("0x%08x Data 0x%08x\n",
 618                 (unsigned)(&sdr_ctrl->wfifo_cmap),
 619                 (unsigned)reg_value);
 620         reg_value = readl(&sdr_ctrl->wfifo_cmap);
 621         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 622
 623         debug("Configuring CPORTRDWR\n");
 624         clrsetbits_le32(&sdr_ctrl->cport_rdwr,
 625                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK,
 626                         CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 627                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB);
 628         debug("   Write - Address ");
 629         debug("0x%08x Data 0x%08x\n",
 630                 (unsigned)(&sdr_ctrl->cport_rdwr),
 631                 (unsigned)reg_value);
 632         reg_value = readl(&sdr_ctrl->cport_rdwr);
 633         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 634
 635         debug("Configuring DRAMODT\n");
 636         clrsetbits_le32(&sdr_ctrl->dram_odt,
 637                         SDR_CTRLGRP_DRAMODT_READ_MASK,
 638                         CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
 639                         SDR_CTRLGRP_DRAMODT_READ_LSB);
 640
 641         clrsetbits_le32(&sdr_ctrl->dram_odt,
 642                         SDR_CTRLGRP_DRAMODT_WRITE_MASK,
 643                         CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
 644                         SDR_CTRLGRP_DRAMODT_WRITE_LSB);
 645
 646         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 647         writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 648                &sysmgr_regs->iswgrp_handoff[3]);
 649
 650         /* only enable if the FPGA is programmed */
 651         if (fpgamgr_test_fpga_ready()) {
 652                 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 653                     CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) {
 654                         status = 1;
 655                         return 1;
 656                 }
 657         }
 658
 659         /* Restore the SDR PHY Register if valid */
 660         if (sdr_phy_reg != 0xffffffff)
 661                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 662
 663 /***** Final step - apply configuration changes *****/
 664         debug("Configuring STATICCFG_\n");
 665         clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 666                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 667         debug("   Write - Address ");
 668         debug("0x%08x Data 0x%08x\n",
 669                 (unsigned)(&sdr_ctrl->static_cfg),
 670                 (unsigned)reg_value);
 671         reg_value = readl(&sdr_ctrl->static_cfg);
 672         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 673
 674         sdram_set_protection_config(0, sdram_calculate_size());
 675
 676         sdram_dump_protection_config();
 677
 678         return status;
 679 }
 680
 681 /*
 682  * To calculate SDRAM device size based on SDRAM controller parameters.
 683  * Size is specified in bytes.
 684  *
 685  * NOTE:
 686  * This function is compiled and linked into the preloader and
 687  * Uboot (there may be others). So if this function changes, the Preloader
 688  * and UBoot must be updated simultaneously.
 689  */
 690 unsigned long sdram_calculate_size(void)
 691 {
 692         unsigned long temp;
 693         unsigned long row, bank, col, cs, width;
 694
 695         temp = readl(&sdr_ctrl->dram_addrw);
 696         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 697                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 698
 699         /* SDRAM Failure When Accessing Non-Existent Memory
 700          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 701          * since the FB specifies we modify ROWBITs to work around SDRAM
 702          * controller issue.
 703          *
 704          * If the stored handoff value for rows is 0, it probably means
 705          * the preloader is older than UBoot. Use the
 706          * #define from the SOCEDS Tools per Crucible review
 707          * uboot-socfpga-204. Note that this is not a supported
 708          * configuration and is not tested. The customer
 709          * should be using preloader and uboot built from the
 710          * same tag.
 711          */
 712         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 713         if (row == 0)
 714                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 715         /* If the stored handoff value for rows is greater than
 716          * the field width in the sdr.dramaddrw register then
 717          * something is very wrong. Revert to using the the #define
 718          * value handed off by the SOCEDS tool chain instead of
 719          * using a broken value.
 720          */
 721         if (row > 31)
 722                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 723
 724         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 725                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 726
 727         /* SDRAM Failure When Accessing Non-Existent Memory
 728          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 729          * since the FB specifies we modify CSBITs to work around SDRAM
 730          * controller issue.
 731          */
 732         cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 733               SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
 734         cs += 1;
 735
 736         cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 737
 738         width = readl(&sdr_ctrl->dram_if_width);
 739         /* ECC would not be calculated as its not addressible */
 740         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 741                 width = 32;
 742         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 743                 width = 16;
 744
 745         /* calculate the SDRAM size base on this info */
 746         temp = 1 << (row + bank + col);
 747         temp = temp * cs * (width  / 8);
 748
 749         debug("sdram_calculate_memory returns %ld\n", temp);
 750
 751         return temp;
 752 }