drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /*
1040  * performs a guaranteed read on the patterns we are going to use during a
1041  * read test to ensure memory works
1042  */
1043 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1044         uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1045         uint32_t all_ranks)
1046 {
1047         uint32_t r, vg;
1048         uint32_t correct_mask_vg;
1049         uint32_t tmp_bit_chk;
1050         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1051                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1052         uint32_t addr;
1053         uint32_t base_rw_mgr;
1054
1055         *bit_chk = param->read_correct_mask;
1056         correct_mask_vg = param->read_correct_mask_vg;
1057
1058         for (r = rank_bgn; r < rank_end; r++) {
1059                 if (param->skip_ranks[r])
1060                         /* request to skip the rank */
1061                         continue;
1062
1063                 /* set rank */
1064                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1065
1066                 /* Load up a constant bursts of read commands */
1067                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1068                 writel(RW_MGR_GUARANTEED_READ,
1069                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1070
1071                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1072                 writel(RW_MGR_GUARANTEED_READ_CONT,
1073                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1074
1075                 tmp_bit_chk = 0;
1076                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1077                         /* reset the fifos to get pointers to known state */
1078
1079                         writel(0, &phy_mgr_cmd->fifo_reset);
1080                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1081                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1082
1083                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1084                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1085
1086                         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1087                         writel(RW_MGR_GUARANTEED_READ, addr +
1088                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1089                                 vg) << 2));
1090
1091                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1092                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1093
1094                         if (vg == 0)
1095                                 break;
1096                 }
1097                 *bit_chk &= tmp_bit_chk;
1098         }
1099
1100         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1101         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1102
1103         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1104         debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1105                    %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1106                    (long unsigned int)(*bit_chk == param->read_correct_mask));
1107         return *bit_chk == param->read_correct_mask;
1108 }
1109
1110 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1111         (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1112 {
1113         return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1114                 num_tries, bit_chk, 1);
1115 }
1116
1117 /**
1118  * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1119  * @rank_bgn:   Rank number
1120  * @all_ranks:  Test all ranks
1121  *
1122  * Load up the patterns we are going to use during a read test.
1123  */
1124 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1125                                                     const int all_ranks)
1126 {
1127         const u32 rank_end = all_ranks ?
1128                         RW_MGR_MEM_NUMBER_OF_RANKS :
1129                         (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1130         u32 r;
1131
1132         debug("%s:%d\n", __func__, __LINE__);
1133
1134         for (r = rank_bgn; r < rank_end; r++) {
1135                 if (param->skip_ranks[r])
1136                         /* request to skip the rank */
1137                         continue;
1138
1139                 /* set rank */
1140                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1141
1142                 /* Load up a constant bursts */
1143                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1144
1145                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1146                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1147
1148                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1149
1150                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1151                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1152
1153                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1154
1155                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1156                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1157
1158                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1159
1160                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1161                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1162
1163                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1164                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1165         }
1166
1167         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1168 }
1169
1170 /*
1171  * try a read and see if it returns correct data back. has dummy reads
1172  * inserted into the mix used to align dqs enable. has more thorough checks
1173  * than the regular read test.
1174  */
1175 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1176         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1177         uint32_t all_groups, uint32_t all_ranks)
1178 {
1179         uint32_t r, vg;
1180         uint32_t correct_mask_vg;
1181         uint32_t tmp_bit_chk;
1182         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1183                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1184         uint32_t addr;
1185         uint32_t base_rw_mgr;
1186
1187         *bit_chk = param->read_correct_mask;
1188         correct_mask_vg = param->read_correct_mask_vg;
1189
1190         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1191                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1192
1193         for (r = rank_bgn; r < rank_end; r++) {
1194                 if (param->skip_ranks[r])
1195                         /* request to skip the rank */
1196                         continue;
1197
1198                 /* set rank */
1199                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1200
1201                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1202
1203                 writel(RW_MGR_READ_B2B_WAIT1,
1204                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1205
1206                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1207                 writel(RW_MGR_READ_B2B_WAIT2,
1208                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1209
1210                 if (quick_read_mode)
1211                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1212                         /* need at least two (1+1) reads to capture failures */
1213                 else if (all_groups)
1214                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1215                 else
1216                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1217
1218                 writel(RW_MGR_READ_B2B,
1219                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1220                 if (all_groups)
1221                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1222                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1223                                &sdr_rw_load_mgr_regs->load_cntr3);
1224                 else
1225                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1226
1227                 writel(RW_MGR_READ_B2B,
1228                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1229
1230                 tmp_bit_chk = 0;
1231                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1232                         /* reset the fifos to get pointers to known state */
1233                         writel(0, &phy_mgr_cmd->fifo_reset);
1234                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1235                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1236
1237                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1238                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1239
1240                         if (all_groups)
1241                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1242                         else
1243                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1244
1245                         writel(RW_MGR_READ_B2B, addr +
1246                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1247                                vg) << 2));
1248
1249                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1250                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1251
1252                         if (vg == 0)
1253                                 break;
1254                 }
1255                 *bit_chk &= tmp_bit_chk;
1256         }
1257
1258         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1259         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1260
1261         if (all_correct) {
1262                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1263                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1264                            (%u == %u) => %lu", __func__, __LINE__, group,
1265                            all_groups, *bit_chk, param->read_correct_mask,
1266                            (long unsigned int)(*bit_chk ==
1267                            param->read_correct_mask));
1268                 return *bit_chk == param->read_correct_mask;
1269         } else  {
1270                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1271                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1272                            (%u != %lu) => %lu\n", __func__, __LINE__,
1273                            group, all_groups, *bit_chk, (long unsigned int)0,
1274                            (long unsigned int)(*bit_chk != 0x00));
1275                 return *bit_chk != 0x00;
1276         }
1277 }
1278
1279 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1280         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1281         uint32_t all_groups)
1282 {
1283         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1284                                               bit_chk, all_groups, 1);
1285 }
1286
1287 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1288 {
1289         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1290         (*v)++;
1291 }
1292
1293 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1294 {
1295         uint32_t i;
1296
1297         for (i = 0; i < VFIFO_SIZE-1; i++)
1298                 rw_mgr_incr_vfifo(grp, v);
1299 }
1300
1301 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1302 {
1303         uint32_t  v;
1304         uint32_t fail_cnt = 0;
1305         uint32_t test_status;
1306
1307         for (v = 0; v < VFIFO_SIZE; ) {
1308                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1309                            __func__, __LINE__, v);
1310                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1311                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1312                 if (!test_status) {
1313                         fail_cnt++;
1314
1315                         if (fail_cnt == 2)
1316                                 break;
1317                 }
1318
1319                 /* fiddle with FIFO */
1320                 rw_mgr_incr_vfifo(grp, &v);
1321         }
1322
1323         if (v >= VFIFO_SIZE) {
1324                 /* no failing read found!! Something must have gone wrong */
1325                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1326                            __func__, __LINE__);
1327                 return 0;
1328         } else {
1329                 return v;
1330         }
1331 }
1332
1333 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1334                               uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1335                               uint32_t *v, uint32_t *d, uint32_t *p,
1336                               uint32_t *i, uint32_t *max_working_cnt)
1337 {
1338         uint32_t found_begin = 0;
1339         uint32_t tmp_delay = 0;
1340         uint32_t test_status;
1341
1342         for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1343                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1344                 *work_bgn = tmp_delay;
1345                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1346
1347                 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1348                         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1349                                 IO_DELAY_PER_OPA_TAP) {
1350                                 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1351
1352                                 test_status =
1353                                 rw_mgr_mem_calibrate_read_test_all_ranks
1354                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1355
1356                                 if (test_status) {
1357                                         *max_working_cnt = 1;
1358                                         found_begin = 1;
1359                                         break;
1360                                 }
1361                         }
1362
1363                         if (found_begin)
1364                                 break;
1365
1366                         if (*p > IO_DQS_EN_PHASE_MAX)
1367                                 /* fiddle with FIFO */
1368                                 rw_mgr_incr_vfifo(*grp, v);
1369                 }
1370
1371                 if (found_begin)
1372                         break;
1373         }
1374
1375         if (*i >= VFIFO_SIZE) {
1376                 /* cannot find working solution */
1377                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1378                            ptap/dtap\n", __func__, __LINE__);
1379                 return 0;
1380         } else {
1381                 return 1;
1382         }
1383 }
1384
1385 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1386                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1387                              uint32_t *p, uint32_t *max_working_cnt)
1388 {
1389         uint32_t found_begin = 0;
1390         uint32_t tmp_delay;
1391
1392         /* Special case code for backing up a phase */
1393         if (*p == 0) {
1394                 *p = IO_DQS_EN_PHASE_MAX;
1395                 rw_mgr_decr_vfifo(*grp, v);
1396         } else {
1397                 (*p)--;
1398         }
1399         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1400         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1401
1402         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1403                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1404                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1405
1406                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1407                                                              PASS_ONE_BIT,
1408                                                              bit_chk, 0)) {
1409                         found_begin = 1;
1410                         *work_bgn = tmp_delay;
1411                         break;
1412                 }
1413         }
1414
1415         /* We have found a working dtap before the ptap found above */
1416         if (found_begin == 1)
1417                 (*max_working_cnt)++;
1418
1419         /*
1420          * Restore VFIFO to old state before we decremented it
1421          * (if needed).
1422          */
1423         (*p)++;
1424         if (*p > IO_DQS_EN_PHASE_MAX) {
1425                 *p = 0;
1426                 rw_mgr_incr_vfifo(*grp, v);
1427         }
1428
1429         scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1430 }
1431
1432 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1433                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1434                              uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1435                              uint32_t *work_end)
1436 {
1437         uint32_t found_end = 0;
1438
1439         (*p)++;
1440         *work_end += IO_DELAY_PER_OPA_TAP;
1441         if (*p > IO_DQS_EN_PHASE_MAX) {
1442                 /* fiddle with FIFO */
1443                 *p = 0;
1444                 rw_mgr_incr_vfifo(*grp, v);
1445         }
1446
1447         for (; *i < VFIFO_SIZE + 1; (*i)++) {
1448                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1449                         += IO_DELAY_PER_OPA_TAP) {
1450                         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1451
1452                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1453                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1454                                 found_end = 1;
1455                                 break;
1456                         } else {
1457                                 (*max_working_cnt)++;
1458                         }
1459                 }
1460
1461                 if (found_end)
1462                         break;
1463
1464                 if (*p > IO_DQS_EN_PHASE_MAX) {
1465                         /* fiddle with FIFO */
1466                         rw_mgr_incr_vfifo(*grp, v);
1467                         *p = 0;
1468                 }
1469         }
1470
1471         if (*i >= VFIFO_SIZE + 1) {
1472                 /* cannot see edge of failing read */
1473                 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1474                            failed\n", __func__, __LINE__);
1475                 return 0;
1476         } else {
1477                 return 1;
1478         }
1479 }
1480
1481 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1482                                   uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1483                                   uint32_t *p, uint32_t *work_mid,
1484                                   uint32_t *work_end)
1485 {
1486         int i;
1487         int tmp_delay = 0;
1488
1489         *work_mid = (*work_bgn + *work_end) / 2;
1490
1491         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1492                    *work_bgn, *work_end, *work_mid);
1493         /* Get the middle delay to be less than a VFIFO delay */
1494         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1495                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1496                 ;
1497         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1498         while (*work_mid > tmp_delay)
1499                 *work_mid -= tmp_delay;
1500         debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1501
1502         tmp_delay = 0;
1503         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1504                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1505                 ;
1506         tmp_delay -= IO_DELAY_PER_OPA_TAP;
1507         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1508         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1509                 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1510                 ;
1511         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1512
1513         scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1514         scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1515
1516         /*
1517          * push vfifo until we can successfully calibrate. We can do this
1518          * because the largest possible margin in 1 VFIFO cycle.
1519          */
1520         for (i = 0; i < VFIFO_SIZE; i++) {
1521                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1522                            *v);
1523                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1524                                                              PASS_ONE_BIT,
1525                                                              bit_chk, 0)) {
1526                         break;
1527                 }
1528
1529                 /* fiddle with FIFO */
1530                 rw_mgr_incr_vfifo(*grp, v);
1531         }
1532
1533         if (i >= VFIFO_SIZE) {
1534                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1535                            failed\n", __func__, __LINE__);
1536                 return 0;
1537         } else {
1538                 return 1;
1539         }
1540 }
1541
1542 /* find a good dqs enable to use */
1543 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1544 {
1545         uint32_t v, d, p, i;
1546         uint32_t max_working_cnt;
1547         uint32_t bit_chk;
1548         uint32_t dtaps_per_ptap;
1549         uint32_t work_bgn, work_mid, work_end;
1550         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1551
1552         debug("%s:%d %u\n", __func__, __LINE__, grp);
1553
1554         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1555
1556         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1557         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1558
1559         /* ************************************************************** */
1560         /* * Step 0 : Determine number of delay taps for each phase tap * */
1561         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1562
1563         /* ********************************************************* */
1564         /* * Step 1 : First push vfifo until we get a failing read * */
1565         v = find_vfifo_read(grp, &bit_chk);
1566
1567         max_working_cnt = 0;
1568
1569         /* ******************************************************** */
1570         /* * step 2: find first working phase, increment in ptaps * */
1571         work_bgn = 0;
1572         if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1573                                 &p, &i, &max_working_cnt) == 0)
1574                 return 0;
1575
1576         work_end = work_bgn;
1577
1578         /*
1579          * If d is 0 then the working window covers a phase tap and
1580          * we can follow the old procedure otherwise, we've found the beginning,
1581          * and we need to increment the dtaps until we find the end.
1582          */
1583         if (d == 0) {
1584                 /* ********************************************************* */
1585                 /* * step 3a: if we have room, back off by one and
1586                 increment in dtaps * */
1587
1588                 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1589                                  &max_working_cnt);
1590
1591                 /* ********************************************************* */
1592                 /* * step 4a: go forward from working phase to non working
1593                 phase, increment in ptaps * */
1594                 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1595                                          &i, &max_working_cnt, &work_end) == 0)
1596                         return 0;
1597
1598                 /* ********************************************************* */
1599                 /* * step 5a:  back off one from last, increment in dtaps  * */
1600
1601                 /* Special case code for backing up a phase */
1602                 if (p == 0) {
1603                         p = IO_DQS_EN_PHASE_MAX;
1604                         rw_mgr_decr_vfifo(grp, &v);
1605                 } else {
1606                         p = p - 1;
1607                 }
1608
1609                 work_end -= IO_DELAY_PER_OPA_TAP;
1610                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1611
1612                 /* * The actual increment of dtaps is done outside of
1613                 the if/else loop to share code */
1614                 d = 0;
1615
1616                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1617                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1618                            v, p);
1619         } else {
1620                 /* ******************************************************* */
1621                 /* * step 3-5b:  Find the right edge of the window using
1622                 delay taps   * */
1623                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1624                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1625                            v, p, d, work_bgn);
1626
1627                 work_end = work_bgn;
1628
1629                 /* * The actual increment of dtaps is done outside of the
1630                 if/else loop to share code */
1631
1632                 /* Only here to counterbalance a subtract later on which is
1633                 not needed if this branch of the algorithm is taken */
1634                 max_working_cnt++;
1635         }
1636
1637         /* The dtap increment to find the failing edge is done here */
1638         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1639                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1640                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1641                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1642                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1643
1644                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1645                                                                       PASS_ONE_BIT,
1646                                                                       &bit_chk, 0)) {
1647                                 break;
1648                         }
1649         }
1650
1651         /* Go back to working dtap */
1652         if (d != 0)
1653                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1654
1655         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1656                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1657                    v, p, d-1, work_end);
1658
1659         if (work_end < work_bgn) {
1660                 /* nil range */
1661                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1662                            failed\n", __func__, __LINE__);
1663                 return 0;
1664         }
1665
1666         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1667                    __func__, __LINE__, work_bgn, work_end);
1668
1669         /* *************************************************************** */
1670         /*
1671          * * We need to calculate the number of dtaps that equal a ptap
1672          * * To do that we'll back up a ptap and re-find the edge of the
1673          * * window using dtaps
1674          */
1675
1676         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1677                    for tracking\n", __func__, __LINE__);
1678
1679         /* Special case code for backing up a phase */
1680         if (p == 0) {
1681                 p = IO_DQS_EN_PHASE_MAX;
1682                 rw_mgr_decr_vfifo(grp, &v);
1683                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1684                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1685                            v, p);
1686         } else {
1687                 p = p - 1;
1688                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1689                            phase only: v=%u p=%u", __func__, __LINE__,
1690                            v, p);
1691         }
1692
1693         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1694
1695         /*
1696          * Increase dtap until we first see a passing read (in case the
1697          * window is smaller than a ptap),
1698          * and then a failing read to mark the edge of the window again
1699          */
1700
1701         /* Find a passing read */
1702         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1703                    __func__, __LINE__);
1704         found_passing_read = 0;
1705         found_failing_read = 0;
1706         initial_failing_dtap = d;
1707         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1708                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1709                            read d=%u\n", __func__, __LINE__, d);
1710                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1711
1712                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1713                                                              PASS_ONE_BIT,
1714                                                              &bit_chk, 0)) {
1715                         found_passing_read = 1;
1716                         break;
1717                 }
1718         }
1719
1720         if (found_passing_read) {
1721                 /* Find a failing read */
1722                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1723                            read\n", __func__, __LINE__);
1724                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1725                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1726                                    testing read d=%u\n", __func__, __LINE__, d);
1727                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1728
1729                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1730                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1731                                 found_failing_read = 1;
1732                                 break;
1733                         }
1734                 }
1735         } else {
1736                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1737                            calculate dtaps", __func__, __LINE__);
1738                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1739         }
1740
1741         /*
1742          * The dynamically calculated dtaps_per_ptap is only valid if we
1743          * found a passing/failing read. If we didn't, it means d hit the max
1744          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1745          * statically calculated value.
1746          */
1747         if (found_passing_read && found_failing_read)
1748                 dtaps_per_ptap = d - initial_failing_dtap;
1749
1750         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1751         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1752                    - %u = %u",  __func__, __LINE__, d,
1753                    initial_failing_dtap, dtaps_per_ptap);
1754
1755         /* ******************************************** */
1756         /* * step 6:  Find the centre of the window   * */
1757         if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1758                                    &work_mid, &work_end) == 0)
1759                 return 0;
1760
1761         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1762                    vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1763                    v, p-1, d);
1764         return 1;
1765 }
1766
1767 /*
1768  * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1769  * dq_in_delay values
1770  */
1771 static uint32_t
1772 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1773 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1774 {
1775         uint32_t found;
1776         uint32_t i;
1777         uint32_t p;
1778         uint32_t d;
1779         uint32_t r;
1780
1781         const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1782                 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1783                 /* we start at zero, so have one less dq to devide among */
1784
1785         debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1786               test_bgn);
1787
1788         /* try different dq_in_delays since the dq path is shorter than dqs */
1789
1790         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1791              r += NUM_RANKS_PER_SHADOW_REG) {
1792                 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
1793                         debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1794                                    vfifo_find_dqs_", __func__, __LINE__);
1795                         debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1796                                write_group, read_group);
1797                         debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1798                         scc_mgr_set_dq_in_delay(p, d);
1799                         scc_mgr_load_dq(p);
1800                 }
1801                 writel(0, &sdr_scc_mgr->update);
1802         }
1803
1804         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1805
1806         debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1807                    en_phase_sweep_dq", __func__, __LINE__);
1808         debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1809                    chain to zero\n", write_group, read_group, found);
1810
1811         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1812              r += NUM_RANKS_PER_SHADOW_REG) {
1813                 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1814                         i++, p++) {
1815                         scc_mgr_set_dq_in_delay(p, 0);
1816                         scc_mgr_load_dq(p);
1817                 }
1818                 writel(0, &sdr_scc_mgr->update);
1819         }
1820
1821         return found;
1822 }
1823
1824 /* per-bit deskew DQ and center */
1825 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1826         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1827         uint32_t use_read_test, uint32_t update_fom)
1828 {
1829         uint32_t i, p, d, min_index;
1830         /*
1831          * Store these as signed since there are comparisons with
1832          * signed numbers.
1833          */
1834         uint32_t bit_chk;
1835         uint32_t sticky_bit_chk;
1836         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1837         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1838         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1839         int32_t mid;
1840         int32_t orig_mid_min, mid_min;
1841         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1842                 final_dqs_en;
1843         int32_t dq_margin, dqs_margin;
1844         uint32_t stop;
1845         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1846         uint32_t addr;
1847
1848         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1849
1850         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1851         start_dqs = readl(addr + (read_group << 2));
1852         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1853                 start_dqs_en = readl(addr + ((read_group << 2)
1854                                      - IO_DQS_EN_DELAY_OFFSET));
1855
1856         /* set the left and right edge of each bit to an illegal value */
1857         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1858         sticky_bit_chk = 0;
1859         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1860                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1861                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1862         }
1863
1864         /* Search for the left edge of the window for each bit */
1865         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1866                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1867
1868                 writel(0, &sdr_scc_mgr->update);
1869
1870                 /*
1871                  * Stop searching when the read test doesn't pass AND when
1872                  * we've seen a passing read on every bit.
1873                  */
1874                 if (use_read_test) {
1875                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1876                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1877                                 &bit_chk, 0, 0);
1878                 } else {
1879                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1880                                                         0, PASS_ONE_BIT,
1881                                                         &bit_chk, 0);
1882                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1883                                 (read_group - (write_group *
1884                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1885                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1886                         stop = (bit_chk == 0);
1887                 }
1888                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1889                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1890                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1891                            && %u", __func__, __LINE__, d,
1892                            sticky_bit_chk,
1893                         param->read_correct_mask, stop);
1894
1895                 if (stop == 1) {
1896                         break;
1897                 } else {
1898                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1899                                 if (bit_chk & 1) {
1900                                         /* Remember a passing test as the
1901                                         left_edge */
1902                                         left_edge[i] = d;
1903                                 } else {
1904                                         /* If a left edge has not been seen yet,
1905                                         then a future passing test will mark
1906                                         this edge as the right edge */
1907                                         if (left_edge[i] ==
1908                                                 IO_IO_IN_DELAY_MAX + 1) {
1909                                                 right_edge[i] = -(d + 1);
1910                                         }
1911                                 }
1912                                 bit_chk = bit_chk >> 1;
1913                         }
1914                 }
1915         }
1916
1917         /* Reset DQ delay chains to 0 */
1918         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1919         sticky_bit_chk = 0;
1920         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1921                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1922                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1923                            i, left_edge[i], i, right_edge[i]);
1924
1925                 /*
1926                  * Check for cases where we haven't found the left edge,
1927                  * which makes our assignment of the the right edge invalid.
1928                  * Reset it to the illegal value.
1929                  */
1930                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1931                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1932                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1933                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1934                                    right_edge[%u]: %d\n", __func__, __LINE__,
1935                                    i, right_edge[i]);
1936                 }
1937
1938                 /*
1939                  * Reset sticky bit (except for bits where we have seen
1940                  * both the left and right edge).
1941                  */
1942                 sticky_bit_chk = sticky_bit_chk << 1;
1943                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1944                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1945                         sticky_bit_chk = sticky_bit_chk | 1;
1946                 }
1947
1948                 if (i == 0)
1949                         break;
1950         }
1951
1952         /* Search for the right edge of the window for each bit */
1953         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1954                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1955                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1956                         uint32_t delay = d + start_dqs_en;
1957                         if (delay > IO_DQS_EN_DELAY_MAX)
1958                                 delay = IO_DQS_EN_DELAY_MAX;
1959                         scc_mgr_set_dqs_en_delay(read_group, delay);
1960                 }
1961                 scc_mgr_load_dqs(read_group);
1962
1963                 writel(0, &sdr_scc_mgr->update);
1964
1965                 /*
1966                  * Stop searching when the read test doesn't pass AND when
1967                  * we've seen a passing read on every bit.
1968                  */
1969                 if (use_read_test) {
1970                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1971                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1972                                 &bit_chk, 0, 0);
1973                 } else {
1974                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1975                                                         0, PASS_ONE_BIT,
1976                                                         &bit_chk, 0);
1977                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1978                                 (read_group - (write_group *
1979                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1980                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1981                         stop = (bit_chk == 0);
1982                 }
1983                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1984                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1985
1986                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1987                            %u && %u", __func__, __LINE__, d,
1988                            sticky_bit_chk, param->read_correct_mask, stop);
1989
1990                 if (stop == 1) {
1991                         break;
1992                 } else {
1993                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1994                                 if (bit_chk & 1) {
1995                                         /* Remember a passing test as
1996                                         the right_edge */
1997                                         right_edge[i] = d;
1998                                 } else {
1999                                         if (d != 0) {
2000                                                 /* If a right edge has not been
2001                                                 seen yet, then a future passing
2002                                                 test will mark this edge as the
2003                                                 left edge */
2004                                                 if (right_edge[i] ==
2005                                                 IO_IO_IN_DELAY_MAX + 1) {
2006                                                         left_edge[i] = -(d + 1);
2007                                                 }
2008                                         } else {
2009                                                 /* d = 0 failed, but it passed
2010                                                 when testing the left edge,
2011                                                 so it must be marginal,
2012                                                 set it to -1 */
2013                                                 if (right_edge[i] ==
2014                                                         IO_IO_IN_DELAY_MAX + 1 &&
2015                                                         left_edge[i] !=
2016                                                         IO_IO_IN_DELAY_MAX
2017                                                         + 1) {
2018                                                         right_edge[i] = -1;
2019                                                 }
2020                                                 /* If a right edge has not been
2021                                                 seen yet, then a future passing
2022                                                 test will mark this edge as the
2023                                                 left edge */
2024                                                 else if (right_edge[i] ==
2025                                                         IO_IO_IN_DELAY_MAX +
2026                                                         1) {
2027                                                         left_edge[i] = -(d + 1);
2028                                                 }
2029                                         }
2030                                 }
2031
2032                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2033                                            d=%u]: ", __func__, __LINE__, d);
2034                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2035                                            (int)(bit_chk & 1), i, left_edge[i]);
2036                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2037                                            right_edge[i]);
2038                                 bit_chk = bit_chk >> 1;
2039                         }
2040                 }
2041         }
2042
2043         /* Check that all bits have a window */
2044         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2045                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2046                            %d right_edge[%u]: %d", __func__, __LINE__,
2047                            i, left_edge[i], i, right_edge[i]);
2048                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2049                         == IO_IO_IN_DELAY_MAX + 1)) {
2050                         /*
2051                          * Restore delay chain settings before letting the loop
2052                          * in rw_mgr_mem_calibrate_vfifo to retry different
2053                          * dqs/ck relationships.
2054                          */
2055                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2056                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2057                                 scc_mgr_set_dqs_en_delay(read_group,
2058                                                          start_dqs_en);
2059                         }
2060                         scc_mgr_load_dqs(read_group);
2061                         writel(0, &sdr_scc_mgr->update);
2062
2063                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2064                                    find edge [%u]: %d %d", __func__, __LINE__,
2065                                    i, left_edge[i], right_edge[i]);
2066                         if (use_read_test) {
2067                                 set_failing_group_stage(read_group *
2068                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2069                                         CAL_STAGE_VFIFO,
2070                                         CAL_SUBSTAGE_VFIFO_CENTER);
2071                         } else {
2072                                 set_failing_group_stage(read_group *
2073                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2074                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2075                                         CAL_SUBSTAGE_VFIFO_CENTER);
2076                         }
2077                         return 0;
2078                 }
2079         }
2080
2081         /* Find middle of window for each DQ bit */
2082         mid_min = left_edge[0] - right_edge[0];
2083         min_index = 0;
2084         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2085                 mid = left_edge[i] - right_edge[i];
2086                 if (mid < mid_min) {
2087                         mid_min = mid;
2088                         min_index = i;
2089                 }
2090         }
2091
2092         /*
2093          * -mid_min/2 represents the amount that we need to move DQS.
2094          * If mid_min is odd and positive we'll need to add one to
2095          * make sure the rounding in further calculations is correct
2096          * (always bias to the right), so just add 1 for all positive values.
2097          */
2098         if (mid_min > 0)
2099                 mid_min++;
2100
2101         mid_min = mid_min / 2;
2102
2103         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2104                    __func__, __LINE__, mid_min, min_index);
2105
2106         /* Determine the amount we can change DQS (which is -mid_min) */
2107         orig_mid_min = mid_min;
2108         new_dqs = start_dqs - mid_min;
2109         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2110                 new_dqs = IO_DQS_IN_DELAY_MAX;
2111         else if (new_dqs < 0)
2112                 new_dqs = 0;
2113
2114         mid_min = start_dqs - new_dqs;
2115         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2116                    mid_min, new_dqs);
2117
2118         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2119                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2120                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2121                 else if (start_dqs_en - mid_min < 0)
2122                         mid_min += start_dqs_en - mid_min;
2123         }
2124         new_dqs = start_dqs - mid_min;
2125
2126         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2127                    new_dqs=%d mid_min=%d\n", start_dqs,
2128                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2129                    new_dqs, mid_min);
2130
2131         /* Initialize data for export structures */
2132         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2133         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2134
2135         /* add delay to bring centre of all DQ windows to the same "level" */
2136         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2137                 /* Use values before divide by 2 to reduce round off error */
2138                 shift_dq = (left_edge[i] - right_edge[i] -
2139                         (left_edge[min_index] - right_edge[min_index]))/2  +
2140                         (orig_mid_min - mid_min);
2141
2142                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2143                            shift_dq[%u]=%d\n", i, shift_dq);
2144
2145                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2146                 temp_dq_in_delay1 = readl(addr + (p << 2));
2147                 temp_dq_in_delay2 = readl(addr + (i << 2));
2148
2149                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2150                         (int32_t)IO_IO_IN_DELAY_MAX) {
2151                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2152                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2153                         shift_dq = -(int32_t)temp_dq_in_delay1;
2154                 }
2155                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2156                            shift_dq[%u]=%d\n", i, shift_dq);
2157                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2158                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2159                 scc_mgr_load_dq(p);
2160
2161                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2162                            left_edge[i] - shift_dq + (-mid_min),
2163                            right_edge[i] + shift_dq - (-mid_min));
2164                 /* To determine values for export structures */
2165                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2166                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2167
2168                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2169                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2170         }
2171
2172         final_dqs = new_dqs;
2173         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2174                 final_dqs_en = start_dqs_en - mid_min;
2175
2176         /* Move DQS-en */
2177         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2178                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2179                 scc_mgr_load_dqs(read_group);
2180         }
2181
2182         /* Move DQS */
2183         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2184         scc_mgr_load_dqs(read_group);
2185         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2186                    dqs_margin=%d", __func__, __LINE__,
2187                    dq_margin, dqs_margin);
2188
2189         /*
2190          * Do not remove this line as it makes sure all of our decisions
2191          * have been applied. Apply the update bit.
2192          */
2193         writel(0, &sdr_scc_mgr->update);
2194
2195         return (dq_margin >= 0) && (dqs_margin >= 0);
2196 }
2197
2198 /**
2199  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2200  * @rw_group:   Read/Write Group
2201  * @phase:      DQ/DQS phase
2202  *
2203  * Because initially no communication ca be reliably performed with the memory
2204  * device, the sequencer uses a guaranteed write mechanism to write data into
2205  * the memory device.
2206  */
2207 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2208                                                  const u32 phase)
2209 {
2210         u32 bit_chk;
2211         int ret;
2212
2213         /* Set a particular DQ/DQS phase. */
2214         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2215
2216         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2217                    __func__, __LINE__, rw_group, phase);
2218
2219         /*
2220          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2221          * Load up the patterns used by read calibration using the
2222          * current DQDQS phase.
2223          */
2224         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2225
2226         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2227                 return 0;
2228
2229         /*
2230          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2231          * Back-to-Back reads of the patterns used for calibration.
2232          */
2233         ret = rw_mgr_mem_calibrate_read_test_patterns_all_ranks(rw_group, 1,
2234                                                                 &bit_chk);
2235         if (!ret) {     /* FIXME: 0 means failure in this old code :-( */
2236                 debug_cond(DLEVEL == 1,
2237                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2238                            __func__, __LINE__, rw_group, phase);
2239                 return -EIO;
2240         }
2241
2242         return 0;
2243 }
2244
2245 /**
2246  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2247  * @rw_group:   Read/Write Group
2248  * @test_bgn:   Rank at which the test begins
2249  *
2250  * DQS enable calibration ensures reliable capture of the DQ signal without
2251  * glitches on the DQS line.
2252  */
2253 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2254                                                        const u32 test_bgn)
2255 {
2256         int ret;
2257
2258         /*
2259          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2260          * DQS and DQS Eanble Signal Relationships.
2261          */
2262         ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
2263                                                 rw_group, rw_group, test_bgn);
2264         if (!ret)       /* FIXME: 0 means failure in this old code :-( */
2265                 return -EIO;
2266
2267         return 0;
2268 }
2269
2270 /**
2271  * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2272  * @rw_group:           Read/Write Group
2273  * @test_bgn:           Rank at which the test begins
2274  * @use_read_test:      Perform a read test
2275  * @update_fom:         Update FOM
2276  *
2277  * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2278  * within a group.
2279  */
2280 static int
2281 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2282                                       const int use_read_test,
2283                                       const int update_fom)
2284
2285 {
2286         int ret, grp_calibrated;
2287         u32 rank_bgn, sr;
2288
2289         /*
2290          * Altera EMI_RM 2015.05.04 :: Figure 1-28
2291          * Read per-bit deskew can be done on a per shadow register basis.
2292          */
2293         grp_calibrated = 1;
2294         for (rank_bgn = 0, sr = 0;
2295              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2296              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2297                 /* Check if this set of ranks should be skipped entirely. */
2298                 if (param->skip_shadow_regs[sr])
2299                         continue;
2300
2301                 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2302                                                         rw_group, test_bgn,
2303                                                         use_read_test,
2304                                                         update_fom);
2305                 if (ret)
2306                         continue;
2307
2308                 grp_calibrated = 0;
2309         }
2310
2311         if (!grp_calibrated)
2312                 return -EIO;
2313
2314         return 0;
2315 }
2316
2317 /**
2318  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2319  * @rw_group:           Read/Write Group
2320  * @test_bgn:           Rank at which the test begins
2321  *
2322  * Stage 1: Calibrate the read valid prediction FIFO.
2323  *
2324  * This function implements UniPHY calibration Stage 1, as explained in
2325  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2326  *
2327  * - read valid prediction will consist of finding:
2328  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2329  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2330  *  - we also do a per-bit deskew on the DQ lines.
2331  */
2332 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2333 {
2334         uint32_t p, d;
2335         uint32_t dtaps_per_ptap;
2336         uint32_t failed_substage;
2337
2338         int ret;
2339
2340         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2341
2342         /* Update info for sims */
2343         reg_file_set_group(rw_group);
2344         reg_file_set_stage(CAL_STAGE_VFIFO);
2345         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2346
2347         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2348
2349         /* USER Determine number of delay taps for each phase tap. */
2350         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2351                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2352
2353         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2354                 /*
2355                  * In RLDRAMX we may be messing the delay of pins in
2356                  * the same write rw_group but outside of the current read
2357                  * the rw_group, but that's ok because we haven't calibrated
2358                  * output side yet.
2359                  */
2360                 if (d > 0) {
2361                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2362                                                                 rw_group, d);
2363                 }
2364
2365                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2366                         /* 1) Guaranteed Write */
2367                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2368                         if (ret)
2369                                 break;
2370
2371                         /* 2) DQS Enable Calibration */
2372                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2373                                                                           test_bgn);
2374                         if (ret) {
2375                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2376                                 continue;
2377                         }
2378
2379                         /* 3) Centering DQ/DQS */
2380                         /*
2381                          * If doing read after write calibration, do not update
2382                          * FOM now. Do it then.
2383                          */
2384                         ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2385                                                                 test_bgn, 1, 0);
2386                         if (ret) {
2387                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2388                                 continue;
2389                         }
2390
2391                         /* All done. */
2392                         goto cal_done_ok;
2393                 }
2394         }
2395
2396         /* Calibration Stage 1 failed. */
2397         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2398         return 0;
2399
2400         /* Calibration Stage 1 completed OK. */
2401 cal_done_ok:
2402         /*
2403          * Reset the delay chains back to zero if they have moved > 1
2404          * (check for > 1 because loop will increase d even when pass in
2405          * first case).
2406          */
2407         if (d > 2)
2408                 scc_mgr_zero_group(rw_group, 1);
2409
2410         return 1;
2411 }
2412
2413 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2414 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2415                                                uint32_t test_bgn)
2416 {
2417         uint32_t rank_bgn, sr;
2418         uint32_t grp_calibrated;
2419         uint32_t write_group;
2420
2421         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2422
2423         /* update info for sims */
2424
2425         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2426         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2427
2428         write_group = read_group;
2429
2430         /* update info for sims */
2431         reg_file_set_group(read_group);
2432
2433         grp_calibrated = 1;
2434         /* Read per-bit deskew can be done on a per shadow register basis */
2435         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2436                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2437                 /* Determine if this set of ranks should be skipped entirely */
2438                 if (!param->skip_shadow_regs[sr]) {
2439                 /* This is the last calibration round, update FOM here */
2440                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2441                                                                 write_group,
2442                                                                 read_group,
2443                                                                 test_bgn, 0,
2444                                                                 1)) {
2445                                 grp_calibrated = 0;
2446                         }
2447                 }
2448         }
2449
2450
2451         if (grp_calibrated == 0) {
2452                 set_failing_group_stage(write_group,
2453                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2454                                         CAL_SUBSTAGE_VFIFO_CENTER);
2455                 return 0;
2456         }
2457
2458         return 1;
2459 }
2460
2461 /* Calibrate LFIFO to find smallest read latency */
2462 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2463 {
2464         uint32_t found_one;
2465         uint32_t bit_chk;
2466
2467         debug("%s:%d\n", __func__, __LINE__);
2468
2469         /* update info for sims */
2470         reg_file_set_stage(CAL_STAGE_LFIFO);
2471         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2472
2473         /* Load up the patterns used by read calibration for all ranks */
2474         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2475         found_one = 0;
2476
2477         do {
2478                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2479                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2480                            __func__, __LINE__, gbl->curr_read_lat);
2481
2482                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2483                                                               NUM_READ_TESTS,
2484                                                               PASS_ALL_BITS,
2485                                                               &bit_chk, 1)) {
2486                         break;
2487                 }
2488
2489                 found_one = 1;
2490                 /* reduce read latency and see if things are working */
2491                 /* correctly */
2492                 gbl->curr_read_lat--;
2493         } while (gbl->curr_read_lat > 0);
2494
2495         /* reset the fifos to get pointers to known state */
2496
2497         writel(0, &phy_mgr_cmd->fifo_reset);
2498
2499         if (found_one) {
2500                 /* add a fudge factor to the read latency that was determined */
2501                 gbl->curr_read_lat += 2;
2502                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2503                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2504                            read_lat=%u\n", __func__, __LINE__,
2505                            gbl->curr_read_lat);
2506                 return 1;
2507         } else {
2508                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2509                                         CAL_SUBSTAGE_READ_LATENCY);
2510
2511                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2512                            read_lat=%u\n", __func__, __LINE__,
2513                            gbl->curr_read_lat);
2514                 return 0;
2515         }
2516 }
2517
2518 /*
2519  * issue write test command.
2520  * two variants are provided. one that just tests a write pattern and
2521  * another that tests datamask functionality.
2522  */
2523 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2524                                                   uint32_t test_dm)
2525 {
2526         uint32_t mcc_instruction;
2527         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2528                 ENABLE_SUPER_QUICK_CALIBRATION);
2529         uint32_t rw_wl_nop_cycles;
2530         uint32_t addr;
2531
2532         /*
2533          * Set counter and jump addresses for the right
2534          * number of NOP cycles.
2535          * The number of supported NOP cycles can range from -1 to infinity
2536          * Three different cases are handled:
2537          *
2538          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2539          *    mechanism will be used to insert the right number of NOPs
2540          *
2541          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2542          *    issuing the write command will jump straight to the
2543          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2544          *    data (for RLD), skipping
2545          *    the NOP micro-instruction all together
2546          *
2547          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2548          *    turned on in the same micro-instruction that issues the write
2549          *    command. Then we need
2550          *    to directly jump to the micro-instruction that sends out the data
2551          *
2552          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2553          *       (2 and 3). One jump-counter (0) is used to perform multiple
2554          *       write-read operations.
2555          *       one counter left to issue this command in "multiple-group" mode
2556          */
2557
2558         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2559
2560         if (rw_wl_nop_cycles == -1) {
2561                 /*
2562                  * CNTR 2 - We want to execute the special write operation that
2563                  * turns on DQS right away and then skip directly to the
2564                  * instruction that sends out the data. We set the counter to a
2565                  * large number so that the jump is always taken.
2566                  */
2567                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2568
2569                 /* CNTR 3 - Not used */
2570                 if (test_dm) {
2571                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2572                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2573                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2574                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2575                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2576                 } else {
2577                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2578                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2579                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2580                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2581                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2582                 }
2583         } else if (rw_wl_nop_cycles == 0) {
2584                 /*
2585                  * CNTR 2 - We want to skip the NOP operation and go straight
2586                  * to the DQS enable instruction. We set the counter to a large
2587                  * number so that the jump is always taken.
2588                  */
2589                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2590
2591                 /* CNTR 3 - Not used */
2592                 if (test_dm) {
2593                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2594                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2595                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2596                 } else {
2597                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2598                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2599                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2600                 }
2601         } else {
2602                 /*
2603                  * CNTR 2 - In this case we want to execute the next instruction
2604                  * and NOT take the jump. So we set the counter to 0. The jump
2605                  * address doesn't count.
2606                  */
2607                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2608                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2609
2610                 /*
2611                  * CNTR 3 - Set the nop counter to the number of cycles we
2612                  * need to loop for, minus 1.
2613                  */
2614                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2615                 if (test_dm) {
2616                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2617                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2618                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2619                 } else {
2620                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2621                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2622                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2623                 }
2624         }
2625
2626         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2627                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2628
2629         if (quick_write_mode)
2630                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2631         else
2632                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2633
2634         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2635
2636         /*
2637          * CNTR 1 - This is used to ensure enough time elapses
2638          * for read data to come back.
2639          */
2640         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2641
2642         if (test_dm) {
2643                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2644                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2645         } else {
2646                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2647                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2648         }
2649
2650         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2651         writel(mcc_instruction, addr + (group << 2));
2652 }
2653
2654 /* Test writes, can check for a single bit pass or multiple bit pass */
2655 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2656         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2657         uint32_t *bit_chk, uint32_t all_ranks)
2658 {
2659         uint32_t r;
2660         uint32_t correct_mask_vg;
2661         uint32_t tmp_bit_chk;
2662         uint32_t vg;
2663         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2664                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2665         uint32_t addr_rw_mgr;
2666         uint32_t base_rw_mgr;
2667
2668         *bit_chk = param->write_correct_mask;
2669         correct_mask_vg = param->write_correct_mask_vg;
2670
2671         for (r = rank_bgn; r < rank_end; r++) {
2672                 if (param->skip_ranks[r]) {
2673                         /* request to skip the rank */
2674                         continue;
2675                 }
2676
2677                 /* set rank */
2678                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2679
2680                 tmp_bit_chk = 0;
2681                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2682                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2683                         /* reset the fifos to get pointers to known state */
2684                         writel(0, &phy_mgr_cmd->fifo_reset);
2685
2686                         tmp_bit_chk = tmp_bit_chk <<
2687                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2688                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2689                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2690                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2691                                 use_dm);
2692
2693                         base_rw_mgr = readl(addr_rw_mgr);
2694                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2695                         if (vg == 0)
2696                                 break;
2697                 }
2698                 *bit_chk &= tmp_bit_chk;
2699         }
2700
2701         if (all_correct) {
2702                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2703                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2704                            %u => %lu", write_group, use_dm,
2705                            *bit_chk, param->write_correct_mask,
2706                            (long unsigned int)(*bit_chk ==
2707                            param->write_correct_mask));
2708                 return *bit_chk == param->write_correct_mask;
2709         } else {
2710                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2711                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2712                        write_group, use_dm, *bit_chk);
2713                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2714                         (long unsigned int)(*bit_chk != 0));
2715                 return *bit_chk != 0x00;
2716         }
2717 }
2718
2719 /*
2720  * center all windows. do per-bit-deskew to possibly increase size of
2721  * certain windows.
2722  */
2723 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2724         uint32_t write_group, uint32_t test_bgn)
2725 {
2726         uint32_t i, p, min_index;
2727         int32_t d;
2728         /*
2729          * Store these as signed since there are comparisons with
2730          * signed numbers.
2731          */
2732         uint32_t bit_chk;
2733         uint32_t sticky_bit_chk;
2734         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2735         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2736         int32_t mid;
2737         int32_t mid_min, orig_mid_min;
2738         int32_t new_dqs, start_dqs, shift_dq;
2739         int32_t dq_margin, dqs_margin, dm_margin;
2740         uint32_t stop;
2741         uint32_t temp_dq_out1_delay;
2742         uint32_t addr;
2743
2744         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2745
2746         dm_margin = 0;
2747
2748         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2749         start_dqs = readl(addr +
2750                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2751
2752         /* per-bit deskew */
2753
2754         /*
2755          * set the left and right edge of each bit to an illegal value
2756          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2757          */
2758         sticky_bit_chk = 0;
2759         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2760                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2761                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2762         }
2763
2764         /* Search for the left edge of the window for each bit */
2765         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2766                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2767
2768                 writel(0, &sdr_scc_mgr->update);
2769
2770                 /*
2771                  * Stop searching when the read test doesn't pass AND when
2772                  * we've seen a passing read on every bit.
2773                  */
2774                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2775                         0, PASS_ONE_BIT, &bit_chk, 0);
2776                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2777                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2778                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2779                            == %u && %u [bit_chk= %u ]\n",
2780                         d, sticky_bit_chk, param->write_correct_mask,
2781                         stop, bit_chk);
2782
2783                 if (stop == 1) {
2784                         break;
2785                 } else {
2786                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2787                                 if (bit_chk & 1) {
2788                                         /*
2789                                          * Remember a passing test as the
2790                                          * left_edge.
2791                                          */
2792                                         left_edge[i] = d;
2793                                 } else {
2794                                         /*
2795                                          * If a left edge has not been seen
2796                                          * yet, then a future passing test will
2797                                          * mark this edge as the right edge.
2798                                          */
2799                                         if (left_edge[i] ==
2800                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2801                                                 right_edge[i] = -(d + 1);
2802                                         }
2803                                 }
2804                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2805                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2806                                            (int)(bit_chk & 1), i, left_edge[i]);
2807                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2808                                        right_edge[i]);
2809                                 bit_chk = bit_chk >> 1;
2810                         }
2811                 }
2812         }
2813
2814         /* Reset DQ delay chains to 0 */
2815         scc_mgr_apply_group_dq_out1_delay(0);
2816         sticky_bit_chk = 0;
2817         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2818                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2819                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2820                            i, left_edge[i], i, right_edge[i]);
2821
2822                 /*
2823                  * Check for cases where we haven't found the left edge,
2824                  * which makes our assignment of the the right edge invalid.
2825                  * Reset it to the illegal value.
2826                  */
2827                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2828                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2829                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2830                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2831                                    right_edge[%u]: %d\n", __func__, __LINE__,
2832                                    i, right_edge[i]);
2833                 }
2834
2835                 /*
2836                  * Reset sticky bit (except for bits where we have
2837                  * seen the left edge).
2838                  */
2839                 sticky_bit_chk = sticky_bit_chk << 1;
2840                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2841                         sticky_bit_chk = sticky_bit_chk | 1;
2842
2843                 if (i == 0)
2844                         break;
2845         }
2846
2847         /* Search for the right edge of the window for each bit */
2848         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2849                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2850                                                         d + start_dqs);
2851
2852                 writel(0, &sdr_scc_mgr->update);
2853
2854                 /*
2855                  * Stop searching when the read test doesn't pass AND when
2856                  * we've seen a passing read on every bit.
2857                  */
2858                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2859                         0, PASS_ONE_BIT, &bit_chk, 0);
2860
2861                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2862                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2863
2864                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2865                            %u && %u\n", d, sticky_bit_chk,
2866                            param->write_correct_mask, stop);
2867
2868                 if (stop == 1) {
2869                         if (d == 0) {
2870                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2871                                         i++) {
2872                                         /* d = 0 failed, but it passed when
2873                                         testing the left edge, so it must be
2874                                         marginal, set it to -1 */
2875                                         if (right_edge[i] ==
2876                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2877                                                 left_edge[i] !=
2878                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2879                                                 right_edge[i] = -1;
2880                                         }
2881                                 }
2882                         }
2883                         break;
2884                 } else {
2885                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2886                                 if (bit_chk & 1) {
2887                                         /*
2888                                          * Remember a passing test as
2889                                          * the right_edge.
2890                                          */
2891                                         right_edge[i] = d;
2892                                 } else {
2893                                         if (d != 0) {
2894                                                 /*
2895                                                  * If a right edge has not
2896                                                  * been seen yet, then a future
2897                                                  * passing test will mark this
2898                                                  * edge as the left edge.
2899                                                  */
2900                                                 if (right_edge[i] ==
2901                                                     IO_IO_OUT1_DELAY_MAX + 1)
2902                                                         left_edge[i] = -(d + 1);
2903                                         } else {
2904                                                 /*
2905                                                  * d = 0 failed, but it passed
2906                                                  * when testing the left edge,
2907                                                  * so it must be marginal, set
2908                                                  * it to -1.
2909                                                  */
2910                                                 if (right_edge[i] ==
2911                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2912                                                     left_edge[i] !=
2913                                                     IO_IO_OUT1_DELAY_MAX + 1)
2914                                                         right_edge[i] = -1;
2915                                                 /*
2916                                                  * If a right edge has not been
2917                                                  * seen yet, then a future
2918                                                  * passing test will mark this
2919                                                  * edge as the left edge.
2920                                                  */
2921                                                 else if (right_edge[i] ==
2922                                                         IO_IO_OUT1_DELAY_MAX +
2923                                                         1)
2924                                                         left_edge[i] = -(d + 1);
2925                                         }
2926                                 }
2927                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2928                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2929                                            (int)(bit_chk & 1), i, left_edge[i]);
2930                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2931                                            right_edge[i]);
2932                                 bit_chk = bit_chk >> 1;
2933                         }
2934                 }
2935         }
2936
2937         /* Check that all bits have a window */
2938         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2939                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2940                            %d right_edge[%u]: %d", __func__, __LINE__,
2941                            i, left_edge[i], i, right_edge[i]);
2942                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2943                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2944                         set_failing_group_stage(test_bgn + i,
2945                                                 CAL_STAGE_WRITES,
2946                                                 CAL_SUBSTAGE_WRITES_CENTER);
2947                         return 0;
2948                 }
2949         }
2950
2951         /* Find middle of window for each DQ bit */
2952         mid_min = left_edge[0] - right_edge[0];
2953         min_index = 0;
2954         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2955                 mid = left_edge[i] - right_edge[i];
2956                 if (mid < mid_min) {
2957                         mid_min = mid;
2958                         min_index = i;
2959                 }
2960         }
2961
2962         /*
2963          * -mid_min/2 represents the amount that we need to move DQS.
2964          * If mid_min is odd and positive we'll need to add one to
2965          * make sure the rounding in further calculations is correct
2966          * (always bias to the right), so just add 1 for all positive values.
2967          */
2968         if (mid_min > 0)
2969                 mid_min++;
2970         mid_min = mid_min / 2;
2971         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2972                    __LINE__, mid_min);
2973
2974         /* Determine the amount we can change DQS (which is -mid_min) */
2975         orig_mid_min = mid_min;
2976         new_dqs = start_dqs;
2977         mid_min = 0;
2978         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2979                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2980         /* Initialize data for export structures */
2981         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2982         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2983
2984         /* add delay to bring centre of all DQ windows to the same "level" */
2985         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2986                 /* Use values before divide by 2 to reduce round off error */
2987                 shift_dq = (left_edge[i] - right_edge[i] -
2988                         (left_edge[min_index] - right_edge[min_index]))/2  +
2989                 (orig_mid_min - mid_min);
2990
2991                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2992                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2993
2994                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2995                 temp_dq_out1_delay = readl(addr + (i << 2));
2996                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2997                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2998                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2999                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
3000                         shift_dq = -(int32_t)temp_dq_out1_delay;
3001                 }
3002                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
3003                            i, shift_dq);
3004                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
3005                 scc_mgr_load_dq(i);
3006
3007                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
3008                            left_edge[i] - shift_dq + (-mid_min),
3009                            right_edge[i] + shift_dq - (-mid_min));
3010                 /* To determine values for export structures */
3011                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
3012                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
3013
3014                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
3015                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
3016         }
3017
3018         /* Move DQS */
3019         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3020         writel(0, &sdr_scc_mgr->update);
3021
3022         /* Centre DM */
3023         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3024
3025         /*
3026          * set the left and right edge of each bit to an illegal value,
3027          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3028          */
3029         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
3030         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3031         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3032         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3033         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3034         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3035         int32_t win_best = 0;
3036
3037         /* Search for the/part of the window with DM shift */
3038         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3039                 scc_mgr_apply_group_dm_out1_delay(d);
3040                 writel(0, &sdr_scc_mgr->update);
3041
3042                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3043                                                     PASS_ALL_BITS, &bit_chk,
3044                                                     0)) {
3045                         /* USE Set current end of the window */
3046                         end_curr = -d;
3047                         /*
3048                          * If a starting edge of our window has not been seen
3049                          * this is our current start of the DM window.
3050                          */
3051                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3052                                 bgn_curr = -d;
3053
3054                         /*
3055                          * If current window is bigger than best seen.
3056                          * Set best seen to be current window.
3057                          */
3058                         if ((end_curr-bgn_curr+1) > win_best) {
3059                                 win_best = end_curr-bgn_curr+1;
3060                                 bgn_best = bgn_curr;
3061                                 end_best = end_curr;
3062                         }
3063                 } else {
3064                         /* We just saw a failing test. Reset temp edge */
3065                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3066                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3067                         }
3068                 }
3069
3070
3071         /* Reset DM delay chains to 0 */
3072         scc_mgr_apply_group_dm_out1_delay(0);
3073
3074         /*
3075          * Check to see if the current window nudges up aganist 0 delay.
3076          * If so we need to continue the search by shifting DQS otherwise DQS
3077          * search begins as a new search. */
3078         if (end_curr != 0) {
3079                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3080                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3081         }
3082
3083         /* Search for the/part of the window with DQS shifts */
3084         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3085                 /*
3086                  * Note: This only shifts DQS, so are we limiting ourselve to
3087                  * width of DQ unnecessarily.
3088                  */
3089                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3090                                                         d + new_dqs);
3091
3092                 writel(0, &sdr_scc_mgr->update);
3093                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3094                                                     PASS_ALL_BITS, &bit_chk,
3095                                                     0)) {
3096                         /* USE Set current end of the window */
3097                         end_curr = d;
3098                         /*
3099                          * If a beginning edge of our window has not been seen
3100                          * this is our current begin of the DM window.
3101                          */
3102                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3103                                 bgn_curr = d;
3104
3105                         /*
3106                          * If current window is bigger than best seen. Set best
3107                          * seen to be current window.
3108                          */
3109                         if ((end_curr-bgn_curr+1) > win_best) {
3110                                 win_best = end_curr-bgn_curr+1;
3111                                 bgn_best = bgn_curr;
3112                                 end_best = end_curr;
3113                         }
3114                 } else {
3115                         /* We just saw a failing test. Reset temp edge */
3116                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3117                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3118
3119                         /* Early exit optimization: if ther remaining delay
3120                         chain space is less than already seen largest window
3121                         we can exit */
3122                         if ((win_best-1) >
3123                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3124                                         break;
3125                                 }
3126                         }
3127                 }
3128
3129         /* assign left and right edge for cal and reporting; */
3130         left_edge[0] = -1*bgn_best;
3131         right_edge[0] = end_best;
3132
3133         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3134                    __LINE__, left_edge[0], right_edge[0]);
3135
3136         /* Move DQS (back to orig) */
3137         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3138
3139         /* Move DM */
3140
3141         /* Find middle of window for the DM bit */
3142         mid = (left_edge[0] - right_edge[0]) / 2;
3143
3144         /* only move right, since we are not moving DQS/DQ */
3145         if (mid < 0)
3146                 mid = 0;
3147
3148         /* dm_marign should fail if we never find a window */
3149         if (win_best == 0)
3150                 dm_margin = -1;
3151         else
3152                 dm_margin = left_edge[0] - mid;
3153
3154         scc_mgr_apply_group_dm_out1_delay(mid);
3155         writel(0, &sdr_scc_mgr->update);
3156
3157         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3158                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3159                    right_edge[0], mid, dm_margin);
3160         /* Export values */
3161         gbl->fom_out += dq_margin + dqs_margin;
3162
3163         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3164                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3165                    dq_margin, dqs_margin, dm_margin);
3166
3167         /*
3168          * Do not remove this line as it makes sure all of our
3169          * decisions have been applied.
3170          */
3171         writel(0, &sdr_scc_mgr->update);
3172         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3173 }
3174
3175 /* calibrate the write operations */
3176 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3177         uint32_t test_bgn)
3178 {
3179         /* update info for sims */
3180         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3181
3182         reg_file_set_stage(CAL_STAGE_WRITES);
3183         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3184
3185         reg_file_set_group(g);
3186
3187         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3188                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3189                                         CAL_SUBSTAGE_WRITES_CENTER);
3190                 return 0;
3191         }
3192
3193         return 1;
3194 }
3195
3196 /**
3197  * mem_precharge_and_activate() - Precharge all banks and activate
3198  *
3199  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3200  */
3201 static void mem_precharge_and_activate(void)
3202 {
3203         int r;
3204
3205         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3206                 /* Test if the rank should be skipped. */
3207                 if (param->skip_ranks[r])
3208                         continue;
3209
3210                 /* Set rank. */
3211                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3212
3213                 /* Precharge all banks. */
3214                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3215                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3216
3217                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3218                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3219                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3220
3221                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3222                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3223                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3224
3225                 /* Activate rows. */
3226                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3227                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3228         }
3229 }
3230
3231 /**
3232  * mem_init_latency() - Configure memory RLAT and WLAT settings
3233  *
3234  * Configure memory RLAT and WLAT parameters.
3235  */
3236 static void mem_init_latency(void)
3237 {
3238         /*
3239          * For AV/CV, LFIFO is hardened and always runs at full rate
3240          * so max latency in AFI clocks, used here, is correspondingly
3241          * smaller.
3242          */
3243         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3244         u32 rlat, wlat;
3245
3246         debug("%s:%d\n", __func__, __LINE__);
3247
3248         /*
3249          * Read in write latency.
3250          * WL for Hard PHY does not include additive latency.
3251          */
3252         wlat = readl(&data_mgr->t_wl_add);
3253         wlat += readl(&data_mgr->mem_t_add);
3254
3255         gbl->rw_wl_nop_cycles = wlat - 1;
3256
3257         /* Read in readl latency. */
3258         rlat = readl(&data_mgr->t_rl_add);
3259
3260         /* Set a pretty high read latency initially. */
3261         gbl->curr_read_lat = rlat + 16;
3262         if (gbl->curr_read_lat > max_latency)
3263                 gbl->curr_read_lat = max_latency;
3264
3265         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3266
3267         /* Advertise write latency. */
3268         writel(wlat, &phy_mgr_cfg->afi_wlat);
3269 }
3270
3271 /**
3272  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3273  *
3274  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3275  */
3276 static void mem_skip_calibrate(void)
3277 {
3278         uint32_t vfifo_offset;
3279         uint32_t i, j, r;
3280
3281         debug("%s:%d\n", __func__, __LINE__);
3282         /* Need to update every shadow register set used by the interface */
3283         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3284              r += NUM_RANKS_PER_SHADOW_REG) {
3285                 /*
3286                  * Set output phase alignment settings appropriate for
3287                  * skip calibration.
3288                  */
3289                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3290                         scc_mgr_set_dqs_en_phase(i, 0);
3291 #if IO_DLL_CHAIN_LENGTH == 6
3292                         scc_mgr_set_dqdqs_output_phase(i, 6);
3293 #else
3294                         scc_mgr_set_dqdqs_output_phase(i, 7);
3295 #endif
3296                         /*
3297                          * Case:33398
3298                          *
3299                          * Write data arrives to the I/O two cycles before write
3300                          * latency is reached (720 deg).
3301                          *   -> due to bit-slip in a/c bus
3302                          *   -> to allow board skew where dqs is longer than ck
3303                          *      -> how often can this happen!?
3304                          *      -> can claim back some ptaps for high freq
3305                          *       support if we can relax this, but i digress...
3306                          *
3307                          * The write_clk leads mem_ck by 90 deg
3308                          * The minimum ptap of the OPA is 180 deg
3309                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3310                          * The write_clk is always delayed by 2 ptaps
3311                          *
3312                          * Hence, to make DQS aligned to CK, we need to delay
3313                          * DQS by:
3314                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3315                          *
3316                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3317                          * gives us the number of ptaps, which simplies to:
3318                          *
3319                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3320                          */
3321                         scc_mgr_set_dqdqs_output_phase(i,
3322                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3323                 }
3324                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3325                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3326
3327                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3328                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3329                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3330                 }
3331                 writel(0xff, &sdr_scc_mgr->dq_ena);
3332                 writel(0xff, &sdr_scc_mgr->dm_ena);
3333                 writel(0, &sdr_scc_mgr->update);
3334         }
3335
3336         /* Compensate for simulation model behaviour */
3337         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3338                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3339                 scc_mgr_load_dqs(i);
3340         }
3341         writel(0, &sdr_scc_mgr->update);
3342
3343         /*
3344          * ArriaV has hard FIFOs that can only be initialized by incrementing
3345          * in sequencer.
3346          */
3347         vfifo_offset = CALIB_VFIFO_OFFSET;
3348         for (j = 0; j < vfifo_offset; j++)
3349                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3350         writel(0, &phy_mgr_cmd->fifo_reset);
3351
3352         /*
3353          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3354          * setting from generation-time constant.
3355          */
3356         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3357         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3358 }
3359
3360 /**
3361  * mem_calibrate() - Memory calibration entry point.
3362  *
3363  * Perform memory calibration.
3364  */
3365 static uint32_t mem_calibrate(void)
3366 {
3367         uint32_t i;
3368         uint32_t rank_bgn, sr;
3369         uint32_t write_group, write_test_bgn;
3370         uint32_t read_group, read_test_bgn;
3371         uint32_t run_groups, current_run;
3372         uint32_t failing_groups = 0;
3373         uint32_t group_failed = 0;
3374
3375         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3376                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3377
3378         debug("%s:%d\n", __func__, __LINE__);
3379
3380         /* Initialize the data settings */
3381         gbl->error_substage = CAL_SUBSTAGE_NIL;
3382         gbl->error_stage = CAL_STAGE_NIL;
3383         gbl->error_group = 0xff;
3384         gbl->fom_in = 0;
3385         gbl->fom_out = 0;
3386
3387         /* Initialize WLAT and RLAT. */
3388         mem_init_latency();
3389
3390         /* Initialize bit slips. */
3391         mem_precharge_and_activate();
3392
3393         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3394                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3395                           SCC_MGR_GROUP_COUNTER_OFFSET);
3396                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3397                 if (i == 0)
3398                         scc_mgr_set_hhp_extras();
3399
3400                 scc_set_bypass_mode(i);
3401         }
3402
3403         /* Calibration is skipped. */
3404         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3405                 /*
3406                  * Set VFIFO and LFIFO to instant-on settings in skip
3407                  * calibration mode.
3408                  */
3409                 mem_skip_calibrate();
3410
3411                 /*
3412                  * Do not remove this line as it makes sure all of our
3413                  * decisions have been applied.
3414                  */
3415                 writel(0, &sdr_scc_mgr->update);
3416                 return 1;
3417         }
3418
3419         /* Calibration is not skipped. */
3420         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3421                 /*
3422                  * Zero all delay chain/phase settings for all
3423                  * groups and all shadow register sets.
3424                  */
3425                 scc_mgr_zero_all();
3426
3427                 run_groups = ~param->skip_groups;
3428
3429                 for (write_group = 0, write_test_bgn = 0; write_group
3430                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3431                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3432
3433                         /* Initialize the group failure */
3434                         group_failed = 0;
3435
3436                         current_run = run_groups & ((1 <<
3437                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3438                         run_groups = run_groups >>
3439                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3440
3441                         if (current_run == 0)
3442                                 continue;
3443
3444                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3445                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3446                         scc_mgr_zero_group(write_group, 0);
3447
3448                         for (read_group = write_group * rwdqs_ratio,
3449                              read_test_bgn = 0;
3450                              read_group < (write_group + 1) * rwdqs_ratio;
3451                              read_group++,
3452                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3453                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3454                                         continue;
3455
3456                                 /* Calibrate the VFIFO */
3457                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3458                                                                read_test_bgn))
3459                                         continue;
3460
3461                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3462                                         return 0;
3463
3464                                 /* The group failed, we're done. */
3465                                 goto grp_failed;
3466                         }
3467
3468                         /* Calibrate the output side */
3469                         for (rank_bgn = 0, sr = 0;
3470                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3471                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3472                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3473                                         continue;
3474
3475                                 /* Not needed in quick mode! */
3476                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3477                                         continue;
3478
3479                                 /*
3480                                  * Determine if this set of ranks
3481                                  * should be skipped entirely.
3482                                  */
3483                                 if (param->skip_shadow_regs[sr])
3484                                         continue;
3485
3486                                 /* Calibrate WRITEs */
3487                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3488                                                 write_group, write_test_bgn))
3489                                         continue;
3490
3491                                 group_failed = 1;
3492                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3493                                         return 0;
3494                         }
3495
3496                         /* Some group failed, we're done. */
3497                         if (group_failed)
3498                                 goto grp_failed;
3499
3500                         for (read_group = write_group * rwdqs_ratio,
3501                              read_test_bgn = 0;
3502                              read_group < (write_group + 1) * rwdqs_ratio;
3503                              read_group++,
3504                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3505                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3506                                         continue;
3507
3508                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3509                                                                 read_test_bgn))
3510                                         continue;
3511
3512                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3513                                         return 0;
3514
3515                                 /* The group failed, we're done. */
3516                                 goto grp_failed;
3517                         }
3518
3519                         /* No group failed, continue as usual. */
3520                         continue;
3521
3522 grp_failed:             /* A group failed, increment the counter. */
3523                         failing_groups++;
3524                 }
3525
3526                 /*
3527                  * USER If there are any failing groups then report
3528                  * the failure.
3529                  */
3530                 if (failing_groups != 0)
3531                         return 0;
3532
3533                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3534                         continue;
3535
3536                 /*
3537                  * If we're skipping groups as part of debug,
3538                  * don't calibrate LFIFO.
3539                  */
3540                 if (param->skip_groups != 0)
3541                         continue;
3542
3543                 /* Calibrate the LFIFO */
3544                 if (!rw_mgr_mem_calibrate_lfifo())
3545                         return 0;
3546         }
3547
3548         /*
3549          * Do not remove this line as it makes sure all of our decisions
3550          * have been applied.
3551          */
3552         writel(0, &sdr_scc_mgr->update);
3553         return 1;
3554 }
3555
3556 /**
3557  * run_mem_calibrate() - Perform memory calibration
3558  *
3559  * This function triggers the entire memory calibration procedure.
3560  */
3561 static int run_mem_calibrate(void)
3562 {
3563         int pass;
3564
3565         debug("%s:%d\n", __func__, __LINE__);
3566
3567         /* Reset pass/fail status shown on afi_cal_success/fail */
3568         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3569
3570         /* Stop tracking manager. */
3571         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3572
3573         phy_mgr_initialize();
3574         rw_mgr_mem_initialize();
3575
3576         /* Perform the actual memory calibration. */
3577         pass = mem_calibrate();
3578
3579         mem_precharge_and_activate();
3580         writel(0, &phy_mgr_cmd->fifo_reset);
3581
3582         /* Handoff. */
3583         rw_mgr_mem_handoff();
3584         /*
3585          * In Hard PHY this is a 2-bit control:
3586          * 0: AFI Mux Select
3587          * 1: DDIO Mux Select
3588          */
3589         writel(0x2, &phy_mgr_cfg->mux_sel);
3590
3591         /* Start tracking manager. */
3592         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3593
3594         return pass;
3595 }
3596
3597 /**
3598  * debug_mem_calibrate() - Report result of memory calibration
3599  * @pass:       Value indicating whether calibration passed or failed
3600  *
3601  * This function reports the results of the memory calibration
3602  * and writes debug information into the register file.
3603  */
3604 static void debug_mem_calibrate(int pass)
3605 {
3606         uint32_t debug_info;
3607
3608         if (pass) {
3609                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3610
3611                 gbl->fom_in /= 2;
3612                 gbl->fom_out /= 2;
3613
3614                 if (gbl->fom_in > 0xff)
3615                         gbl->fom_in = 0xff;
3616
3617                 if (gbl->fom_out > 0xff)
3618                         gbl->fom_out = 0xff;
3619
3620                 /* Update the FOM in the register file */
3621                 debug_info = gbl->fom_in;
3622                 debug_info |= gbl->fom_out << 8;
3623                 writel(debug_info, &sdr_reg_file->fom);
3624
3625                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3626                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3627         } else {
3628                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3629
3630                 debug_info = gbl->error_stage;
3631                 debug_info |= gbl->error_substage << 8;
3632                 debug_info |= gbl->error_group << 16;
3633
3634                 writel(debug_info, &sdr_reg_file->failing_stage);
3635                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3636                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3637
3638                 /* Update the failing group/stage in the register file */
3639                 debug_info = gbl->error_stage;
3640                 debug_info |= gbl->error_substage << 8;
3641                 debug_info |= gbl->error_group << 16;
3642                 writel(debug_info, &sdr_reg_file->failing_stage);
3643         }
3644
3645         printf("%s: Calibration complete\n", __FILE__);
3646 }
3647
3648 /**
3649  * hc_initialize_rom_data() - Initialize ROM data
3650  *
3651  * Initialize ROM data.
3652  */
3653 static void hc_initialize_rom_data(void)
3654 {
3655         u32 i, addr;
3656
3657         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3658         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3659                 writel(inst_rom_init[i], addr + (i << 2));
3660
3661         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3662         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3663                 writel(ac_rom_init[i], addr + (i << 2));
3664 }
3665
3666 /**
3667  * initialize_reg_file() - Initialize SDR register file
3668  *
3669  * Initialize SDR register file.
3670  */
3671 static void initialize_reg_file(void)
3672 {
3673         /* Initialize the register file with the correct data */
3674         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3675         writel(0, &sdr_reg_file->debug_data_addr);
3676         writel(0, &sdr_reg_file->cur_stage);
3677         writel(0, &sdr_reg_file->fom);
3678         writel(0, &sdr_reg_file->failing_stage);
3679         writel(0, &sdr_reg_file->debug1);
3680         writel(0, &sdr_reg_file->debug2);
3681 }
3682
3683 /**
3684  * initialize_hps_phy() - Initialize HPS PHY
3685  *
3686  * Initialize HPS PHY.
3687  */
3688 static void initialize_hps_phy(void)
3689 {
3690         uint32_t reg;
3691         /*
3692          * Tracking also gets configured here because it's in the
3693          * same register.
3694          */
3695         uint32_t trk_sample_count = 7500;
3696         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3697         /*
3698          * Format is number of outer loops in the 16 MSB, sample
3699          * count in 16 LSB.
3700          */
3701
3702         reg = 0;
3703         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3704         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3705         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3706         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3707         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3708         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3709         /*
3710          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3711          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3712          */
3713         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3714         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3715                 trk_sample_count);
3716         writel(reg, &sdr_ctrl->phy_ctrl0);
3717
3718         reg = 0;
3719         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3720                 trk_sample_count >>
3721                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3722         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3723                 trk_long_idle_sample_count);
3724         writel(reg, &sdr_ctrl->phy_ctrl1);
3725
3726         reg = 0;
3727         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3728                 trk_long_idle_sample_count >>
3729                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3730         writel(reg, &sdr_ctrl->phy_ctrl2);
3731 }
3732
3733 /**
3734  * initialize_tracking() - Initialize tracking
3735  *
3736  * Initialize the register file with usable initial data.
3737  */
3738 static void initialize_tracking(void)
3739 {
3740         /*
3741          * Initialize the register file with the correct data.
3742          * Compute usable version of value in case we skip full
3743          * computation later.
3744          */
3745         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3746                &sdr_reg_file->dtaps_per_ptap);
3747
3748         /* trk_sample_count */
3749         writel(7500, &sdr_reg_file->trk_sample_count);
3750
3751         /* longidle outer loop [15:0] */
3752         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3753
3754         /*
3755          * longidle sample count [31:24]
3756          * trfc, worst case of 933Mhz 4Gb [23:16]
3757          * trcd, worst case [15:8]
3758          * vfifo wait [7:0]
3759          */
3760         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3761                &sdr_reg_file->delays);
3762
3763         /* mux delay */
3764         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3765                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3766                &sdr_reg_file->trk_rw_mgr_addr);
3767
3768         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3769                &sdr_reg_file->trk_read_dqs_width);
3770
3771         /* trefi [7:0] */
3772         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3773                &sdr_reg_file->trk_rfsh);
3774 }
3775
3776 int sdram_calibration_full(void)
3777 {
3778         struct param_type my_param;
3779         struct gbl_type my_gbl;
3780         uint32_t pass;
3781
3782         memset(&my_param, 0, sizeof(my_param));
3783         memset(&my_gbl, 0, sizeof(my_gbl));
3784
3785         param = &my_param;
3786         gbl = &my_gbl;
3787
3788         /* Set the calibration enabled by default */
3789         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3790         /*
3791          * Only sweep all groups (regardless of fail state) by default
3792          * Set enabled read test by default.
3793          */
3794 #if DISABLE_GUARANTEED_READ
3795         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3796 #endif
3797         /* Initialize the register file */
3798         initialize_reg_file();
3799
3800         /* Initialize any PHY CSR */
3801         initialize_hps_phy();
3802
3803         scc_mgr_initialize();
3804
3805         initialize_tracking();
3806
3807         printf("%s: Preparing to start memory calibration\n", __FILE__);
3808
3809         debug("%s:%d\n", __func__, __LINE__);
3810         debug_cond(DLEVEL == 1,
3811                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3812                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3813                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3814                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3815                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3816         debug_cond(DLEVEL == 1,
3817                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3818                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3819                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3820                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3821         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3822                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3823         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3824                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3825                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3826         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3827                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3828                    IO_IO_OUT2_DELAY_MAX);
3829         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3830                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3831
3832         hc_initialize_rom_data();
3833
3834         /* update info for sims */
3835         reg_file_set_stage(CAL_STAGE_NIL);
3836         reg_file_set_group(0);
3837
3838         /*
3839          * Load global needed for those actions that require
3840          * some dynamic calibration support.
3841          */
3842         dyn_calib_steps = STATIC_CALIB_STEPS;
3843         /*
3844          * Load global to allow dynamic selection of delay loop settings
3845          * based on calibration mode.
3846          */
3847         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3848                 skip_delay_mask = 0xff;
3849         else
3850                 skip_delay_mask = 0x0;
3851
3852         pass = run_mem_calibrate();
3853         debug_mem_calibrate(pass);
3854         return pass;
3855 }