2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
91 * Only set the global stage if there was not been any other
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
101 static void reg_file_set_group(u16 set_group)
103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
106 static void reg_file_set_stage(u8 set_stage)
108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
111 static void reg_file_set_sub_stage(u8 set_sub_stage)
113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
118 * phy_mgr_initialize() - Initialize PHY Manager
120 * Initialize PHY Manager.
122 static void phy_mgr_initialize(void)
126 debug("%s:%d\n", __func__, __LINE__);
127 /* Calibration has control over path to memory */
129 * In Hard PHY this is a 2-bit control:
133 writel(0x3, &phy_mgr_cfg->mux_sel);
135 /* USER memory clock is not stable we begin initialization */
136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
138 /* USER calibration status all set to zero */
139 writel(0, &phy_mgr_cfg->cal_status);
141 writel(0, &phy_mgr_cfg->cal_debug_info);
143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
163 * Set Rank and ODT mask (On-Die Termination).
165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
177 /* Read: ODT = 0 ; Write: ODT = 1 */
181 case 2: /* 2 Ranks */
182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
195 odt_mask_0 = 0x3 & ~(1 << rank);
199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
205 odt_mask_1 = 0x3 & (1 << rank);
208 case 4: /* 4 Ranks */
210 * ----------+-----------------------+
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
222 * ----------+-----------------------+
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
276 * scc_mgr_initialize() - Initialize SCC Manager registers
278 * Initialize SCC Manager registers.
280 static void scc_mgr_initialize(void)
283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
290 for (i = 0; i < 16; i++) {
291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
292 __func__, __LINE__, i);
293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
346 /* load up dqs config settings */
347 static void scc_mgr_load_dqs(uint32_t dqs)
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
352 /* load up dqs io config settings */
353 static void scc_mgr_load_dqs_io(void)
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
358 /* load up dq config settings */
359 static void scc_mgr_load_dq(uint32_t dq_in_group)
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
364 /* load up dm config settings */
365 static void scc_mgr_load_dm(uint32_t dm)
367 writel(dm, &sdr_scc_mgr->dm_ena);
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
387 scc_mgr_set(off, grp, val);
389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
391 writel(0, &sdr_scc_mgr->update);
396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
438 writel(0, &sdr_scc_mgr->update);
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
446 * This function sets the OCT output delay in SCC manager.
448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
468 * Load the fixed setting in the SCC manager HHP extras.
470 static void scc_mgr_set_hhp_extras(void)
473 * Load the fixed setting in the SCC manager
474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
495 * scc_mgr_zero_all() - Zero all DQS config
497 * Zero all DQS config.
499 static void scc_mgr_zero_all(void)
504 * USER Zero all DQS config settings, across all groups and all
507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
522 /* Arria V/Cyclone V don't have out2. */
523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
527 /* Multicast to all DQS group enables. */
528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
536 * Set bypass mode and trigger SCC update.
538 static void scc_set_bypass_mode(const u32 write_group)
540 /* Multicast to all DQ enables. */
541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
544 /* Update current DQS IO enable. */
545 writel(0, &sdr_scc_mgr->dqs_io_ena);
547 /* Update the DQS logic. */
548 writel(write_group, &sdr_scc_mgr->dqs_ena);
551 writel(0, &sdr_scc_mgr->update);
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
558 * Load DQS settings for Write Group, do not trigger SCC update.
560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
567 * Load the setting in the SCC manager
568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
571 * the setting must be set multiple times.
573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
578 * scc_mgr_zero_group() - Zero all configs for a group
580 * Zero DQ, DM, DQS and OCT configs for a group.
582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
590 scc_mgr_set_dq_out1_delay(i, 0);
592 scc_mgr_set_dq_in_delay(i, 0);
595 /* Multicast to all DQ enables. */
596 writel(0xff, &sdr_scc_mgr->dq_ena);
598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
600 scc_mgr_set_dm_out1_delay(i, 0);
602 /* Multicast to all DM enables. */
603 writel(0xff, &sdr_scc_mgr->dm_ena);
605 /* Zero all DQS IO settings. */
607 scc_mgr_set_dqs_io_in_delay(0);
609 /* Arria V/Cyclone V don't have out2. */
610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
614 /* Multicast to all DQS IO enables (only 1 in total). */
615 writel(0, &sdr_scc_mgr->dqs_io_ena);
617 /* Hit update to zero everything. */
618 writel(0, &sdr_scc_mgr->update);
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
631 scc_mgr_set_dq_in_delay(p, delay);
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
640 * Apply and load a particular output delay for the DQ pins in a group.
642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
652 /* apply and load a particular output delay for the DM pins in a group */
653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
658 scc_mgr_set_dm_out1_delay(i, delay1);
664 /* apply and load delay on both DQS and OCT out1 */
665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
668 scc_mgr_set_dqs_out1_delay(delay);
669 scc_mgr_load_dqs_io();
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
702 new_delay - IO_IO_OUT2_DELAY_MAX);
703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
707 scc_mgr_load_dqs_io();
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
716 new_delay - IO_IO_OUT2_DELAY_MAX);
717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
721 scc_mgr_load_dqs_for_write_group(write_group);
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
738 r += NUM_RANKS_PER_SHADOW_REG) {
739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
740 writel(0, &sdr_scc_mgr->update);
745 * set_jump_as_return() - Return instruction optimization
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
750 static void set_jump_as_return(void)
753 * To save space, we replace return with jump to special shared
754 * RETURN instruction so we set the counter to large value so that
757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
765 static void delay_for_n_mem_clocks(const uint32_t clocks)
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 if (afi_clocks == 0) {
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
791 } else if (afi_clocks <= 0x10000) {
793 outer = (afi_clocks-1) >> 8;
798 c_loop = (afi_clocks-1) >> 16;
802 * rom instructions are structured as follows:
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
818 if (afi_clocks <= 0x100) {
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
850 } while (c_loop-- != 0);
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
863 * Load instruction registers.
865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
883 /* Execute count instruction */
884 writel(jump, grpaddr);
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
893 * Load user calibration values and optionally precharge the banks.
895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
911 /* precharge all banks ... */
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
916 * USER Use Mirror-ed commands for odd ranks if address
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
956 * rw_mgr_mem_initialize() - Initialize RW Manager
958 * Initialize RW Manager.
960 static void rw_mgr_mem_initialize(void)
962 debug("%s:%d\n", __func__, __LINE__);
964 /* The reset / cke part of initialization is broadcasted to all ranks */
965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
978 /* Start with memory RESET activated */
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
995 /* Indicate that memory is stable. */
996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
999 * transition the RESET to high
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
1016 /* Bring up clock enable. */
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1029 static void rw_mgr_mem_handoff(void)
1031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050 const u32 all_ranks)
1052 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054 const u32 addr_offset =
1055 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056 const u32 rank_end = all_ranks ?
1057 RW_MGR_MEM_NUMBER_OF_RANKS :
1058 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061 const u32 correct_mask_vg = param->read_correct_mask_vg;
1063 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1067 bit_chk = param->read_correct_mask;
1069 for (r = rank_bgn; r < rank_end; r++) {
1070 /* Request to skip the rank */
1071 if (param->skip_ranks[r])
1075 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1077 /* Load up a constant bursts of read commands */
1078 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079 writel(RW_MGR_GUARANTEED_READ,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1082 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083 writel(RW_MGR_GUARANTEED_READ_CONT,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1087 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1089 /* Reset the FIFOs to get pointers to known state. */
1090 writel(0, &phy_mgr_cmd->fifo_reset);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093 writel(RW_MGR_GUARANTEED_READ,
1094 addr + addr_offset + (vg << 2));
1096 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097 tmp_bit_chk <<= shift_ratio;
1098 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1101 bit_chk &= tmp_bit_chk;
1104 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1108 if (bit_chk != param->read_correct_mask)
1111 debug_cond(DLEVEL == 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__, __LINE__, group, bit_chk,
1114 param->read_correct_mask, ret);
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1124 * Load up the patterns we are going to use during a read test.
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127 const int all_ranks)
1129 const u32 rank_end = all_ranks ?
1130 RW_MGR_MEM_NUMBER_OF_RANKS :
1131 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1134 debug("%s:%d\n", __func__, __LINE__);
1136 for (r = rank_bgn; r < rank_end; r++) {
1137 if (param->skip_ranks[r])
1138 /* request to skip the rank */
1142 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1144 /* Load up a constant bursts */
1145 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1150 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1155 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1160 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1165 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1173 * try a read and see if it returns correct data back. has dummy reads
1174 * inserted into the mix used to align dqs enable. has more thorough checks
1175 * than the regular read test.
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179 uint32_t all_groups, uint32_t all_ranks)
1182 uint32_t correct_mask_vg;
1183 uint32_t tmp_bit_chk;
1184 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1187 uint32_t base_rw_mgr;
1189 *bit_chk = param->read_correct_mask;
1190 correct_mask_vg = param->read_correct_mask_vg;
1192 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1195 for (r = rank_bgn; r < rank_end; r++) {
1196 if (param->skip_ranks[r])
1197 /* request to skip the rank */
1201 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1203 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1205 writel(RW_MGR_READ_B2B_WAIT1,
1206 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1208 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209 writel(RW_MGR_READ_B2B_WAIT2,
1210 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1212 if (quick_read_mode)
1213 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214 /* need at least two (1+1) reads to capture failures */
1215 else if (all_groups)
1216 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1218 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1220 writel(RW_MGR_READ_B2B,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1223 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225 &sdr_rw_load_mgr_regs->load_cntr3);
1227 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1229 writel(RW_MGR_READ_B2B,
1230 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1233 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234 /* reset the fifos to get pointers to known state */
1235 writel(0, &phy_mgr_cmd->fifo_reset);
1236 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1239 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1243 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1245 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1247 writel(RW_MGR_READ_B2B, addr +
1248 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1251 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1257 *bit_chk &= tmp_bit_chk;
1260 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1264 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266 (%u == %u) => %lu", __func__, __LINE__, group,
1267 all_groups, *bit_chk, param->read_correct_mask,
1268 (long unsigned int)(*bit_chk ==
1269 param->read_correct_mask));
1270 return *bit_chk == param->read_correct_mask;
1272 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274 (%u != %lu) => %lu\n", __func__, __LINE__,
1275 group, all_groups, *bit_chk, (long unsigned int)0,
1276 (long unsigned int)(*bit_chk != 0x00));
1277 return *bit_chk != 0x00;
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283 uint32_t all_groups)
1285 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286 bit_chk, all_groups, 1);
1289 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1291 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1295 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1299 for (i = 0; i < VFIFO_SIZE-1; i++)
1300 rw_mgr_incr_vfifo(grp, v);
1303 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1306 uint32_t fail_cnt = 0;
1307 uint32_t test_status;
1309 for (v = 0; v < VFIFO_SIZE; ) {
1310 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1311 __func__, __LINE__, v);
1312 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1313 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1321 /* fiddle with FIFO */
1322 rw_mgr_incr_vfifo(grp, &v);
1325 if (v >= VFIFO_SIZE) {
1326 /* no failing read found!! Something must have gone wrong */
1327 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1328 __func__, __LINE__);
1336 * sdr_find_phase() - Find DQS enable phase
1337 * @working: If 1, look for working phase, if 0, look for non-working phase
1338 * @grp: Read/Write group
1340 * @work: Working window position
1342 * @p: DQS Phase Iterator
1344 * Find working or non-working DQS enable phase setting.
1346 static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
1350 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1352 for (; *i < end; (*i)++) {
1356 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
1357 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1359 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1360 PASS_ONE_BIT, &bit_chk, 0);
1367 *work += IO_DELAY_PER_OPA_TAP;
1370 if (*p > IO_DQS_EN_PHASE_MAX) {
1371 /* Fiddle with FIFO. */
1372 rw_mgr_incr_vfifo(grp, v);
1381 static int sdr_working_phase(uint32_t grp,
1382 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1383 uint32_t *v, uint32_t *d, uint32_t *p,
1390 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1392 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1393 ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
1396 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1399 /* Cannot find working solution */
1400 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1401 __func__, __LINE__);
1405 static void sdr_backup_phase(uint32_t grp,
1406 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1412 /* Special case code for backing up a phase */
1414 *p = IO_DQS_EN_PHASE_MAX;
1415 rw_mgr_decr_vfifo(grp, v);
1419 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1420 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1422 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1423 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1424 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1426 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1429 *work_bgn = tmp_delay;
1435 * Restore VFIFO to old state before we decremented it
1439 if (*p > IO_DQS_EN_PHASE_MAX) {
1441 rw_mgr_incr_vfifo(grp, v);
1444 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1447 static int sdr_nonworking_phase(uint32_t grp,
1448 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1449 uint32_t *p, uint32_t *i,
1455 *work_end += IO_DELAY_PER_OPA_TAP;
1456 if (*p > IO_DQS_EN_PHASE_MAX) {
1457 /* Fiddle with FIFO. */
1459 rw_mgr_incr_vfifo(grp, v);
1462 ret = sdr_find_phase(0, grp, v, work_end, i, p);
1464 /* Cannot see edge of failing read. */
1465 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1466 __func__, __LINE__);
1473 * sdr_find_window_center() - Find center of the working DQS window.
1474 * @grp: Read/Write group
1475 * @work_bgn: First working settings
1476 * @work_end: Last working settings
1479 * Find center of the working DQS enable window.
1481 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1482 const u32 work_end, const u32 val)
1484 u32 bit_chk, work_mid, v = val;
1488 work_mid = (work_bgn + work_end) / 2;
1490 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1491 work_bgn, work_end, work_mid);
1492 /* Get the middle delay to be less than a VFIFO delay */
1493 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1495 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1496 work_mid %= tmp_delay;
1497 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1499 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1500 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1501 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1502 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1504 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1506 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1507 if (d > IO_DQS_EN_DELAY_MAX)
1508 d = IO_DQS_EN_DELAY_MAX;
1509 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1511 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1513 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1514 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1517 * push vfifo until we can successfully calibrate. We can do this
1518 * because the largest possible margin in 1 VFIFO cycle.
1520 for (i = 0; i < VFIFO_SIZE; i++) {
1521 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1523 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1526 debug_cond(DLEVEL == 2,
1527 "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
1528 __func__, __LINE__, v, p, d);
1532 /* Fiddle with FIFO. */
1533 rw_mgr_incr_vfifo(grp, &v);
1536 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1537 __func__, __LINE__);
1541 /* find a good dqs enable to use */
1542 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1544 uint32_t v, d, p, i;
1546 uint32_t dtaps_per_ptap;
1547 uint32_t work_bgn, work_end;
1548 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1550 debug("%s:%d %u\n", __func__, __LINE__, grp);
1552 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1554 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1555 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1557 /* ************************************************************** */
1558 /* * Step 0 : Determine number of delay taps for each phase tap * */
1559 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1561 /* ********************************************************* */
1562 /* * Step 1 : First push vfifo until we get a failing read * */
1563 v = find_vfifo_read(grp, &bit_chk);
1565 /* ******************************************************** */
1566 /* * step 2: find first working phase, increment in ptaps * */
1568 if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d, &p, &i))
1571 work_end = work_bgn;
1574 * If d is 0 then the working window covers a phase tap and
1575 * we can follow the old procedure otherwise, we've found the beginning,
1576 * and we need to increment the dtaps until we find the end.
1579 /* ********************************************************* */
1580 /* * step 3a: if we have room, back off by one and
1581 increment in dtaps * */
1583 sdr_backup_phase(grp, &work_bgn, &v, &d, &p);
1585 /* ********************************************************* */
1586 /* * step 4a: go forward from working phase to non working
1587 phase, increment in ptaps * */
1588 if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
1592 /* ********************************************************* */
1593 /* * step 5a: back off one from last, increment in dtaps * */
1595 /* Special case code for backing up a phase */
1597 p = IO_DQS_EN_PHASE_MAX;
1598 rw_mgr_decr_vfifo(grp, &v);
1603 work_end -= IO_DELAY_PER_OPA_TAP;
1604 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1606 /* * The actual increment of dtaps is done outside of
1607 the if/else loop to share code */
1610 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1611 vfifo=%u ptap=%u\n", __func__, __LINE__,
1614 /* ******************************************************* */
1615 /* * step 3-5b: Find the right edge of the window using
1617 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1618 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1621 work_end = work_bgn;
1624 /* The dtap increment to find the failing edge is done here */
1625 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1626 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1627 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1628 end-2: dtap=%u\n", __func__, __LINE__, d);
1629 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1631 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1638 /* Go back to working dtap */
1640 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1642 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1643 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1644 v, p, d-1, work_end);
1646 if (work_end < work_bgn) {
1648 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1649 failed\n", __func__, __LINE__);
1653 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1654 __func__, __LINE__, work_bgn, work_end);
1656 /* *************************************************************** */
1658 * * We need to calculate the number of dtaps that equal a ptap
1659 * * To do that we'll back up a ptap and re-find the edge of the
1660 * * window using dtaps
1663 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1664 for tracking\n", __func__, __LINE__);
1666 /* Special case code for backing up a phase */
1668 p = IO_DQS_EN_PHASE_MAX;
1669 rw_mgr_decr_vfifo(grp, &v);
1670 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1671 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1675 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1676 phase only: v=%u p=%u", __func__, __LINE__,
1680 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1683 * Increase dtap until we first see a passing read (in case the
1684 * window is smaller than a ptap),
1685 * and then a failing read to mark the edge of the window again
1688 /* Find a passing read */
1689 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1690 __func__, __LINE__);
1691 found_passing_read = 0;
1692 found_failing_read = 0;
1693 initial_failing_dtap = d;
1694 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1695 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1696 read d=%u\n", __func__, __LINE__, d);
1697 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1699 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1702 found_passing_read = 1;
1707 if (found_passing_read) {
1708 /* Find a failing read */
1709 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1710 read\n", __func__, __LINE__);
1711 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1712 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1713 testing read d=%u\n", __func__, __LINE__, d);
1714 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1716 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1717 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1718 found_failing_read = 1;
1723 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1724 calculate dtaps", __func__, __LINE__);
1725 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1729 * The dynamically calculated dtaps_per_ptap is only valid if we
1730 * found a passing/failing read. If we didn't, it means d hit the max
1731 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1732 * statically calculated value.
1734 if (found_passing_read && found_failing_read)
1735 dtaps_per_ptap = d - initial_failing_dtap;
1737 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1738 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1739 - %u = %u", __func__, __LINE__, d,
1740 initial_failing_dtap, dtaps_per_ptap);
1742 /* ******************************************** */
1743 /* * step 6: Find the centre of the window * */
1744 if (sdr_find_window_centre(grp, work_bgn, work_end, v))
1745 return 0; /* FIXME: Old code, return 0 means failure :-( */
1750 /* per-bit deskew DQ and center */
1751 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1752 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1753 uint32_t use_read_test, uint32_t update_fom)
1755 uint32_t i, p, d, min_index;
1757 * Store these as signed since there are comparisons with
1761 uint32_t sticky_bit_chk;
1762 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1763 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1764 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1766 int32_t orig_mid_min, mid_min;
1767 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1769 int32_t dq_margin, dqs_margin;
1771 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1774 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1776 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1777 start_dqs = readl(addr + (read_group << 2));
1778 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1779 start_dqs_en = readl(addr + ((read_group << 2)
1780 - IO_DQS_EN_DELAY_OFFSET));
1782 /* set the left and right edge of each bit to an illegal value */
1783 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1785 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1786 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1787 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1790 /* Search for the left edge of the window for each bit */
1791 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1792 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1794 writel(0, &sdr_scc_mgr->update);
1797 * Stop searching when the read test doesn't pass AND when
1798 * we've seen a passing read on every bit.
1800 if (use_read_test) {
1801 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1802 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1805 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1808 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1809 (read_group - (write_group *
1810 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1811 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1812 stop = (bit_chk == 0);
1814 sticky_bit_chk = sticky_bit_chk | bit_chk;
1815 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1816 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1817 && %u", __func__, __LINE__, d,
1819 param->read_correct_mask, stop);
1824 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1826 /* Remember a passing test as the
1830 /* If a left edge has not been seen yet,
1831 then a future passing test will mark
1832 this edge as the right edge */
1834 IO_IO_IN_DELAY_MAX + 1) {
1835 right_edge[i] = -(d + 1);
1838 bit_chk = bit_chk >> 1;
1843 /* Reset DQ delay chains to 0 */
1844 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1846 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1847 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1848 %d right_edge[%u]: %d\n", __func__, __LINE__,
1849 i, left_edge[i], i, right_edge[i]);
1852 * Check for cases where we haven't found the left edge,
1853 * which makes our assignment of the the right edge invalid.
1854 * Reset it to the illegal value.
1856 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1857 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1858 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1859 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1860 right_edge[%u]: %d\n", __func__, __LINE__,
1865 * Reset sticky bit (except for bits where we have seen
1866 * both the left and right edge).
1868 sticky_bit_chk = sticky_bit_chk << 1;
1869 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1870 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1871 sticky_bit_chk = sticky_bit_chk | 1;
1878 /* Search for the right edge of the window for each bit */
1879 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1880 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1881 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1882 uint32_t delay = d + start_dqs_en;
1883 if (delay > IO_DQS_EN_DELAY_MAX)
1884 delay = IO_DQS_EN_DELAY_MAX;
1885 scc_mgr_set_dqs_en_delay(read_group, delay);
1887 scc_mgr_load_dqs(read_group);
1889 writel(0, &sdr_scc_mgr->update);
1892 * Stop searching when the read test doesn't pass AND when
1893 * we've seen a passing read on every bit.
1895 if (use_read_test) {
1896 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1897 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1900 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1903 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1904 (read_group - (write_group *
1905 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1906 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1907 stop = (bit_chk == 0);
1909 sticky_bit_chk = sticky_bit_chk | bit_chk;
1910 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1912 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1913 %u && %u", __func__, __LINE__, d,
1914 sticky_bit_chk, param->read_correct_mask, stop);
1919 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1921 /* Remember a passing test as
1926 /* If a right edge has not been
1927 seen yet, then a future passing
1928 test will mark this edge as the
1930 if (right_edge[i] ==
1931 IO_IO_IN_DELAY_MAX + 1) {
1932 left_edge[i] = -(d + 1);
1935 /* d = 0 failed, but it passed
1936 when testing the left edge,
1937 so it must be marginal,
1939 if (right_edge[i] ==
1940 IO_IO_IN_DELAY_MAX + 1 &&
1946 /* If a right edge has not been
1947 seen yet, then a future passing
1948 test will mark this edge as the
1950 else if (right_edge[i] ==
1951 IO_IO_IN_DELAY_MAX +
1953 left_edge[i] = -(d + 1);
1958 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1959 d=%u]: ", __func__, __LINE__, d);
1960 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1961 (int)(bit_chk & 1), i, left_edge[i]);
1962 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1964 bit_chk = bit_chk >> 1;
1969 /* Check that all bits have a window */
1970 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1971 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1972 %d right_edge[%u]: %d", __func__, __LINE__,
1973 i, left_edge[i], i, right_edge[i]);
1974 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
1975 == IO_IO_IN_DELAY_MAX + 1)) {
1977 * Restore delay chain settings before letting the loop
1978 * in rw_mgr_mem_calibrate_vfifo to retry different
1979 * dqs/ck relationships.
1981 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
1982 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1983 scc_mgr_set_dqs_en_delay(read_group,
1986 scc_mgr_load_dqs(read_group);
1987 writel(0, &sdr_scc_mgr->update);
1989 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
1990 find edge [%u]: %d %d", __func__, __LINE__,
1991 i, left_edge[i], right_edge[i]);
1992 if (use_read_test) {
1993 set_failing_group_stage(read_group *
1994 RW_MGR_MEM_DQ_PER_READ_DQS + i,
1996 CAL_SUBSTAGE_VFIFO_CENTER);
1998 set_failing_group_stage(read_group *
1999 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2000 CAL_STAGE_VFIFO_AFTER_WRITES,
2001 CAL_SUBSTAGE_VFIFO_CENTER);
2007 /* Find middle of window for each DQ bit */
2008 mid_min = left_edge[0] - right_edge[0];
2010 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2011 mid = left_edge[i] - right_edge[i];
2012 if (mid < mid_min) {
2019 * -mid_min/2 represents the amount that we need to move DQS.
2020 * If mid_min is odd and positive we'll need to add one to
2021 * make sure the rounding in further calculations is correct
2022 * (always bias to the right), so just add 1 for all positive values.
2027 mid_min = mid_min / 2;
2029 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2030 __func__, __LINE__, mid_min, min_index);
2032 /* Determine the amount we can change DQS (which is -mid_min) */
2033 orig_mid_min = mid_min;
2034 new_dqs = start_dqs - mid_min;
2035 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2036 new_dqs = IO_DQS_IN_DELAY_MAX;
2037 else if (new_dqs < 0)
2040 mid_min = start_dqs - new_dqs;
2041 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2044 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2045 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2046 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2047 else if (start_dqs_en - mid_min < 0)
2048 mid_min += start_dqs_en - mid_min;
2050 new_dqs = start_dqs - mid_min;
2052 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2053 new_dqs=%d mid_min=%d\n", start_dqs,
2054 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2057 /* Initialize data for export structures */
2058 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2059 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2061 /* add delay to bring centre of all DQ windows to the same "level" */
2062 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2063 /* Use values before divide by 2 to reduce round off error */
2064 shift_dq = (left_edge[i] - right_edge[i] -
2065 (left_edge[min_index] - right_edge[min_index]))/2 +
2066 (orig_mid_min - mid_min);
2068 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2069 shift_dq[%u]=%d\n", i, shift_dq);
2071 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2072 temp_dq_in_delay1 = readl(addr + (p << 2));
2073 temp_dq_in_delay2 = readl(addr + (i << 2));
2075 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2076 (int32_t)IO_IO_IN_DELAY_MAX) {
2077 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2078 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2079 shift_dq = -(int32_t)temp_dq_in_delay1;
2081 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2082 shift_dq[%u]=%d\n", i, shift_dq);
2083 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2084 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2087 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2088 left_edge[i] - shift_dq + (-mid_min),
2089 right_edge[i] + shift_dq - (-mid_min));
2090 /* To determine values for export structures */
2091 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2092 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2094 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2095 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2098 final_dqs = new_dqs;
2099 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2100 final_dqs_en = start_dqs_en - mid_min;
2103 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2104 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2105 scc_mgr_load_dqs(read_group);
2109 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2110 scc_mgr_load_dqs(read_group);
2111 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2112 dqs_margin=%d", __func__, __LINE__,
2113 dq_margin, dqs_margin);
2116 * Do not remove this line as it makes sure all of our decisions
2117 * have been applied. Apply the update bit.
2119 writel(0, &sdr_scc_mgr->update);
2121 return (dq_margin >= 0) && (dqs_margin >= 0);
2125 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2126 * @rw_group: Read/Write Group
2127 * @phase: DQ/DQS phase
2129 * Because initially no communication ca be reliably performed with the memory
2130 * device, the sequencer uses a guaranteed write mechanism to write data into
2131 * the memory device.
2133 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2138 /* Set a particular DQ/DQS phase. */
2139 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2141 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2142 __func__, __LINE__, rw_group, phase);
2145 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2146 * Load up the patterns used by read calibration using the
2147 * current DQDQS phase.
2149 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2151 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2155 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2156 * Back-to-Back reads of the patterns used for calibration.
2158 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2160 debug_cond(DLEVEL == 1,
2161 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2162 __func__, __LINE__, rw_group, phase);
2167 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2168 * @rw_group: Read/Write Group
2169 * @test_bgn: Rank at which the test begins
2171 * DQS enable calibration ensures reliable capture of the DQ signal without
2172 * glitches on the DQS line.
2174 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2178 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2179 * DQS and DQS Eanble Signal Relationships.
2182 /* We start at zero, so have one less dq to devide among */
2183 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2184 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2188 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2190 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2191 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2192 r += NUM_RANKS_PER_SHADOW_REG) {
2193 for (i = 0, p = test_bgn, d = 0;
2194 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2195 i++, p++, d += delay_step) {
2196 debug_cond(DLEVEL == 1,
2197 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2198 __func__, __LINE__, rw_group, r, i, p, d);
2200 scc_mgr_set_dq_in_delay(p, d);
2204 writel(0, &sdr_scc_mgr->update);
2208 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2209 * dq_in_delay values
2211 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2213 debug_cond(DLEVEL == 1,
2214 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2215 __func__, __LINE__, rw_group, found);
2217 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2218 r += NUM_RANKS_PER_SHADOW_REG) {
2219 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2220 writel(0, &sdr_scc_mgr->update);
2231 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2232 * @rw_group: Read/Write Group
2233 * @test_bgn: Rank at which the test begins
2234 * @use_read_test: Perform a read test
2235 * @update_fom: Update FOM
2237 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2241 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2242 const int use_read_test,
2243 const int update_fom)
2246 int ret, grp_calibrated;
2250 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2251 * Read per-bit deskew can be done on a per shadow register basis.
2254 for (rank_bgn = 0, sr = 0;
2255 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2256 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2257 /* Check if this set of ranks should be skipped entirely. */
2258 if (param->skip_shadow_regs[sr])
2261 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2271 if (!grp_calibrated)
2278 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2279 * @rw_group: Read/Write Group
2280 * @test_bgn: Rank at which the test begins
2282 * Stage 1: Calibrate the read valid prediction FIFO.
2284 * This function implements UniPHY calibration Stage 1, as explained in
2285 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2287 * - read valid prediction will consist of finding:
2288 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2289 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2290 * - we also do a per-bit deskew on the DQ lines.
2292 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2295 uint32_t dtaps_per_ptap;
2296 uint32_t failed_substage;
2300 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2302 /* Update info for sims */
2303 reg_file_set_group(rw_group);
2304 reg_file_set_stage(CAL_STAGE_VFIFO);
2305 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2307 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2309 /* USER Determine number of delay taps for each phase tap. */
2310 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2311 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2313 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2315 * In RLDRAMX we may be messing the delay of pins in
2316 * the same write rw_group but outside of the current read
2317 * the rw_group, but that's ok because we haven't calibrated
2321 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2325 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2326 /* 1) Guaranteed Write */
2327 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2331 /* 2) DQS Enable Calibration */
2332 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2335 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2339 /* 3) Centering DQ/DQS */
2341 * If doing read after write calibration, do not update
2342 * FOM now. Do it then.
2344 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2347 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2356 /* Calibration Stage 1 failed. */
2357 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2360 /* Calibration Stage 1 completed OK. */
2363 * Reset the delay chains back to zero if they have moved > 1
2364 * (check for > 1 because loop will increase d even when pass in
2368 scc_mgr_zero_group(rw_group, 1);
2373 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2374 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2377 uint32_t rank_bgn, sr;
2378 uint32_t grp_calibrated;
2379 uint32_t write_group;
2381 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2383 /* update info for sims */
2385 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2386 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2388 write_group = read_group;
2390 /* update info for sims */
2391 reg_file_set_group(read_group);
2394 /* Read per-bit deskew can be done on a per shadow register basis */
2395 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2396 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2397 /* Determine if this set of ranks should be skipped entirely */
2398 if (!param->skip_shadow_regs[sr]) {
2399 /* This is the last calibration round, update FOM here */
2400 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2411 if (grp_calibrated == 0) {
2412 set_failing_group_stage(write_group,
2413 CAL_STAGE_VFIFO_AFTER_WRITES,
2414 CAL_SUBSTAGE_VFIFO_CENTER);
2421 /* Calibrate LFIFO to find smallest read latency */
2422 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2427 debug("%s:%d\n", __func__, __LINE__);
2429 /* update info for sims */
2430 reg_file_set_stage(CAL_STAGE_LFIFO);
2431 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2433 /* Load up the patterns used by read calibration for all ranks */
2434 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2438 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2439 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2440 __func__, __LINE__, gbl->curr_read_lat);
2442 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2450 /* reduce read latency and see if things are working */
2452 gbl->curr_read_lat--;
2453 } while (gbl->curr_read_lat > 0);
2455 /* reset the fifos to get pointers to known state */
2457 writel(0, &phy_mgr_cmd->fifo_reset);
2460 /* add a fudge factor to the read latency that was determined */
2461 gbl->curr_read_lat += 2;
2462 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2463 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2464 read_lat=%u\n", __func__, __LINE__,
2465 gbl->curr_read_lat);
2468 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2469 CAL_SUBSTAGE_READ_LATENCY);
2471 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2472 read_lat=%u\n", __func__, __LINE__,
2473 gbl->curr_read_lat);
2479 * issue write test command.
2480 * two variants are provided. one that just tests a write pattern and
2481 * another that tests datamask functionality.
2483 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2486 uint32_t mcc_instruction;
2487 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2488 ENABLE_SUPER_QUICK_CALIBRATION);
2489 uint32_t rw_wl_nop_cycles;
2493 * Set counter and jump addresses for the right
2494 * number of NOP cycles.
2495 * The number of supported NOP cycles can range from -1 to infinity
2496 * Three different cases are handled:
2498 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2499 * mechanism will be used to insert the right number of NOPs
2501 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2502 * issuing the write command will jump straight to the
2503 * micro-instruction that turns on DQS (for DDRx), or outputs write
2504 * data (for RLD), skipping
2505 * the NOP micro-instruction all together
2507 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2508 * turned on in the same micro-instruction that issues the write
2509 * command. Then we need
2510 * to directly jump to the micro-instruction that sends out the data
2512 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2513 * (2 and 3). One jump-counter (0) is used to perform multiple
2514 * write-read operations.
2515 * one counter left to issue this command in "multiple-group" mode
2518 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2520 if (rw_wl_nop_cycles == -1) {
2522 * CNTR 2 - We want to execute the special write operation that
2523 * turns on DQS right away and then skip directly to the
2524 * instruction that sends out the data. We set the counter to a
2525 * large number so that the jump is always taken.
2527 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2529 /* CNTR 3 - Not used */
2531 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2532 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2533 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2534 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2535 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2537 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2538 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2539 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2540 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2541 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2543 } else if (rw_wl_nop_cycles == 0) {
2545 * CNTR 2 - We want to skip the NOP operation and go straight
2546 * to the DQS enable instruction. We set the counter to a large
2547 * number so that the jump is always taken.
2549 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2551 /* CNTR 3 - Not used */
2553 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2554 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2555 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2557 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2558 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2559 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2563 * CNTR 2 - In this case we want to execute the next instruction
2564 * and NOT take the jump. So we set the counter to 0. The jump
2565 * address doesn't count.
2567 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2568 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2571 * CNTR 3 - Set the nop counter to the number of cycles we
2572 * need to loop for, minus 1.
2574 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2576 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2577 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2578 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2580 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2581 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2582 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2586 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2587 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2589 if (quick_write_mode)
2590 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2592 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2594 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2597 * CNTR 1 - This is used to ensure enough time elapses
2598 * for read data to come back.
2600 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2603 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2604 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2606 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2607 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2610 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2611 writel(mcc_instruction, addr + (group << 2));
2614 /* Test writes, can check for a single bit pass or multiple bit pass */
2615 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2616 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2617 uint32_t *bit_chk, uint32_t all_ranks)
2620 uint32_t correct_mask_vg;
2621 uint32_t tmp_bit_chk;
2623 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2624 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2625 uint32_t addr_rw_mgr;
2626 uint32_t base_rw_mgr;
2628 *bit_chk = param->write_correct_mask;
2629 correct_mask_vg = param->write_correct_mask_vg;
2631 for (r = rank_bgn; r < rank_end; r++) {
2632 if (param->skip_ranks[r]) {
2633 /* request to skip the rank */
2638 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2641 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2642 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2643 /* reset the fifos to get pointers to known state */
2644 writel(0, &phy_mgr_cmd->fifo_reset);
2646 tmp_bit_chk = tmp_bit_chk <<
2647 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2648 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2649 rw_mgr_mem_calibrate_write_test_issue(write_group *
2650 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2653 base_rw_mgr = readl(addr_rw_mgr);
2654 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2658 *bit_chk &= tmp_bit_chk;
2662 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2663 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2664 %u => %lu", write_group, use_dm,
2665 *bit_chk, param->write_correct_mask,
2666 (long unsigned int)(*bit_chk ==
2667 param->write_correct_mask));
2668 return *bit_chk == param->write_correct_mask;
2670 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2671 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2672 write_group, use_dm, *bit_chk);
2673 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2674 (long unsigned int)(*bit_chk != 0));
2675 return *bit_chk != 0x00;
2680 * center all windows. do per-bit-deskew to possibly increase size of
2683 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2684 uint32_t write_group, uint32_t test_bgn)
2686 uint32_t i, p, min_index;
2689 * Store these as signed since there are comparisons with
2693 uint32_t sticky_bit_chk;
2694 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2695 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2697 int32_t mid_min, orig_mid_min;
2698 int32_t new_dqs, start_dqs, shift_dq;
2699 int32_t dq_margin, dqs_margin, dm_margin;
2701 uint32_t temp_dq_out1_delay;
2704 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2708 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2709 start_dqs = readl(addr +
2710 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2712 /* per-bit deskew */
2715 * set the left and right edge of each bit to an illegal value
2716 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2719 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2720 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2721 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2724 /* Search for the left edge of the window for each bit */
2725 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2726 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2728 writel(0, &sdr_scc_mgr->update);
2731 * Stop searching when the read test doesn't pass AND when
2732 * we've seen a passing read on every bit.
2734 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2735 0, PASS_ONE_BIT, &bit_chk, 0);
2736 sticky_bit_chk = sticky_bit_chk | bit_chk;
2737 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2738 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2739 == %u && %u [bit_chk= %u ]\n",
2740 d, sticky_bit_chk, param->write_correct_mask,
2746 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2749 * Remember a passing test as the
2755 * If a left edge has not been seen
2756 * yet, then a future passing test will
2757 * mark this edge as the right edge.
2760 IO_IO_OUT1_DELAY_MAX + 1) {
2761 right_edge[i] = -(d + 1);
2764 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2765 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2766 (int)(bit_chk & 1), i, left_edge[i]);
2767 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2769 bit_chk = bit_chk >> 1;
2774 /* Reset DQ delay chains to 0 */
2775 scc_mgr_apply_group_dq_out1_delay(0);
2777 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2778 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2779 %d right_edge[%u]: %d\n", __func__, __LINE__,
2780 i, left_edge[i], i, right_edge[i]);
2783 * Check for cases where we haven't found the left edge,
2784 * which makes our assignment of the the right edge invalid.
2785 * Reset it to the illegal value.
2787 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2788 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2789 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2790 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2791 right_edge[%u]: %d\n", __func__, __LINE__,
2796 * Reset sticky bit (except for bits where we have
2797 * seen the left edge).
2799 sticky_bit_chk = sticky_bit_chk << 1;
2800 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2801 sticky_bit_chk = sticky_bit_chk | 1;
2807 /* Search for the right edge of the window for each bit */
2808 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2809 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2812 writel(0, &sdr_scc_mgr->update);
2815 * Stop searching when the read test doesn't pass AND when
2816 * we've seen a passing read on every bit.
2818 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2819 0, PASS_ONE_BIT, &bit_chk, 0);
2821 sticky_bit_chk = sticky_bit_chk | bit_chk;
2822 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2824 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2825 %u && %u\n", d, sticky_bit_chk,
2826 param->write_correct_mask, stop);
2830 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2832 /* d = 0 failed, but it passed when
2833 testing the left edge, so it must be
2834 marginal, set it to -1 */
2835 if (right_edge[i] ==
2836 IO_IO_OUT1_DELAY_MAX + 1 &&
2838 IO_IO_OUT1_DELAY_MAX + 1) {
2845 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2848 * Remember a passing test as
2855 * If a right edge has not
2856 * been seen yet, then a future
2857 * passing test will mark this
2858 * edge as the left edge.
2860 if (right_edge[i] ==
2861 IO_IO_OUT1_DELAY_MAX + 1)
2862 left_edge[i] = -(d + 1);
2865 * d = 0 failed, but it passed
2866 * when testing the left edge,
2867 * so it must be marginal, set
2870 if (right_edge[i] ==
2871 IO_IO_OUT1_DELAY_MAX + 1 &&
2873 IO_IO_OUT1_DELAY_MAX + 1)
2876 * If a right edge has not been
2877 * seen yet, then a future
2878 * passing test will mark this
2879 * edge as the left edge.
2881 else if (right_edge[i] ==
2882 IO_IO_OUT1_DELAY_MAX +
2884 left_edge[i] = -(d + 1);
2887 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2888 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2889 (int)(bit_chk & 1), i, left_edge[i]);
2890 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2892 bit_chk = bit_chk >> 1;
2897 /* Check that all bits have a window */
2898 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2899 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2900 %d right_edge[%u]: %d", __func__, __LINE__,
2901 i, left_edge[i], i, right_edge[i]);
2902 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2903 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2904 set_failing_group_stage(test_bgn + i,
2906 CAL_SUBSTAGE_WRITES_CENTER);
2911 /* Find middle of window for each DQ bit */
2912 mid_min = left_edge[0] - right_edge[0];
2914 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2915 mid = left_edge[i] - right_edge[i];
2916 if (mid < mid_min) {
2923 * -mid_min/2 represents the amount that we need to move DQS.
2924 * If mid_min is odd and positive we'll need to add one to
2925 * make sure the rounding in further calculations is correct
2926 * (always bias to the right), so just add 1 for all positive values.
2930 mid_min = mid_min / 2;
2931 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2934 /* Determine the amount we can change DQS (which is -mid_min) */
2935 orig_mid_min = mid_min;
2936 new_dqs = start_dqs;
2938 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2939 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2940 /* Initialize data for export structures */
2941 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2942 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2944 /* add delay to bring centre of all DQ windows to the same "level" */
2945 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2946 /* Use values before divide by 2 to reduce round off error */
2947 shift_dq = (left_edge[i] - right_edge[i] -
2948 (left_edge[min_index] - right_edge[min_index]))/2 +
2949 (orig_mid_min - mid_min);
2951 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2952 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2954 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2955 temp_dq_out1_delay = readl(addr + (i << 2));
2956 if (shift_dq + (int32_t)temp_dq_out1_delay >
2957 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2958 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2959 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2960 shift_dq = -(int32_t)temp_dq_out1_delay;
2962 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2964 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2967 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2968 left_edge[i] - shift_dq + (-mid_min),
2969 right_edge[i] + shift_dq - (-mid_min));
2970 /* To determine values for export structures */
2971 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2972 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2974 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2975 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2979 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2980 writel(0, &sdr_scc_mgr->update);
2983 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2986 * set the left and right edge of each bit to an illegal value,
2987 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2989 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2990 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2991 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2992 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2993 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2994 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2995 int32_t win_best = 0;
2997 /* Search for the/part of the window with DM shift */
2998 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2999 scc_mgr_apply_group_dm_out1_delay(d);
3000 writel(0, &sdr_scc_mgr->update);
3002 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3003 PASS_ALL_BITS, &bit_chk,
3005 /* USE Set current end of the window */
3008 * If a starting edge of our window has not been seen
3009 * this is our current start of the DM window.
3011 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3015 * If current window is bigger than best seen.
3016 * Set best seen to be current window.
3018 if ((end_curr-bgn_curr+1) > win_best) {
3019 win_best = end_curr-bgn_curr+1;
3020 bgn_best = bgn_curr;
3021 end_best = end_curr;
3024 /* We just saw a failing test. Reset temp edge */
3025 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3026 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3031 /* Reset DM delay chains to 0 */
3032 scc_mgr_apply_group_dm_out1_delay(0);
3035 * Check to see if the current window nudges up aganist 0 delay.
3036 * If so we need to continue the search by shifting DQS otherwise DQS
3037 * search begins as a new search. */
3038 if (end_curr != 0) {
3039 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3040 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3043 /* Search for the/part of the window with DQS shifts */
3044 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3046 * Note: This only shifts DQS, so are we limiting ourselve to
3047 * width of DQ unnecessarily.
3049 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3052 writel(0, &sdr_scc_mgr->update);
3053 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3054 PASS_ALL_BITS, &bit_chk,
3056 /* USE Set current end of the window */
3059 * If a beginning edge of our window has not been seen
3060 * this is our current begin of the DM window.
3062 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3066 * If current window is bigger than best seen. Set best
3067 * seen to be current window.
3069 if ((end_curr-bgn_curr+1) > win_best) {
3070 win_best = end_curr-bgn_curr+1;
3071 bgn_best = bgn_curr;
3072 end_best = end_curr;
3075 /* We just saw a failing test. Reset temp edge */
3076 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3077 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3079 /* Early exit optimization: if ther remaining delay
3080 chain space is less than already seen largest window
3083 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3089 /* assign left and right edge for cal and reporting; */
3090 left_edge[0] = -1*bgn_best;
3091 right_edge[0] = end_best;
3093 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3094 __LINE__, left_edge[0], right_edge[0]);
3096 /* Move DQS (back to orig) */
3097 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3101 /* Find middle of window for the DM bit */
3102 mid = (left_edge[0] - right_edge[0]) / 2;
3104 /* only move right, since we are not moving DQS/DQ */
3108 /* dm_marign should fail if we never find a window */
3112 dm_margin = left_edge[0] - mid;
3114 scc_mgr_apply_group_dm_out1_delay(mid);
3115 writel(0, &sdr_scc_mgr->update);
3117 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3118 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3119 right_edge[0], mid, dm_margin);
3121 gbl->fom_out += dq_margin + dqs_margin;
3123 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3124 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3125 dq_margin, dqs_margin, dm_margin);
3128 * Do not remove this line as it makes sure all of our
3129 * decisions have been applied.
3131 writel(0, &sdr_scc_mgr->update);
3132 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3135 /* calibrate the write operations */
3136 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3139 /* update info for sims */
3140 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3142 reg_file_set_stage(CAL_STAGE_WRITES);
3143 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3145 reg_file_set_group(g);
3147 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3148 set_failing_group_stage(g, CAL_STAGE_WRITES,
3149 CAL_SUBSTAGE_WRITES_CENTER);
3157 * mem_precharge_and_activate() - Precharge all banks and activate
3159 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3161 static void mem_precharge_and_activate(void)
3165 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3166 /* Test if the rank should be skipped. */
3167 if (param->skip_ranks[r])
3171 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3173 /* Precharge all banks. */
3174 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3175 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3177 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3178 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3179 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3181 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3182 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3183 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3185 /* Activate rows. */
3186 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3187 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3192 * mem_init_latency() - Configure memory RLAT and WLAT settings
3194 * Configure memory RLAT and WLAT parameters.
3196 static void mem_init_latency(void)
3199 * For AV/CV, LFIFO is hardened and always runs at full rate
3200 * so max latency in AFI clocks, used here, is correspondingly
3203 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3206 debug("%s:%d\n", __func__, __LINE__);
3209 * Read in write latency.
3210 * WL for Hard PHY does not include additive latency.
3212 wlat = readl(&data_mgr->t_wl_add);
3213 wlat += readl(&data_mgr->mem_t_add);
3215 gbl->rw_wl_nop_cycles = wlat - 1;
3217 /* Read in readl latency. */
3218 rlat = readl(&data_mgr->t_rl_add);
3220 /* Set a pretty high read latency initially. */
3221 gbl->curr_read_lat = rlat + 16;
3222 if (gbl->curr_read_lat > max_latency)
3223 gbl->curr_read_lat = max_latency;
3225 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3227 /* Advertise write latency. */
3228 writel(wlat, &phy_mgr_cfg->afi_wlat);
3232 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3234 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3236 static void mem_skip_calibrate(void)
3238 uint32_t vfifo_offset;
3241 debug("%s:%d\n", __func__, __LINE__);
3242 /* Need to update every shadow register set used by the interface */
3243 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3244 r += NUM_RANKS_PER_SHADOW_REG) {
3246 * Set output phase alignment settings appropriate for
3249 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3250 scc_mgr_set_dqs_en_phase(i, 0);
3251 #if IO_DLL_CHAIN_LENGTH == 6
3252 scc_mgr_set_dqdqs_output_phase(i, 6);
3254 scc_mgr_set_dqdqs_output_phase(i, 7);
3259 * Write data arrives to the I/O two cycles before write
3260 * latency is reached (720 deg).
3261 * -> due to bit-slip in a/c bus
3262 * -> to allow board skew where dqs is longer than ck
3263 * -> how often can this happen!?
3264 * -> can claim back some ptaps for high freq
3265 * support if we can relax this, but i digress...
3267 * The write_clk leads mem_ck by 90 deg
3268 * The minimum ptap of the OPA is 180 deg
3269 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3270 * The write_clk is always delayed by 2 ptaps
3272 * Hence, to make DQS aligned to CK, we need to delay
3274 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3276 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3277 * gives us the number of ptaps, which simplies to:
3279 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3281 scc_mgr_set_dqdqs_output_phase(i,
3282 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3284 writel(0xff, &sdr_scc_mgr->dqs_ena);
3285 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3287 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3288 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3289 SCC_MGR_GROUP_COUNTER_OFFSET);
3291 writel(0xff, &sdr_scc_mgr->dq_ena);
3292 writel(0xff, &sdr_scc_mgr->dm_ena);
3293 writel(0, &sdr_scc_mgr->update);
3296 /* Compensate for simulation model behaviour */
3297 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3298 scc_mgr_set_dqs_bus_in_delay(i, 10);
3299 scc_mgr_load_dqs(i);
3301 writel(0, &sdr_scc_mgr->update);
3304 * ArriaV has hard FIFOs that can only be initialized by incrementing
3307 vfifo_offset = CALIB_VFIFO_OFFSET;
3308 for (j = 0; j < vfifo_offset; j++)
3309 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3310 writel(0, &phy_mgr_cmd->fifo_reset);
3313 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3314 * setting from generation-time constant.
3316 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3317 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3321 * mem_calibrate() - Memory calibration entry point.
3323 * Perform memory calibration.
3325 static uint32_t mem_calibrate(void)
3328 uint32_t rank_bgn, sr;
3329 uint32_t write_group, write_test_bgn;
3330 uint32_t read_group, read_test_bgn;
3331 uint32_t run_groups, current_run;
3332 uint32_t failing_groups = 0;
3333 uint32_t group_failed = 0;
3335 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3336 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3338 debug("%s:%d\n", __func__, __LINE__);
3340 /* Initialize the data settings */
3341 gbl->error_substage = CAL_SUBSTAGE_NIL;
3342 gbl->error_stage = CAL_STAGE_NIL;
3343 gbl->error_group = 0xff;
3347 /* Initialize WLAT and RLAT. */
3350 /* Initialize bit slips. */
3351 mem_precharge_and_activate();
3353 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3354 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3355 SCC_MGR_GROUP_COUNTER_OFFSET);
3356 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3358 scc_mgr_set_hhp_extras();
3360 scc_set_bypass_mode(i);
3363 /* Calibration is skipped. */
3364 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3366 * Set VFIFO and LFIFO to instant-on settings in skip
3369 mem_skip_calibrate();
3372 * Do not remove this line as it makes sure all of our
3373 * decisions have been applied.
3375 writel(0, &sdr_scc_mgr->update);
3379 /* Calibration is not skipped. */
3380 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3382 * Zero all delay chain/phase settings for all
3383 * groups and all shadow register sets.
3387 run_groups = ~param->skip_groups;
3389 for (write_group = 0, write_test_bgn = 0; write_group
3390 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3391 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3393 /* Initialize the group failure */
3396 current_run = run_groups & ((1 <<
3397 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3398 run_groups = run_groups >>
3399 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3401 if (current_run == 0)
3404 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3405 SCC_MGR_GROUP_COUNTER_OFFSET);
3406 scc_mgr_zero_group(write_group, 0);
3408 for (read_group = write_group * rwdqs_ratio,
3410 read_group < (write_group + 1) * rwdqs_ratio;
3412 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3413 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3416 /* Calibrate the VFIFO */
3417 if (rw_mgr_mem_calibrate_vfifo(read_group,
3421 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3424 /* The group failed, we're done. */
3428 /* Calibrate the output side */
3429 for (rank_bgn = 0, sr = 0;
3430 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3431 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3432 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3435 /* Not needed in quick mode! */
3436 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3440 * Determine if this set of ranks
3441 * should be skipped entirely.
3443 if (param->skip_shadow_regs[sr])
3446 /* Calibrate WRITEs */
3447 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3448 write_group, write_test_bgn))
3452 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3456 /* Some group failed, we're done. */
3460 for (read_group = write_group * rwdqs_ratio,
3462 read_group < (write_group + 1) * rwdqs_ratio;
3464 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3465 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3468 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3472 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3475 /* The group failed, we're done. */
3479 /* No group failed, continue as usual. */
3482 grp_failed: /* A group failed, increment the counter. */
3487 * USER If there are any failing groups then report
3490 if (failing_groups != 0)
3493 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3497 * If we're skipping groups as part of debug,
3498 * don't calibrate LFIFO.
3500 if (param->skip_groups != 0)
3503 /* Calibrate the LFIFO */
3504 if (!rw_mgr_mem_calibrate_lfifo())
3509 * Do not remove this line as it makes sure all of our decisions
3510 * have been applied.
3512 writel(0, &sdr_scc_mgr->update);
3517 * run_mem_calibrate() - Perform memory calibration
3519 * This function triggers the entire memory calibration procedure.
3521 static int run_mem_calibrate(void)
3525 debug("%s:%d\n", __func__, __LINE__);
3527 /* Reset pass/fail status shown on afi_cal_success/fail */
3528 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3530 /* Stop tracking manager. */
3531 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3533 phy_mgr_initialize();
3534 rw_mgr_mem_initialize();
3536 /* Perform the actual memory calibration. */
3537 pass = mem_calibrate();
3539 mem_precharge_and_activate();
3540 writel(0, &phy_mgr_cmd->fifo_reset);
3543 rw_mgr_mem_handoff();
3545 * In Hard PHY this is a 2-bit control:
3547 * 1: DDIO Mux Select
3549 writel(0x2, &phy_mgr_cfg->mux_sel);
3551 /* Start tracking manager. */
3552 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3558 * debug_mem_calibrate() - Report result of memory calibration
3559 * @pass: Value indicating whether calibration passed or failed
3561 * This function reports the results of the memory calibration
3562 * and writes debug information into the register file.
3564 static void debug_mem_calibrate(int pass)
3566 uint32_t debug_info;
3569 printf("%s: CALIBRATION PASSED\n", __FILE__);
3574 if (gbl->fom_in > 0xff)
3577 if (gbl->fom_out > 0xff)
3578 gbl->fom_out = 0xff;
3580 /* Update the FOM in the register file */
3581 debug_info = gbl->fom_in;
3582 debug_info |= gbl->fom_out << 8;
3583 writel(debug_info, &sdr_reg_file->fom);
3585 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3586 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3588 printf("%s: CALIBRATION FAILED\n", __FILE__);
3590 debug_info = gbl->error_stage;
3591 debug_info |= gbl->error_substage << 8;
3592 debug_info |= gbl->error_group << 16;
3594 writel(debug_info, &sdr_reg_file->failing_stage);
3595 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3596 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3598 /* Update the failing group/stage in the register file */
3599 debug_info = gbl->error_stage;
3600 debug_info |= gbl->error_substage << 8;
3601 debug_info |= gbl->error_group << 16;
3602 writel(debug_info, &sdr_reg_file->failing_stage);
3605 printf("%s: Calibration complete\n", __FILE__);
3609 * hc_initialize_rom_data() - Initialize ROM data
3611 * Initialize ROM data.
3613 static void hc_initialize_rom_data(void)
3617 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3618 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3619 writel(inst_rom_init[i], addr + (i << 2));
3621 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3622 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3623 writel(ac_rom_init[i], addr + (i << 2));
3627 * initialize_reg_file() - Initialize SDR register file
3629 * Initialize SDR register file.
3631 static void initialize_reg_file(void)
3633 /* Initialize the register file with the correct data */
3634 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3635 writel(0, &sdr_reg_file->debug_data_addr);
3636 writel(0, &sdr_reg_file->cur_stage);
3637 writel(0, &sdr_reg_file->fom);
3638 writel(0, &sdr_reg_file->failing_stage);
3639 writel(0, &sdr_reg_file->debug1);
3640 writel(0, &sdr_reg_file->debug2);
3644 * initialize_hps_phy() - Initialize HPS PHY
3646 * Initialize HPS PHY.
3648 static void initialize_hps_phy(void)
3652 * Tracking also gets configured here because it's in the
3655 uint32_t trk_sample_count = 7500;
3656 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3658 * Format is number of outer loops in the 16 MSB, sample
3663 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3664 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3665 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3666 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3667 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3668 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3670 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3671 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3673 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3674 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3676 writel(reg, &sdr_ctrl->phy_ctrl0);
3679 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3681 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3682 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3683 trk_long_idle_sample_count);
3684 writel(reg, &sdr_ctrl->phy_ctrl1);
3687 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3688 trk_long_idle_sample_count >>
3689 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3690 writel(reg, &sdr_ctrl->phy_ctrl2);
3694 * initialize_tracking() - Initialize tracking
3696 * Initialize the register file with usable initial data.
3698 static void initialize_tracking(void)
3701 * Initialize the register file with the correct data.
3702 * Compute usable version of value in case we skip full
3703 * computation later.
3705 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3706 &sdr_reg_file->dtaps_per_ptap);
3708 /* trk_sample_count */
3709 writel(7500, &sdr_reg_file->trk_sample_count);
3711 /* longidle outer loop [15:0] */
3712 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3715 * longidle sample count [31:24]
3716 * trfc, worst case of 933Mhz 4Gb [23:16]
3717 * trcd, worst case [15:8]
3720 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3721 &sdr_reg_file->delays);
3724 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3725 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3726 &sdr_reg_file->trk_rw_mgr_addr);
3728 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3729 &sdr_reg_file->trk_read_dqs_width);
3732 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3733 &sdr_reg_file->trk_rfsh);
3736 int sdram_calibration_full(void)
3738 struct param_type my_param;
3739 struct gbl_type my_gbl;
3742 memset(&my_param, 0, sizeof(my_param));
3743 memset(&my_gbl, 0, sizeof(my_gbl));
3748 /* Set the calibration enabled by default */
3749 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3751 * Only sweep all groups (regardless of fail state) by default
3752 * Set enabled read test by default.
3754 #if DISABLE_GUARANTEED_READ
3755 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3757 /* Initialize the register file */
3758 initialize_reg_file();
3760 /* Initialize any PHY CSR */
3761 initialize_hps_phy();
3763 scc_mgr_initialize();
3765 initialize_tracking();
3767 printf("%s: Preparing to start memory calibration\n", __FILE__);
3769 debug("%s:%d\n", __func__, __LINE__);
3770 debug_cond(DLEVEL == 1,
3771 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3772 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3773 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3774 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3775 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3776 debug_cond(DLEVEL == 1,
3777 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3778 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3779 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3780 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3781 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3782 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3783 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3784 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3785 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3786 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3787 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3788 IO_IO_OUT2_DELAY_MAX);
3789 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3790 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3792 hc_initialize_rom_data();
3794 /* update info for sims */
3795 reg_file_set_stage(CAL_STAGE_NIL);
3796 reg_file_set_group(0);
3799 * Load global needed for those actions that require
3800 * some dynamic calibration support.
3802 dyn_calib_steps = STATIC_CALIB_STEPS;
3804 * Load global to allow dynamic selection of delay loop settings
3805 * based on calibration mode.
3807 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3808 skip_delay_mask = 0xff;
3810 skip_delay_mask = 0x0;
3812 pass = run_mem_calibrate();
3813 debug_mem_calibrate(pass);