2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
11 / rwcfg->mem_if_write_dqs_width)
12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
13 / rwcfg->mem_if_write_dqs_width)
15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
16 / rwcfg->mem_if_write_dqs_width)
17 #define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
26 #define NUM_SHADOW_REGS 1
28 #define RW_MGR_RANK_NONE 0xFF
29 #define RW_MGR_RANK_ALL 0x00
31 #define RW_MGR_ODT_MODE_OFF 0
32 #define RW_MGR_ODT_MODE_READ_WRITE 1
34 #define NUM_CALIB_REPEAT 1
36 #define NUM_READ_TESTS 7
37 #define NUM_READ_PB_TESTS 7
38 #define NUM_WRITE_TESTS 15
39 #define NUM_WRITE_PB_TESTS 31
41 #define PASS_ALL_BITS 1
42 #define PASS_ONE_BIT 0
44 /* calibration stages */
45 #define CAL_STAGE_NIL 0
46 #define CAL_STAGE_VFIFO 1
47 #define CAL_STAGE_WLEVEL 2
48 #define CAL_STAGE_LFIFO 3
49 #define CAL_STAGE_WRITES 4
50 #define CAL_STAGE_FULLTEST 5
51 #define CAL_STAGE_REFRESH 6
52 #define CAL_STAGE_CAL_SKIPPED 7
53 #define CAL_STAGE_CAL_ABORTED 8
54 #define CAL_STAGE_VFIFO_AFTER_WRITES 9
56 /* calibration substages */
57 #define CAL_SUBSTAGE_NIL 0
58 #define CAL_SUBSTAGE_GUARANTEED_READ 1
59 #define CAL_SUBSTAGE_DQS_EN_PHASE 2
60 #define CAL_SUBSTAGE_VFIFO_CENTER 3
61 #define CAL_SUBSTAGE_WORKING_DELAY 1
62 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
63 #define CAL_SUBSTAGE_WLEVEL_COPY 3
64 #define CAL_SUBSTAGE_WRITES_CENTER 1
65 #define CAL_SUBSTAGE_READ_LATENCY 1
66 #define CAL_SUBSTAGE_REFRESH 1
68 /* length of VFIFO, from SW_MACROS */
69 #define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
71 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
72 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
73 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
74 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
75 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
76 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
77 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
78 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900
80 /* HHP-HPS-specific versions of some commands */
81 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600
82 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800
83 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00
84 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
85 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
87 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0)
88 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000)
89 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000)
90 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
91 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
93 #define PHY_MGR_CAL_RESET (0)
94 #define PHY_MGR_CAL_SUCCESS (1)
95 #define PHY_MGR_CAL_FAIL (2)
97 #define CALIB_SKIP_DELAY_LOOPS (1 << 0)
98 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
99 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
100 #define CALIB_SKIP_VFIFO (1 << 3)
101 #define CALIB_SKIP_LFIFO (1 << 4)
102 #define CALIB_SKIP_WLEVEL (1 << 5)
103 #define CALIB_SKIP_WRITES (1 << 6)
104 #define CALIB_SKIP_FULL_TEST (1 << 7)
105 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
106 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
107 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
108 #define CALIB_IN_RTL_SIM (1 << 8)
110 /* Scan chain manager command addresses */
111 #define READ_SCC_OCT_OUT2_DELAY 0
112 #define READ_SCC_DQ_OUT2_DELAY 0
113 #define READ_SCC_DQS_IO_OUT2_DELAY 0
114 #define READ_SCC_DM_IO_OUT2_DELAY 0
116 /* HHP-HPS-specific values */
117 #define SCC_MGR_HHP_EXTRAS_OFFSET 0
118 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
120 /* PHY Debug mode flag constants */
121 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
122 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
123 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
124 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
125 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
126 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
128 /* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
129 * otherwise, revert to defaults
130 * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 =
133 #ifdef TINIT_CNTR0_VAL
134 #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
136 #define SEQ_TINIT_CNTR0_VAL 0
139 #ifdef TINIT_CNTR1_VAL
140 #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
142 #define SEQ_TINIT_CNTR1_VAL 202
145 #ifdef TINIT_CNTR2_VAL
146 #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
148 #define SEQ_TINIT_CNTR2_VAL 131
152 /* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 =
155 #ifdef TRESET_CNTR0_VAL
156 #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
158 #define SEQ_TRESET_CNTR0_VAL 2
161 #ifdef TRESET_CNTR1_VAL
162 #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
164 #define SEQ_TRESET_CNTR1_VAL 252
167 #ifdef TRESET_CNTR2_VAL
168 #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
170 #define SEQ_TRESET_CNTR2_VAL 131
173 struct socfpga_sdr_rw_load_manager {
180 struct socfpga_sdr_rw_load_jump_manager {
187 struct socfpga_sdr_reg_file {
196 u32 trk_sample_count;
200 u32 trk_read_dqs_width;
204 /* parameter variable holder */
206 u32 read_correct_mask;
207 u32 read_correct_mask_vg;
208 u32 write_correct_mask;
209 u32 write_correct_mask_vg;
213 /* global variable holder */
215 uint32_t phy_debug_mode_flags;
217 /* current read latency */
219 uint32_t curr_read_lat;
223 uint32_t error_substage;
224 uint32_t error_stage;
225 uint32_t error_group;
227 /* figure-of-merit in, figure-of-merit out */
232 /*USER Number of RW Mgr NOP cycles between
233 write command and write data */
234 uint32_t rw_wl_nop_cycles;
237 struct socfpga_sdr_scc_mgr {
248 /* PHY manager configuration registers. */
249 struct socfpga_phy_mgr_cfg {
255 u32 vfifo_rd_en_ovrd;
260 /* PHY manager command addresses. */
261 struct socfpga_phy_mgr_cmd {
263 u32 inc_vfifo_hard_phy;
269 struct socfpga_data_mgr {
275 #endif /* _SEQUENCER_H_ */