drivers/ddr/fsl/interactive.c

   1 /*
   2  * Copyright 2010-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  *         York Sun [at freescale.com]
  12  */
  13
  14 #include <common.h>
  15 #include <cli.h>
  16 #include <linux/ctype.h>
  17 #include <asm/types.h>
  18 #include <asm/io.h>
  19
  20 #include <fsl_ddr_sdram.h>
  21 #include <fsl_ddr.h>
  22
  23 /* Option parameter Structures */
  24 struct options_string {
  25         const char *option_name;
  26         size_t offset;
  27         unsigned int size;
  28         const char printhex;
  29 };
  30
  31 static unsigned int picos_to_mhz(unsigned int picos)
  32 {
  33         return 1000000 / picos;
  34 }
  35
  36 static void print_option_table(const struct options_string *table,
  37                          int table_size,
  38                          const void *base)
  39 {
  40         unsigned int i;
  41         unsigned int *ptr;
  42         unsigned long long *ptr_l;
  43
  44         for (i = 0; i < table_size; i++) {
  45                 switch (table[i].size) {
  46                 case 4:
  47                         ptr = (unsigned int *) (base + table[i].offset);
  48                         if (table[i].printhex) {
  49                                 printf("%s = 0x%08X\n",
  50                                         table[i].option_name, *ptr);
  51                         } else {
  52                                 printf("%s = %u\n",
  53                                         table[i].option_name, *ptr);
  54                         }
  55                         break;
  56                 case 8:
  57                         ptr_l = (unsigned long long *) (base + table[i].offset);
  58                         printf("%s = %llu\n",
  59                                 table[i].option_name, *ptr_l);
  60                         break;
  61                 default:
  62                         printf("Unrecognized size!\n");
  63                         break;
  64                 }
  65         }
  66 }
  67
  68 static int handle_option_table(const struct options_string *table,
  69                          int table_size,
  70                          void *base,
  71                          const char *opt,
  72                          const char *val)
  73 {
  74         unsigned int i;
  75         unsigned int value, *ptr;
  76         unsigned long long value_l, *ptr_l;
  77
  78         for (i = 0; i < table_size; i++) {
  79                 if (strcmp(table[i].option_name, opt) != 0)
  80                         continue;
  81                 switch (table[i].size) {
  82                 case 4:
  83                         value = simple_strtoul(val, NULL, 0);
  84                         ptr = base + table[i].offset;
  85                         *ptr = value;
  86                         break;
  87                 case 8:
  88                         value_l = simple_strtoull(val, NULL, 0);
  89                         ptr_l = base + table[i].offset;
  90                         *ptr_l = value_l;
  91                         break;
  92                 default:
  93                         printf("Unrecognized size!\n");
  94                         break;
  95                 }
  96                 return 1;
  97         }
  98
  99         return 0;
 100 }
 101
 102 static void fsl_ddr_generic_edit(void *pdata,
 103                            void *pend,
 104                            unsigned int element_size,
 105                            unsigned int element_num,
 106                            unsigned int value)
 107 {
 108         char *pcdata = (char *)pdata;           /* BIG ENDIAN ONLY */
 109
 110         pcdata += element_num * element_size;
 111         if ((pcdata + element_size) > (char *) pend) {
 112                 printf("trying to write past end of data\n");
 113                 return;
 114         }
 115
 116         switch (element_size) {
 117         case 1:
 118                 __raw_writeb(value, pcdata);
 119                 break;
 120         case 2:
 121                 __raw_writew(value, pcdata);
 122                 break;
 123         case 4:
 124                 __raw_writel(value, pcdata);
 125                 break;
 126         default:
 127                 printf("unexpected element size %u\n", element_size);
 128                 break;
 129         }
 130 }
 131
 132 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
 133                        unsigned int ctrl_num,
 134                        unsigned int dimm_num,
 135                        unsigned int element_num,
 136                        unsigned int value)
 137 {
 138         generic_spd_eeprom_t *pspd;
 139
 140         pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
 141         fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
 142 }
 143
 144 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
 145         sizeof((common_timing_params_t *)0)->x, 0}
 146
 147 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 148                                         unsigned int ctrl_num,
 149                                         const char *optname_str,
 150                                         const char *value_str)
 151 {
 152         common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
 153
 154         static const struct options_string options[] = {
 155                 COMMON_TIMING(tckmin_x_ps),
 156                 COMMON_TIMING(tckmax_ps),
 157                 COMMON_TIMING(taamin_ps),
 158                 COMMON_TIMING(trcd_ps),
 159                 COMMON_TIMING(trp_ps),
 160                 COMMON_TIMING(tras_ps),
 161
 162 #ifdef CONFIG_SYS_FSL_DDR4
 163                 COMMON_TIMING(trfc1_ps),
 164                 COMMON_TIMING(trfc2_ps),
 165                 COMMON_TIMING(trfc4_ps),
 166                 COMMON_TIMING(trrds_ps),
 167                 COMMON_TIMING(trrdl_ps),
 168                 COMMON_TIMING(tccdl_ps),
 169 #else
 170                 COMMON_TIMING(twtr_ps),
 171                 COMMON_TIMING(trfc_ps),
 172                 COMMON_TIMING(trrd_ps),
 173                 COMMON_TIMING(trtp_ps),
 174 #endif
 175                 COMMON_TIMING(twr_ps),
 176                 COMMON_TIMING(trc_ps),
 177                 COMMON_TIMING(refresh_rate_ps),
 178                 COMMON_TIMING(extended_op_srt),
 179 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 180                 COMMON_TIMING(tis_ps),
 181                 COMMON_TIMING(tih_ps),
 182                 COMMON_TIMING(tds_ps),
 183                 COMMON_TIMING(tdh_ps),
 184                 COMMON_TIMING(tdqsq_max_ps),
 185                 COMMON_TIMING(tqhs_ps),
 186 #endif
 187                 COMMON_TIMING(ndimms_present),
 188                 COMMON_TIMING(lowest_common_spd_caslat),
 189                 COMMON_TIMING(highest_common_derated_caslat),
 190                 COMMON_TIMING(additive_latency),
 191                 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
 192                 COMMON_TIMING(all_dimms_registered),
 193                 COMMON_TIMING(all_dimms_unbuffered),
 194                 COMMON_TIMING(all_dimms_ecc_capable),
 195                 COMMON_TIMING(total_mem),
 196                 COMMON_TIMING(base_address),
 197         };
 198         static const unsigned int n_opts = ARRAY_SIZE(options);
 199
 200         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 201                 return;
 202
 203         printf("Error: couldn't find option string %s\n", optname_str);
 204 }
 205
 206 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
 207         sizeof((dimm_params_t *)0)->x, 0}
 208
 209 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 210                                    unsigned int ctrl_num,
 211                                    unsigned int dimm_num,
 212                                    const char *optname_str,
 213                                    const char *value_str)
 214 {
 215         dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
 216
 217         static const struct options_string options[] = {
 218                 DIMM_PARM(n_ranks),
 219                 DIMM_PARM(data_width),
 220                 DIMM_PARM(primary_sdram_width),
 221                 DIMM_PARM(ec_sdram_width),
 222                 DIMM_PARM(registered_dimm),
 223                 DIMM_PARM(device_width),
 224
 225                 DIMM_PARM(n_row_addr),
 226                 DIMM_PARM(n_col_addr),
 227                 DIMM_PARM(edc_config),
 228 #ifdef CONFIG_SYS_FSL_DDR4
 229                 DIMM_PARM(bank_addr_bits),
 230                 DIMM_PARM(bank_group_bits),
 231 #else
 232                 DIMM_PARM(n_banks_per_sdram_device),
 233 #endif
 234                 DIMM_PARM(burst_lengths_bitmask),
 235                 DIMM_PARM(row_density),
 236
 237                 DIMM_PARM(tckmin_x_ps),
 238                 DIMM_PARM(tckmin_x_minus_1_ps),
 239                 DIMM_PARM(tckmin_x_minus_2_ps),
 240                 DIMM_PARM(tckmax_ps),
 241
 242                 DIMM_PARM(caslat_x),
 243                 DIMM_PARM(caslat_x_minus_1),
 244                 DIMM_PARM(caslat_x_minus_2),
 245
 246                 DIMM_PARM(caslat_lowest_derated),
 247
 248                 DIMM_PARM(trcd_ps),
 249                 DIMM_PARM(trp_ps),
 250                 DIMM_PARM(tras_ps),
 251 #ifdef CONFIG_SYS_FSL_DDR4
 252                 DIMM_PARM(trfc1_ps),
 253                 DIMM_PARM(trfc2_ps),
 254                 DIMM_PARM(trfc4_ps),
 255                 DIMM_PARM(trrds_ps),
 256                 DIMM_PARM(trrdl_ps),
 257                 DIMM_PARM(tccdl_ps),
 258 #else
 259                 DIMM_PARM(twr_ps),
 260                 DIMM_PARM(twtr_ps),
 261                 DIMM_PARM(trfc_ps),
 262                 DIMM_PARM(trrd_ps),
 263                 DIMM_PARM(trtp_ps),
 264 #endif
 265                 DIMM_PARM(trc_ps),
 266                 DIMM_PARM(refresh_rate_ps),
 267                 DIMM_PARM(extended_op_srt),
 268
 269 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 270                 DIMM_PARM(tis_ps),
 271                 DIMM_PARM(tih_ps),
 272                 DIMM_PARM(tds_ps),
 273                 DIMM_PARM(tdh_ps),
 274                 DIMM_PARM(tdqsq_max_ps),
 275                 DIMM_PARM(tqhs_ps),
 276 #endif
 277
 278                 DIMM_PARM(rank_density),
 279                 DIMM_PARM(capacity),
 280                 DIMM_PARM(base_address),
 281         };
 282
 283         static const unsigned int n_opts = ARRAY_SIZE(options);
 284
 285         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 286                 return;
 287
 288         printf("couldn't find option string %s\n", optname_str);
 289 }
 290
 291 static void print_dimm_parameters(const dimm_params_t *pdimm)
 292 {
 293         static const struct options_string options[] = {
 294                 DIMM_PARM(n_ranks),
 295                 DIMM_PARM(data_width),
 296                 DIMM_PARM(primary_sdram_width),
 297                 DIMM_PARM(ec_sdram_width),
 298                 DIMM_PARM(registered_dimm),
 299                 DIMM_PARM(device_width),
 300
 301                 DIMM_PARM(n_row_addr),
 302                 DIMM_PARM(n_col_addr),
 303                 DIMM_PARM(edc_config),
 304 #ifdef CONFIG_SYS_FSL_DDR4
 305                 DIMM_PARM(bank_addr_bits),
 306                 DIMM_PARM(bank_group_bits),
 307 #else
 308                 DIMM_PARM(n_banks_per_sdram_device),
 309 #endif
 310
 311                 DIMM_PARM(tckmin_x_ps),
 312                 DIMM_PARM(tckmin_x_minus_1_ps),
 313                 DIMM_PARM(tckmin_x_minus_2_ps),
 314                 DIMM_PARM(tckmax_ps),
 315
 316                 DIMM_PARM(caslat_x),
 317                 DIMM_PARM(taa_ps),
 318                 DIMM_PARM(caslat_x_minus_1),
 319                 DIMM_PARM(caslat_x_minus_2),
 320                 DIMM_PARM(caslat_lowest_derated),
 321
 322                 DIMM_PARM(trcd_ps),
 323                 DIMM_PARM(trp_ps),
 324                 DIMM_PARM(tras_ps),
 325 #ifdef CONFIG_SYS_FSL_DDR4
 326                 DIMM_PARM(trfc1_ps),
 327                 DIMM_PARM(trfc2_ps),
 328                 DIMM_PARM(trfc4_ps),
 329                 DIMM_PARM(trrds_ps),
 330                 DIMM_PARM(trrdl_ps),
 331                 DIMM_PARM(tccdl_ps),
 332 #else
 333                 DIMM_PARM(twr_ps),
 334                 DIMM_PARM(twtr_ps),
 335                 DIMM_PARM(trfc_ps),
 336                 DIMM_PARM(trrd_ps),
 337                 DIMM_PARM(trtp_ps),
 338 #endif
 339                 DIMM_PARM(trc_ps),
 340                 DIMM_PARM(refresh_rate_ps),
 341
 342 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 343                 DIMM_PARM(tis_ps),
 344                 DIMM_PARM(tih_ps),
 345                 DIMM_PARM(tds_ps),
 346                 DIMM_PARM(tdh_ps),
 347                 DIMM_PARM(tdqsq_max_ps),
 348                 DIMM_PARM(tqhs_ps),
 349 #endif
 350         };
 351         static const unsigned int n_opts = ARRAY_SIZE(options);
 352
 353         if (pdimm->n_ranks == 0) {
 354                 printf("DIMM not present\n");
 355                 return;
 356         }
 357         printf("DIMM organization parameters:\n");
 358         printf("module part name = %s\n", pdimm->mpart);
 359         printf("rank_density = %llu bytes (%llu megabytes)\n",
 360                pdimm->rank_density, pdimm->rank_density / 0x100000);
 361         printf("capacity = %llu bytes (%llu megabytes)\n",
 362                pdimm->capacity, pdimm->capacity / 0x100000);
 363         printf("burst_lengths_bitmask = %02X\n",
 364                pdimm->burst_lengths_bitmask);
 365         printf("base_addresss = %llu (%08llX %08llX)\n",
 366                pdimm->base_address,
 367                (pdimm->base_address >> 32),
 368                pdimm->base_address & 0xFFFFFFFF);
 369         print_option_table(options, n_opts, pdimm);
 370 }
 371
 372 static void print_lowest_common_dimm_parameters(
 373                 const common_timing_params_t *plcd_dimm_params)
 374 {
 375         static const struct options_string options[] = {
 376                 COMMON_TIMING(taamin_ps),
 377                 COMMON_TIMING(trcd_ps),
 378                 COMMON_TIMING(trp_ps),
 379                 COMMON_TIMING(tras_ps),
 380 #ifdef CONFIG_SYS_FSL_DDR4
 381                 COMMON_TIMING(trfc1_ps),
 382                 COMMON_TIMING(trfc2_ps),
 383                 COMMON_TIMING(trfc4_ps),
 384                 COMMON_TIMING(trrds_ps),
 385                 COMMON_TIMING(trrdl_ps),
 386                 COMMON_TIMING(tccdl_ps),
 387 #else
 388                 COMMON_TIMING(twtr_ps),
 389                 COMMON_TIMING(trfc_ps),
 390                 COMMON_TIMING(trrd_ps),
 391                 COMMON_TIMING(trtp_ps),
 392 #endif
 393                 COMMON_TIMING(twr_ps),
 394                 COMMON_TIMING(trc_ps),
 395                 COMMON_TIMING(refresh_rate_ps),
 396                 COMMON_TIMING(extended_op_srt),
 397 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 398                 COMMON_TIMING(tis_ps),
 399                 COMMON_TIMING(tih_ps),
 400                 COMMON_TIMING(tds_ps),
 401                 COMMON_TIMING(tdh_ps),
 402                 COMMON_TIMING(tdqsq_max_ps),
 403                 COMMON_TIMING(tqhs_ps),
 404 #endif
 405                 COMMON_TIMING(lowest_common_spd_caslat),
 406                 COMMON_TIMING(highest_common_derated_caslat),
 407                 COMMON_TIMING(additive_latency),
 408                 COMMON_TIMING(ndimms_present),
 409                 COMMON_TIMING(all_dimms_registered),
 410                 COMMON_TIMING(all_dimms_unbuffered),
 411                 COMMON_TIMING(all_dimms_ecc_capable),
 412         };
 413         static const unsigned int n_opts = ARRAY_SIZE(options);
 414
 415         /* Clock frequencies */
 416         printf("tckmin_x_ps = %u (%u MHz)\n",
 417                plcd_dimm_params->tckmin_x_ps,
 418                picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
 419         printf("tckmax_ps = %u (%u MHz)\n",
 420                plcd_dimm_params->tckmax_ps,
 421                picos_to_mhz(plcd_dimm_params->tckmax_ps));
 422         printf("all_dimms_burst_lengths_bitmask = %02X\n",
 423                plcd_dimm_params->all_dimms_burst_lengths_bitmask);
 424
 425         print_option_table(options, n_opts, plcd_dimm_params);
 426
 427         printf("total_mem = %llu (%llu megabytes)\n",
 428                plcd_dimm_params->total_mem,
 429                plcd_dimm_params->total_mem / 0x100000);
 430         printf("base_address = %llu (%llu megabytes)\n",
 431                plcd_dimm_params->base_address,
 432                plcd_dimm_params->base_address / 0x100000);
 433 }
 434
 435 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
 436         sizeof((memctl_options_t *)0)->x, 0}
 437 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
 438         offsetof(memctl_options_t, cs_local_opts[x].y), \
 439         sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
 440
 441 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 442                            unsigned int ctl_num,
 443                            const char *optname_str,
 444                            const char *value_str)
 445 {
 446         memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
 447         /*
 448          * This array all on the stack and *computed* each time this
 449          * function is rung.
 450          */
 451         static const struct options_string options[] = {
 452                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 453                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 454 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 455                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 456                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 457 #endif
 458 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 459                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 460                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 461 #endif
 462 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 463                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 464                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 465 #endif
 466 #if defined(CONFIG_SYS_FSL_DDR3)
 467                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 468                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 469 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 470                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 471                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 472 #endif
 473 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 474                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 475                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 476 #endif
 477 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 478                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 479                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 480 #endif
 481 #endif
 482                 CTRL_OPTIONS(memctl_interleaving),
 483                 CTRL_OPTIONS(memctl_interleaving_mode),
 484                 CTRL_OPTIONS(ba_intlv_ctl),
 485                 CTRL_OPTIONS(ecc_mode),
 486                 CTRL_OPTIONS(ecc_init_using_memctl),
 487                 CTRL_OPTIONS(dqs_config),
 488                 CTRL_OPTIONS(self_refresh_in_sleep),
 489                 CTRL_OPTIONS(dynamic_power),
 490                 CTRL_OPTIONS(data_bus_width),
 491                 CTRL_OPTIONS(burst_length),
 492                 CTRL_OPTIONS(cas_latency_override),
 493                 CTRL_OPTIONS(cas_latency_override_value),
 494                 CTRL_OPTIONS(use_derated_caslat),
 495                 CTRL_OPTIONS(additive_latency_override),
 496                 CTRL_OPTIONS(additive_latency_override_value),
 497                 CTRL_OPTIONS(clk_adjust),
 498                 CTRL_OPTIONS(cpo_override),
 499                 CTRL_OPTIONS(write_data_delay),
 500                 CTRL_OPTIONS(half_strength_driver_enable),
 501
 502                 /*
 503                  * These can probably be changed to 2T_EN and 3T_EN
 504                  * (using a leading numerical character) without problem
 505                  */
 506                 CTRL_OPTIONS(twot_en),
 507                 CTRL_OPTIONS(threet_en),
 508                 CTRL_OPTIONS(ap_en),
 509                 CTRL_OPTIONS(x4_en),
 510                 CTRL_OPTIONS(bstopre),
 511                 CTRL_OPTIONS(wrlvl_override),
 512                 CTRL_OPTIONS(wrlvl_sample),
 513                 CTRL_OPTIONS(wrlvl_start),
 514                 CTRL_OPTIONS(cswl_override),
 515                 CTRL_OPTIONS(rcw_override),
 516                 CTRL_OPTIONS(rcw_1),
 517                 CTRL_OPTIONS(rcw_2),
 518                 CTRL_OPTIONS(ddr_cdr1),
 519                 CTRL_OPTIONS(ddr_cdr2),
 520                 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
 521                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 522                 CTRL_OPTIONS(trwt_override),
 523                 CTRL_OPTIONS(trwt),
 524                 CTRL_OPTIONS(rtt_override),
 525                 CTRL_OPTIONS(rtt_override_value),
 526                 CTRL_OPTIONS(rtt_wr_override_value),
 527         };
 528
 529         static const unsigned int n_opts = ARRAY_SIZE(options);
 530
 531         if (handle_option_table(options, n_opts, p,
 532                                         optname_str, value_str))
 533                 return;
 534
 535         printf("couldn't find option string %s\n", optname_str);
 536 }
 537
 538 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
 539         sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
 540 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
 541         offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
 542         sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
 543
 544 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 545 {
 546         unsigned int i;
 547         static const struct options_string options[] = {
 548                 CFG_REGS_CS(0, bnds),
 549                 CFG_REGS_CS(0, config),
 550                 CFG_REGS_CS(0, config_2),
 551 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 552                 CFG_REGS_CS(1, bnds),
 553                 CFG_REGS_CS(1, config),
 554                 CFG_REGS_CS(1, config_2),
 555 #endif
 556 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 557                 CFG_REGS_CS(2, bnds),
 558                 CFG_REGS_CS(2, config),
 559                 CFG_REGS_CS(2, config_2),
 560 #endif
 561 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 562                 CFG_REGS_CS(3, bnds),
 563                 CFG_REGS_CS(3, config),
 564                 CFG_REGS_CS(3, config_2),
 565 #endif
 566                 CFG_REGS(timing_cfg_3),
 567                 CFG_REGS(timing_cfg_0),
 568                 CFG_REGS(timing_cfg_1),
 569                 CFG_REGS(timing_cfg_2),
 570                 CFG_REGS(ddr_sdram_cfg),
 571                 CFG_REGS(ddr_sdram_cfg_2),
 572                 CFG_REGS(ddr_sdram_cfg_3),
 573                 CFG_REGS(ddr_sdram_mode),
 574                 CFG_REGS(ddr_sdram_mode_2),
 575                 CFG_REGS(ddr_sdram_mode_3),
 576                 CFG_REGS(ddr_sdram_mode_4),
 577                 CFG_REGS(ddr_sdram_mode_5),
 578                 CFG_REGS(ddr_sdram_mode_6),
 579                 CFG_REGS(ddr_sdram_mode_7),
 580                 CFG_REGS(ddr_sdram_mode_8),
 581 #ifdef CONFIG_SYS_FSL_DDR4
 582                 CFG_REGS(ddr_sdram_mode_9),
 583                 CFG_REGS(ddr_sdram_mode_10),
 584                 CFG_REGS(ddr_sdram_mode_11),
 585                 CFG_REGS(ddr_sdram_mode_12),
 586                 CFG_REGS(ddr_sdram_mode_13),
 587                 CFG_REGS(ddr_sdram_mode_14),
 588                 CFG_REGS(ddr_sdram_mode_15),
 589                 CFG_REGS(ddr_sdram_mode_16),
 590 #endif
 591                 CFG_REGS(ddr_sdram_interval),
 592                 CFG_REGS(ddr_data_init),
 593                 CFG_REGS(ddr_sdram_clk_cntl),
 594                 CFG_REGS(ddr_init_addr),
 595                 CFG_REGS(ddr_init_ext_addr),
 596                 CFG_REGS(timing_cfg_4),
 597                 CFG_REGS(timing_cfg_5),
 598 #ifdef CONFIG_SYS_FSL_DDR4
 599                 CFG_REGS(timing_cfg_6),
 600                 CFG_REGS(timing_cfg_7),
 601                 CFG_REGS(timing_cfg_8),
 602                 CFG_REGS(timing_cfg_9),
 603 #endif
 604                 CFG_REGS(ddr_zq_cntl),
 605                 CFG_REGS(ddr_wrlvl_cntl),
 606                 CFG_REGS(ddr_wrlvl_cntl_2),
 607                 CFG_REGS(ddr_wrlvl_cntl_3),
 608                 CFG_REGS(ddr_sr_cntr),
 609                 CFG_REGS(ddr_sdram_rcw_1),
 610                 CFG_REGS(ddr_sdram_rcw_2),
 611                 CFG_REGS(ddr_cdr1),
 612                 CFG_REGS(ddr_cdr2),
 613                 CFG_REGS(dq_map_0),
 614                 CFG_REGS(dq_map_1),
 615                 CFG_REGS(dq_map_2),
 616                 CFG_REGS(dq_map_3),
 617                 CFG_REGS(err_disable),
 618                 CFG_REGS(err_int_en),
 619                 CFG_REGS(ddr_eor),
 620         };
 621         static const unsigned int n_opts = ARRAY_SIZE(options);
 622
 623         print_option_table(options, n_opts, ddr);
 624
 625         for (i = 0; i < 32; i++)
 626                 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 627 }
 628
 629 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 630                         unsigned int ctrl_num,
 631                         const char *regname,
 632                         const char *value_str)
 633 {
 634         unsigned int i;
 635         fsl_ddr_cfg_regs_t *ddr;
 636         char buf[20];
 637         static const struct options_string options[] = {
 638                 CFG_REGS_CS(0, bnds),
 639                 CFG_REGS_CS(0, config),
 640                 CFG_REGS_CS(0, config_2),
 641 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 642                 CFG_REGS_CS(1, bnds),
 643                 CFG_REGS_CS(1, config),
 644                 CFG_REGS_CS(1, config_2),
 645 #endif
 646 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 647                 CFG_REGS_CS(2, bnds),
 648                 CFG_REGS_CS(2, config),
 649                 CFG_REGS_CS(2, config_2),
 650 #endif
 651 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 652                 CFG_REGS_CS(3, bnds),
 653                 CFG_REGS_CS(3, config),
 654                 CFG_REGS_CS(3, config_2),
 655 #endif
 656                 CFG_REGS(timing_cfg_3),
 657                 CFG_REGS(timing_cfg_0),
 658                 CFG_REGS(timing_cfg_1),
 659                 CFG_REGS(timing_cfg_2),
 660                 CFG_REGS(ddr_sdram_cfg),
 661                 CFG_REGS(ddr_sdram_cfg_2),
 662                 CFG_REGS(ddr_sdram_cfg_3),
 663                 CFG_REGS(ddr_sdram_mode),
 664                 CFG_REGS(ddr_sdram_mode_2),
 665                 CFG_REGS(ddr_sdram_mode_3),
 666                 CFG_REGS(ddr_sdram_mode_4),
 667                 CFG_REGS(ddr_sdram_mode_5),
 668                 CFG_REGS(ddr_sdram_mode_6),
 669                 CFG_REGS(ddr_sdram_mode_7),
 670                 CFG_REGS(ddr_sdram_mode_8),
 671 #ifdef CONFIG_SYS_FSL_DDR4
 672                 CFG_REGS(ddr_sdram_mode_9),
 673                 CFG_REGS(ddr_sdram_mode_10),
 674                 CFG_REGS(ddr_sdram_mode_11),
 675                 CFG_REGS(ddr_sdram_mode_12),
 676                 CFG_REGS(ddr_sdram_mode_13),
 677                 CFG_REGS(ddr_sdram_mode_14),
 678                 CFG_REGS(ddr_sdram_mode_15),
 679                 CFG_REGS(ddr_sdram_mode_16),
 680 #endif
 681                 CFG_REGS(ddr_sdram_interval),
 682                 CFG_REGS(ddr_data_init),
 683                 CFG_REGS(ddr_sdram_clk_cntl),
 684                 CFG_REGS(ddr_init_addr),
 685                 CFG_REGS(ddr_init_ext_addr),
 686                 CFG_REGS(timing_cfg_4),
 687                 CFG_REGS(timing_cfg_5),
 688 #ifdef CONFIG_SYS_FSL_DDR4
 689                 CFG_REGS(timing_cfg_6),
 690                 CFG_REGS(timing_cfg_7),
 691                 CFG_REGS(timing_cfg_8),
 692                 CFG_REGS(timing_cfg_9),
 693 #endif
 694                 CFG_REGS(ddr_zq_cntl),
 695                 CFG_REGS(ddr_wrlvl_cntl),
 696                 CFG_REGS(ddr_wrlvl_cntl_2),
 697                 CFG_REGS(ddr_wrlvl_cntl_3),
 698                 CFG_REGS(ddr_sr_cntr),
 699                 CFG_REGS(ddr_sdram_rcw_1),
 700                 CFG_REGS(ddr_sdram_rcw_2),
 701                 CFG_REGS(ddr_cdr1),
 702                 CFG_REGS(ddr_cdr2),
 703                 CFG_REGS(dq_map_0),
 704                 CFG_REGS(dq_map_1),
 705                 CFG_REGS(dq_map_2),
 706                 CFG_REGS(dq_map_3),
 707                 CFG_REGS(err_disable),
 708                 CFG_REGS(err_int_en),
 709                 CFG_REGS(ddr_sdram_rcw_2),
 710                 CFG_REGS(ddr_sdram_rcw_2),
 711                 CFG_REGS(ddr_eor),
 712         };
 713         static const unsigned int n_opts = ARRAY_SIZE(options);
 714
 715         debug("fsl_ddr_regs_edit: ctrl_num = %u, "
 716                 "regname = %s, value = %s\n",
 717                 ctrl_num, regname, value_str);
 718         if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
 719                 return;
 720
 721         ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
 722
 723         if (handle_option_table(options, n_opts, ddr, regname, value_str))
 724                 return;
 725
 726         for (i = 0; i < 32; i++) {
 727                 unsigned int value = simple_strtoul(value_str, NULL, 0);
 728                 sprintf(buf, "debug_%u", i + 1);
 729                 if (strcmp(buf, regname) == 0) {
 730                         ddr->debug[i] = value;
 731                         return;
 732                 }
 733         }
 734         printf("Error: couldn't find register string %s\n", regname);
 735 }
 736
 737 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
 738         sizeof((memctl_options_t *)0)->x, 1}
 739
 740 static void print_memctl_options(const memctl_options_t *popts)
 741 {
 742         static const struct options_string options[] = {
 743                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 744                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 745 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 746                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 747                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 748 #endif
 749 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 750                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 751                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 752 #endif
 753 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 754                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 755                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 756 #endif
 757 #if defined(CONFIG_SYS_FSL_DDR3)
 758                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 759                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 760 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 761                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 762                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 763 #endif
 764 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 765                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 766                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 767 #endif
 768 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 769                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 770                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 771 #endif
 772 #endif
 773                 CTRL_OPTIONS(memctl_interleaving),
 774                 CTRL_OPTIONS(memctl_interleaving_mode),
 775                 CTRL_OPTIONS_HEX(ba_intlv_ctl),
 776                 CTRL_OPTIONS(ecc_mode),
 777                 CTRL_OPTIONS(ecc_init_using_memctl),
 778                 CTRL_OPTIONS(dqs_config),
 779                 CTRL_OPTIONS(self_refresh_in_sleep),
 780                 CTRL_OPTIONS(dynamic_power),
 781                 CTRL_OPTIONS(data_bus_width),
 782                 CTRL_OPTIONS(burst_length),
 783                 CTRL_OPTIONS(cas_latency_override),
 784                 CTRL_OPTIONS(cas_latency_override_value),
 785                 CTRL_OPTIONS(use_derated_caslat),
 786                 CTRL_OPTIONS(additive_latency_override),
 787                 CTRL_OPTIONS(additive_latency_override_value),
 788                 CTRL_OPTIONS(clk_adjust),
 789                 CTRL_OPTIONS(cpo_override),
 790                 CTRL_OPTIONS(write_data_delay),
 791                 CTRL_OPTIONS(half_strength_driver_enable),
 792                 /*
 793                  * These can probably be changed to 2T_EN and 3T_EN
 794                  * (using a leading numerical character) without problem
 795                  */
 796                 CTRL_OPTIONS(twot_en),
 797                 CTRL_OPTIONS(threet_en),
 798                 CTRL_OPTIONS(registered_dimm_en),
 799                 CTRL_OPTIONS(ap_en),
 800                 CTRL_OPTIONS(x4_en),
 801                 CTRL_OPTIONS(bstopre),
 802                 CTRL_OPTIONS(wrlvl_override),
 803                 CTRL_OPTIONS(wrlvl_sample),
 804                 CTRL_OPTIONS(wrlvl_start),
 805                 CTRL_OPTIONS_HEX(cswl_override),
 806                 CTRL_OPTIONS(rcw_override),
 807                 CTRL_OPTIONS(rcw_1),
 808                 CTRL_OPTIONS(rcw_2),
 809                 CTRL_OPTIONS_HEX(ddr_cdr1),
 810                 CTRL_OPTIONS_HEX(ddr_cdr2),
 811                 CTRL_OPTIONS(tcke_clock_pulse_width_ps),
 812                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 813                 CTRL_OPTIONS(trwt_override),
 814                 CTRL_OPTIONS(trwt),
 815                 CTRL_OPTIONS(rtt_override),
 816                 CTRL_OPTIONS(rtt_override_value),
 817                 CTRL_OPTIONS(rtt_wr_override_value),
 818         };
 819         static const unsigned int n_opts = ARRAY_SIZE(options);
 820
 821         print_option_table(options, n_opts, popts);
 822 }
 823
 824 #ifdef CONFIG_SYS_FSL_DDR1
 825 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
 826 {
 827         unsigned int i;
 828
 829         printf("%-3d    : %02x %s\n", 0, spd->info_size,
 830                " spd->info_size,   *  0 # bytes written into serial memory *");
 831         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
 832                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
 833         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
 834                " spd->mem_type,    *  2 Fundamental memory type *");
 835         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
 836                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
 837         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
 838                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
 839         printf("%-3d    : %02x %s\n", 5, spd->nrows,
 840                " spd->nrows        *  5 # of DIMM Banks *");
 841         printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
 842                " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
 843         printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
 844                " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
 845         printf("%-3d    : %02x %s\n", 8, spd->voltage,
 846                " spd->voltage,     *  8 Voltage intf std of this assembly *");
 847         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
 848                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
 849         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
 850                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
 851         printf("%-3d    : %02x %s\n", 11, spd->config,
 852                " spd->config,      * 11 DIMM Configuration type *");
 853         printf("%-3d    : %02x %s\n", 12, spd->refresh,
 854                " spd->refresh,     * 12 Refresh Rate/Type *");
 855         printf("%-3d    : %02x %s\n", 13, spd->primw,
 856                " spd->primw,       * 13 Primary SDRAM Width *");
 857         printf("%-3d    : %02x %s\n", 14, spd->ecw,
 858                " spd->ecw,         * 14 Error Checking SDRAM width *");
 859         printf("%-3d    : %02x %s\n", 15, spd->min_delay,
 860                " spd->min_delay,   * 15 Back to Back Random Access *");
 861         printf("%-3d    : %02x %s\n", 16, spd->burstl,
 862                " spd->burstl,      * 16 Burst Lengths Supported *");
 863         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
 864                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
 865         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
 866                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
 867         printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
 868                " spd->cs_lat,      * 19 Chip Select Latency *");
 869         printf("%-3d    : %02x %s\n", 20, spd->write_lat,
 870                " spd->write_lat,   * 20 Write Latency/Recovery *");
 871         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
 872                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
 873         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
 874                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
 875         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
 876                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
 877         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
 878                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
 879         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
 880                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
 881         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
 882                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
 883         printf("%-3d    : %02x %s\n", 27, spd->trp,
 884                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
 885         printf("%-3d    : %02x %s\n", 28, spd->trrd,
 886                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
 887         printf("%-3d    : %02x %s\n", 29, spd->trcd,
 888                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
 889         printf("%-3d    : %02x %s\n", 30, spd->tras,
 890                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
 891         printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
 892                " spd->bank_dens,   * 31 Density of each bank on module *");
 893         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
 894                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
 895         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
 896                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
 897         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
 898                " spd->data_setup,  * 34 Data signal input setup time *");
 899         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
 900                " spd->data_hold,   * 35 Data signal input hold time *");
 901         printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
 902                " spd->res_36_40[0], * 36 Reserved / tWR *");
 903         printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
 904                " spd->res_36_40[1], * 37 Reserved / tWTR *");
 905         printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
 906                " spd->res_36_40[2], * 38 Reserved / tRTP *");
 907         printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
 908                " spd->res_36_40[3], * 39 Reserved / mem_probe *");
 909         printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
 910                " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
 911         printf("%-3d    : %02x %s\n", 41, spd->trc,
 912                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
 913         printf("%-3d    : %02x %s\n", 42, spd->trfc,
 914                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
 915         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
 916                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
 917         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
 918                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
 919         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
 920                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
 921         printf("%-3d    : %02x %s\n", 46, spd->res_46,
 922                " spd->res_46,  * 46 Reserved/ PLL Relock time *");
 923         printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
 924                " spd->dimm_height  * 47 SDRAM DIMM Height *");
 925
 926         printf("%-3d-%3d: ",  48, 61);
 927
 928         for (i = 0; i < 14; i++)
 929                 printf("%02x", spd->res_48_61[i]);
 930
 931         printf(" * 48-61 IDD in SPD and Reserved space *\n");
 932
 933         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
 934                " spd->spd_rev,     * 62 SPD Data Revision Code *");
 935         printf("%-3d    : %02x %s\n", 63, spd->cksum,
 936                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
 937         printf("%-3d-%3d: ",  64, 71);
 938
 939         for (i = 0; i < 8; i++)
 940                 printf("%02x", spd->mid[i]);
 941
 942         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
 943         printf("%-3d    : %02x %s\n", 72, spd->mloc,
 944                " spd->mloc,        * 72 Manufacturing Location *");
 945
 946         printf("%-3d-%3d: >>",  73, 90);
 947
 948         for (i = 0; i < 18; i++)
 949                 printf("%c", spd->mpart[i]);
 950
 951         printf("<<* 73 Manufacturer's Part Number *\n");
 952
 953         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
 954                "* 91 Revision Code *");
 955         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
 956                "* 93 Manufacturing Date *");
 957         printf("%-3d-%3d: ", 95, 98);
 958
 959         for (i = 0; i < 4; i++)
 960                 printf("%02x", spd->sernum[i]);
 961
 962         printf("* 95 Assembly Serial Number *\n");
 963
 964         printf("%-3d-%3d: ", 99, 127);
 965
 966         for (i = 0; i < 27; i++)
 967                 printf("%02x", spd->mspec[i]);
 968
 969         printf("* 99 Manufacturer Specific Data *\n");
 970 }
 971 #endif
 972
 973 #ifdef CONFIG_SYS_FSL_DDR2
 974 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
 975 {
 976         unsigned int i;
 977
 978         printf("%-3d    : %02x %s\n", 0, spd->info_size,
 979                " spd->info_size,   *  0 # bytes written into serial memory *");
 980         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
 981                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
 982         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
 983                " spd->mem_type,    *  2 Fundamental memory type *");
 984         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
 985                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
 986         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
 987                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
 988         printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
 989                " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
 990         printf("%-3d    : %02x %s\n", 6, spd->dataw,
 991                " spd->dataw,       *  6 Data Width of this assembly *");
 992         printf("%-3d    : %02x %s\n", 7, spd->res_7,
 993                " spd->res_7,       *  7 Reserved *");
 994         printf("%-3d    : %02x %s\n", 8, spd->voltage,
 995                " spd->voltage,     *  8 Voltage intf std of this assembly *");
 996         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
 997                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
 998         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
 999                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
1000         printf("%-3d    : %02x %s\n", 11, spd->config,
1001                " spd->config,      * 11 DIMM Configuration type *");
1002         printf("%-3d    : %02x %s\n", 12, spd->refresh,
1003                " spd->refresh,     * 12 Refresh Rate/Type *");
1004         printf("%-3d    : %02x %s\n", 13, spd->primw,
1005                " spd->primw,       * 13 Primary SDRAM Width *");
1006         printf("%-3d    : %02x %s\n", 14, spd->ecw,
1007                " spd->ecw,         * 14 Error Checking SDRAM width *");
1008         printf("%-3d    : %02x %s\n", 15, spd->res_15,
1009                " spd->res_15,      * 15 Reserved *");
1010         printf("%-3d    : %02x %s\n", 16, spd->burstl,
1011                " spd->burstl,      * 16 Burst Lengths Supported *");
1012         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
1013                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
1014         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
1015                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
1016         printf("%-3d    : %02x %s\n", 19, spd->mech_char,
1017                " spd->mech_char,   * 19 Mechanical Characteristics *");
1018         printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
1019                " spd->dimm_type,   * 20 DIMM type *");
1020         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
1021                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
1022         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
1023                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
1024         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
1025                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
1026         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
1027                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1028         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
1029                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
1030         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
1031                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1032         printf("%-3d    : %02x %s\n", 27, spd->trp,
1033                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
1034         printf("%-3d    : %02x %s\n", 28, spd->trrd,
1035                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
1036         printf("%-3d    : %02x %s\n", 29, spd->trcd,
1037                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
1038         printf("%-3d    : %02x %s\n", 30, spd->tras,
1039                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
1040         printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
1041                " spd->rank_dens,   * 31 Density of each rank on module *");
1042         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
1043                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
1044         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
1045                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
1046         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
1047                " spd->data_setup,  * 34 Data signal input setup time *");
1048         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
1049                " spd->data_hold,   * 35 Data signal input hold time *");
1050         printf("%-3d    : %02x %s\n", 36, spd->twr,
1051                " spd->twr,         * 36 Write Recovery time tWR *");
1052         printf("%-3d    : %02x %s\n", 37, spd->twtr,
1053                " spd->twtr,        * 37 Int write to read delay tWTR *");
1054         printf("%-3d    : %02x %s\n", 38, spd->trtp,
1055                " spd->trtp,        * 38 Int read to precharge delay tRTP *");
1056         printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
1057                " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
1058         printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
1059                " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1060         printf("%-3d    : %02x %s\n", 41, spd->trc,
1061                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
1062         printf("%-3d    : %02x %s\n", 42, spd->trfc,
1063                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
1064         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
1065                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
1066         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
1067                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
1068         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
1069                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
1070         printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
1071                " spd->pll_relock,  * 46 PLL Relock time *");
1072         printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
1073                " spd->t_casemax,    * 47 t_casemax *");
1074         printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
1075                " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
1076                "from Top (Case) to Ambient (Psi T-A DRAM) *");
1077         printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
1078                " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
1079                "Ambient due to Activate-Precharge/Mode Bits "
1080                "(DT0/Mode Bits) *)");
1081         printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
1082                " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
1083                "Ambient due to Precharge/Quiet Standby "
1084                "(DT2N/DT2Q) *");
1085         printf("%-3d    : %02x %s\n", 51, spd->dt2p,
1086                " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
1087                "Ambient due to Precharge Power-Down (DT2P) *");
1088         printf("%-3d    : %02x %s\n", 52, spd->dt3n,
1089                " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
1090                "Ambient due to Active Standby (DT3N) *");
1091         printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
1092                " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
1093                "Ambient due to Active Power-Down with Fast PDN Exit "
1094                "(DT3Pfast) *");
1095         printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
1096                " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
1097                "Ambient due to Active Power-Down with Slow PDN Exit "
1098                "(DT3Pslow) *");
1099         printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
1100                " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1101                "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1102                "(DT4R/DT4R4W Mode Bit) *");
1103         printf("%-3d    : %02x %s\n", 56, spd->dt5b,
1104                " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
1105                "Ambient due to Burst Refresh (DT5B) *");
1106         printf("%-3d    : %02x %s\n", 57, spd->dt7,
1107                " spd->dt7,         * 57 DRAM Case Temperature Rise from "
1108                "Ambient due to Bank Interleave Reads with "
1109                "Auto-Precharge (DT7) *");
1110         printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
1111                " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
1112                " Top (Case) to Ambient (Psi T-A PLL) *");
1113         printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
1114                " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
1115                " from Top (Case) to Ambient (Psi T-A Register) *");
1116         printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
1117                " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1118                "Ambient due to PLL Active (DT PLL Active) *");
1119         printf("%-3d    : %02x %s\n", 61, spd->dtregact,
1120                " spd->dtregact,    "
1121                "* 61 Register Case Temperature Rise from Ambient due to "
1122                "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1123         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1124                " spd->spd_rev,     * 62 SPD Data Revision Code *");
1125         printf("%-3d    : %02x %s\n", 63, spd->cksum,
1126                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1127
1128         printf("%-3d-%3d: ",  64, 71);
1129
1130         for (i = 0; i < 8; i++)
1131                 printf("%02x", spd->mid[i]);
1132
1133         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1134
1135         printf("%-3d    : %02x %s\n", 72, spd->mloc,
1136                " spd->mloc,        * 72 Manufacturing Location *");
1137
1138         printf("%-3d-%3d: >>",  73, 90);
1139         for (i = 0; i < 18; i++)
1140                 printf("%c", spd->mpart[i]);
1141
1142
1143         printf("<<* 73 Manufacturer's Part Number *\n");
1144
1145         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1146                "* 91 Revision Code *");
1147         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1148                "* 93 Manufacturing Date *");
1149         printf("%-3d-%3d: ", 95, 98);
1150
1151         for (i = 0; i < 4; i++)
1152                 printf("%02x", spd->sernum[i]);
1153
1154         printf("* 95 Assembly Serial Number *\n");
1155
1156         printf("%-3d-%3d: ", 99, 127);
1157         for (i = 0; i < 27; i++)
1158                 printf("%02x", spd->mspec[i]);
1159
1160
1161         printf("* 99 Manufacturer Specific Data *\n");
1162 }
1163 #endif
1164
1165 #ifdef CONFIG_SYS_FSL_DDR3
1166 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1167 {
1168         unsigned int i;
1169
1170         /* General Section: Bytes 0-59 */
1171
1172 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1173 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1174         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1175
1176         PRINT_NXS(0, spd->info_size_crc,
1177                 "info_size_crc  bytes written into serial memory, "
1178                 "CRC coverage");
1179         PRINT_NXS(1, spd->spd_rev,
1180                 "spd_rev        SPD Revision");
1181         PRINT_NXS(2, spd->mem_type,
1182                 "mem_type       Key Byte / DRAM Device Type");
1183         PRINT_NXS(3, spd->module_type,
1184                 "module_type    Key Byte / Module Type");
1185         PRINT_NXS(4, spd->density_banks,
1186                 "density_banks  SDRAM Density and Banks");
1187         PRINT_NXS(5, spd->addressing,
1188                 "addressing     SDRAM Addressing");
1189         PRINT_NXS(6, spd->module_vdd,
1190                 "module_vdd     Module Nominal Voltage, VDD");
1191         PRINT_NXS(7, spd->organization,
1192                 "organization   Module Organization");
1193         PRINT_NXS(8, spd->bus_width,
1194                 "bus_width      Module Memory Bus Width");
1195         PRINT_NXS(9, spd->ftb_div,
1196                 "ftb_div        Fine Timebase (FTB) Dividend / Divisor");
1197         PRINT_NXS(10, spd->mtb_dividend,
1198                 "mtb_dividend   Medium Timebase (MTB) Dividend");
1199         PRINT_NXS(11, spd->mtb_divisor,
1200                 "mtb_divisor    Medium Timebase (MTB) Divisor");
1201         PRINT_NXS(12, spd->tck_min,
1202                   "tck_min        SDRAM Minimum Cycle Time");
1203         PRINT_NXS(13, spd->res_13,
1204                 "res_13         Reserved");
1205         PRINT_NXS(14, spd->caslat_lsb,
1206                 "caslat_lsb     CAS Latencies Supported, LSB");
1207         PRINT_NXS(15, spd->caslat_msb,
1208                 "caslat_msb     CAS Latencies Supported, MSB");
1209         PRINT_NXS(16, spd->taa_min,
1210                   "taa_min        Min CAS Latency Time");
1211         PRINT_NXS(17, spd->twr_min,
1212                   "twr_min        Min Write REcovery Time");
1213         PRINT_NXS(18, spd->trcd_min,
1214                   "trcd_min       Min RAS# to CAS# Delay Time");
1215         PRINT_NXS(19, spd->trrd_min,
1216                   "trrd_min       Min Row Active to Row Active Delay Time");
1217         PRINT_NXS(20, spd->trp_min,
1218                   "trp_min        Min Row Precharge Delay Time");
1219         PRINT_NXS(21, spd->tras_trc_ext,
1220                   "tras_trc_ext   Upper Nibbles for tRAS and tRC");
1221         PRINT_NXS(22, spd->tras_min_lsb,
1222                   "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
1223         PRINT_NXS(23, spd->trc_min_lsb,
1224                   "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1225         PRINT_NXS(24, spd->trfc_min_lsb,
1226                   "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
1227         PRINT_NXS(25, spd->trfc_min_msb,
1228                   "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
1229         PRINT_NXS(26, spd->twtr_min,
1230                   "twtr_min Min Internal Write to Read Command Delay Time");
1231         PRINT_NXS(27, spd->trtp_min,
1232                   "trtp_min "
1233                   "Min Internal Read to Precharge Command Delay Time");
1234         PRINT_NXS(28, spd->tfaw_msb,
1235                   "tfaw_msb       Upper Nibble for tFAW");
1236         PRINT_NXS(29, spd->tfaw_min,
1237                   "tfaw_min       Min Four Activate Window Delay Time");
1238         PRINT_NXS(30, spd->opt_features,
1239                 "opt_features   SDRAM Optional Features");
1240         PRINT_NXS(31, spd->therm_ref_opt,
1241                 "therm_ref_opt  SDRAM Thermal and Refresh Opts");
1242         PRINT_NXS(32, spd->therm_sensor,
1243                 "therm_sensor  SDRAM Thermal Sensor");
1244         PRINT_NXS(33, spd->device_type,
1245                 "device_type  SDRAM Device Type");
1246         PRINT_NXS(34, spd->fine_tck_min,
1247                   "fine_tck_min  Fine offset for tCKmin");
1248         PRINT_NXS(35, spd->fine_taa_min,
1249                   "fine_taa_min  Fine offset for tAAmin");
1250         PRINT_NXS(36, spd->fine_trcd_min,
1251                   "fine_trcd_min Fine offset for tRCDmin");
1252         PRINT_NXS(37, spd->fine_trp_min,
1253                   "fine_trp_min  Fine offset for tRPmin");
1254         PRINT_NXS(38, spd->fine_trc_min,
1255                   "fine_trc_min  Fine offset for tRCmin");
1256
1257         printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
1258
1259         for (i = 39; i <= 59; i++)
1260                 printf("%02x ", spd->res_39_59[i - 39]);
1261
1262         puts("\n");
1263
1264         switch (spd->module_type) {
1265         case 0x02:  /* UDIMM */
1266         case 0x03:  /* SO-DIMM */
1267         case 0x04:  /* Micro-DIMM */
1268         case 0x06:  /* Mini-UDIMM */
1269                 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1270                         "mod_height    (Unbuffered) Module Nominal Height");
1271                 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1272                         "mod_thickness (Unbuffered) Module Maximum Thickness");
1273                 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1274                         "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1275                 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1276                         "addr_mapping  (Unbuffered) Address mapping from "
1277                         "Edge Connector to DRAM");
1278                 break;
1279         case 0x01:  /* RDIMM */
1280         case 0x05:  /* Mini-RDIMM */
1281                 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1282                         "mod_height    (Registered) Module Nominal Height");
1283                 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1284                         "mod_thickness (Registered) Module Maximum Thickness");
1285                 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1286                         "ref_raw_card  (Registered) Reference Raw Card Used");
1287                 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1288                         "modu_attr     (Registered) DIMM Module Attributes");
1289                 PRINT_NXS(64, spd->mod_section.registered.thermal,
1290                         "thermal       (Registered) Thermal Heat "
1291                         "Spreader Solution");
1292                 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1293                         "reg_id_lo     (Registered) Register Manufacturer ID "
1294                         "Code, LSB");
1295                 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1296                         "reg_id_hi     (Registered) Register Manufacturer ID "
1297                         "Code, MSB");
1298                 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1299                         "reg_rev       (Registered) Register "
1300                         "Revision Number");
1301                 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1302                         "reg_type      (Registered) Register Type");
1303                 for (i = 69; i <= 76; i++) {
1304                         printf("%-3d    : %02x rcw[%d]\n", i,
1305                                 spd->mod_section.registered.rcw[i-69], i-69);
1306                 }
1307                 break;
1308         default:
1309                 /* Module-specific Section, Unsupported Module Type */
1310                 printf("%-3d-%3d: ", 60, 116);
1311
1312                 for (i = 60; i <= 116; i++)
1313                         printf("%02x", spd->mod_section.uc[i - 60]);
1314
1315                 break;
1316         }
1317
1318         /* Unique Module ID: Bytes 117-125 */
1319         PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1320         PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1321         PRINT_NXS(119, spd->mloc,     "Mfg Location");
1322         PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1323
1324         printf("%-3d-%3d: ", 122, 125);
1325
1326         for (i = 122; i <= 125; i++)
1327                 printf("%02x ", spd->sernum[i - 122]);
1328         printf("   Module Serial Number\n");
1329
1330         /* CRC: Bytes 126-127 */
1331         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1332
1333         /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1334         printf("%-3d-%3d: ", 128, 145);
1335         for (i = 128; i <= 145; i++)
1336                 printf("%02x ", spd->mpart[i - 128]);
1337         printf("   Mfg's Module Part Number\n");
1338
1339         PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1340                 "Module Revision code");
1341
1342         PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1343         PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1344
1345         printf("%-3d-%3d: ", 150, 175);
1346         for (i = 150; i <= 175; i++)
1347                 printf("%02x ", spd->msd[i - 150]);
1348         printf("   Mfg's Specific Data\n");
1349
1350         printf("%-3d-%3d: ", 176, 255);
1351         for (i = 176; i <= 255; i++)
1352                 printf("%02x", spd->cust[i - 176]);
1353         printf("   Mfg's Specific Data\n");
1354
1355 }
1356 #endif
1357
1358 #ifdef CONFIG_SYS_FSL_DDR4
1359 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1360 {
1361         unsigned int i;
1362
1363         /* General Section: Bytes 0-127 */
1364
1365 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1366 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1367         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1368
1369         PRINT_NXS(0, spd->info_size_crc,
1370                   "info_size_crc  bytes written into serial memory, CRC coverage");
1371         PRINT_NXS(1, spd->spd_rev,
1372                   "spd_rev        SPD Revision");
1373         PRINT_NXS(2, spd->mem_type,
1374                   "mem_type       Key Byte / DRAM Device Type");
1375         PRINT_NXS(3, spd->module_type,
1376                   "module_type    Key Byte / Module Type");
1377         PRINT_NXS(4, spd->density_banks,
1378                   "density_banks  SDRAM Density and Banks");
1379         PRINT_NXS(5, spd->addressing,
1380                   "addressing     SDRAM Addressing");
1381         PRINT_NXS(6, spd->package_type,
1382                   "package_type   Package type");
1383         PRINT_NXS(7, spd->opt_feature,
1384                   "opt_feature    Optional features");
1385         PRINT_NXS(8, spd->thermal_ref,
1386                   "thermal_ref    Thermal and Refresh options");
1387         PRINT_NXS(9, spd->oth_opt_features,
1388                   "oth_opt_features Other SDRAM optional features");
1389         PRINT_NXS(10, spd->res_10,
1390                   "res_10         Reserved");
1391         PRINT_NXS(11, spd->module_vdd,
1392                   "module_vdd     Module Nominal Voltage, VDD");
1393         PRINT_NXS(12, spd->organization,
1394                   "organization Module Organization");
1395         PRINT_NXS(13, spd->bus_width,
1396                   "bus_width      Module Memory Bus Width");
1397         PRINT_NXS(14, spd->therm_sensor,
1398                   "therm_sensor   Module Thermal Sensor");
1399         PRINT_NXS(15, spd->ext_type,
1400                   "ext_type       Extended module type");
1401         PRINT_NXS(16, spd->res_16,
1402                   "res_16       Reserved");
1403         PRINT_NXS(17, spd->timebases,
1404                   "timebases    MTb and FTB");
1405         PRINT_NXS(18, spd->tck_min,
1406                   "tck_min      tCKAVGmin");
1407         PRINT_NXS(19, spd->tck_max,
1408                   "tck_max      TCKAVGmax");
1409         PRINT_NXS(20, spd->caslat_b1,
1410                   "caslat_b1    CAS latencies, 1st byte");
1411         PRINT_NXS(21, spd->caslat_b2,
1412                   "caslat_b2    CAS latencies, 2nd byte");
1413         PRINT_NXS(22, spd->caslat_b3,
1414                   "caslat_b3    CAS latencies, 3rd byte ");
1415         PRINT_NXS(23, spd->caslat_b4,
1416                   "caslat_b4    CAS latencies, 4th byte");
1417         PRINT_NXS(24, spd->taa_min,
1418                   "taa_min      Min CAS Latency Time");
1419         PRINT_NXS(25, spd->trcd_min,
1420                   "trcd_min     Min RAS# to CAS# Delay Time");
1421         PRINT_NXS(26, spd->trp_min,
1422                   "trp_min      Min Row Precharge Delay Time");
1423         PRINT_NXS(27, spd->tras_trc_ext,
1424                   "tras_trc_ext Upper Nibbles for tRAS and tRC");
1425         PRINT_NXS(28, spd->tras_min_lsb,
1426                   "tras_min_lsb tRASmin, lsb");
1427         PRINT_NXS(29, spd->trc_min_lsb,
1428                   "trc_min_lsb  tRCmin, lsb");
1429         PRINT_NXS(30, spd->trfc1_min_lsb,
1430                   "trfc1_min_lsb  Min Refresh Recovery Delay Time, LSB");
1431         PRINT_NXS(31, spd->trfc1_min_msb,
1432                   "trfc1_min_msb  Min Refresh Recovery Delay Time, MSB ");
1433         PRINT_NXS(32, spd->trfc2_min_lsb,
1434                   "trfc2_min_lsb  Min Refresh Recovery Delay Time, LSB");
1435         PRINT_NXS(33, spd->trfc2_min_msb,
1436                   "trfc2_min_msb  Min Refresh Recovery Delay Time, MSB");
1437         PRINT_NXS(34, spd->trfc4_min_lsb,
1438                   "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1439         PRINT_NXS(35, spd->trfc4_min_msb,
1440                   "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1441         PRINT_NXS(36, spd->tfaw_msb,
1442                   "tfaw_msb      Upper Nibble for tFAW");
1443         PRINT_NXS(37, spd->tfaw_min,
1444                   "tfaw_min      tFAW, lsb");
1445         PRINT_NXS(38, spd->trrds_min,
1446                   "trrds_min     tRRD_Smin, MTB");
1447         PRINT_NXS(39, spd->trrdl_min,
1448                   "trrdl_min     tRRD_Lmin, MTB");
1449         PRINT_NXS(40, spd->tccdl_min,
1450                   "tccdl_min     tCCS_Lmin, MTB");
1451
1452         printf("%-3d-%3d: ", 41, 59);  /* Reserved, General Section */
1453         for (i = 41; i <= 59; i++)
1454                 printf("%02x ", spd->res_41[i - 41]);
1455
1456         puts("\n");
1457         printf("%-3d-%3d: ", 60, 77);
1458         for (i = 60; i <= 77; i++)
1459                 printf("%02x ", spd->mapping[i - 60]);
1460         puts("   mapping[] Connector to SDRAM bit map\n");
1461
1462         PRINT_NXS(117, spd->fine_tccdl_min,
1463                   "fine_tccdl_min Fine offset for tCCD_Lmin");
1464         PRINT_NXS(118, spd->fine_trrdl_min,
1465                   "fine_trrdl_min Fine offset for tRRD_Lmin");
1466         PRINT_NXS(119, spd->fine_trrds_min,
1467                   "fine_trrds_min Fine offset for tRRD_Smin");
1468         PRINT_NXS(120, spd->fine_trc_min,
1469                   "fine_trc_min   Fine offset for tRCmin");
1470         PRINT_NXS(121, spd->fine_trp_min,
1471                   "fine_trp_min   Fine offset for tRPmin");
1472         PRINT_NXS(122, spd->fine_trcd_min,
1473                   "fine_trcd_min  Fine offset for tRCDmin");
1474         PRINT_NXS(123, spd->fine_taa_min,
1475                   "fine_taa_min   Fine offset for tAAmin");
1476         PRINT_NXS(124, spd->fine_tck_max,
1477                   "fine_tck_max   Fine offset for tCKAVGmax");
1478         PRINT_NXS(125, spd->fine_tck_min,
1479                   "fine_tck_min   Fine offset for tCKAVGmin");
1480
1481         /* CRC: Bytes 126-127 */
1482         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1483
1484         switch (spd->module_type) {
1485         case 0x02:  /* UDIMM */
1486         case 0x03:  /* SO-DIMM */
1487                 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1488                           "mod_height    (Unbuffered) Module Nominal Height");
1489                 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1490                           "mod_thickness (Unbuffered) Module Maximum Thickness");
1491                 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1492                           "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1493                 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1494                           "addr_mapping  (Unbuffered) Address mapping from Edge Connector to DRAM");
1495                 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1496                             spd->mod_section.unbuffered.crc[1], "  Module CRC");
1497                 break;
1498         case 0x01:  /* RDIMM */
1499                 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1500                           "mod_height    (Registered) Module Nominal Height");
1501                 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1502                           "mod_thickness (Registered) Module Maximum Thickness");
1503                 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1504                           "ref_raw_card  (Registered) Reference Raw Card Used");
1505                 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1506                           "modu_attr     (Registered) DIMM Module Attributes");
1507                 PRINT_NXS(132, spd->mod_section.registered.thermal,
1508                           "thermal       (Registered) Thermal Heat Spreader Solution");
1509                 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1510                           "reg_id_lo     (Registered) Register Manufacturer ID Code, LSB");
1511                 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1512                           "reg_id_hi     (Registered) Register Manufacturer ID Code, MSB");
1513                 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1514                           "reg_rev       (Registered) Register Revision Number");
1515                 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1516                           "reg_map       (Registered) Address mapping");
1517                 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1518                             spd->mod_section.registered.crc[1], "  Module CRC");
1519                 break;
1520         case 0x04:  /* LRDIMM */
1521                 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1522                           "mod_height    (Loadreduced) Module Nominal Height");
1523                 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1524                           "mod_thickness (Loadreduced) Module Maximum Thickness");
1525                 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1526                           "ref_raw_card  (Loadreduced) Reference Raw Card Used");
1527                 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1528                           "modu_attr     (Loadreduced) DIMM Module Attributes");
1529                 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1530                           "thermal       (Loadreduced) Thermal Heat Spreader Solution");
1531                 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1532                           "reg_id_lo     (Loadreduced) Register Manufacturer ID Code, LSB");
1533                 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1534                           "reg_id_hi     (Loadreduced) Register Manufacturer ID Code, MSB");
1535                 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1536                           "reg_rev       (Loadreduced) Register Revision Number");
1537                 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1538                           "reg_map       (Loadreduced) Address mapping");
1539                 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1540                           "reg_drv       (Loadreduced) Reg output drive strength");
1541                 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1542                           "reg_drv_ck    (Loadreduced) Reg output drive strength for CK");
1543                 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1544                           "data_buf_rev  (Loadreduced) Data Buffer Revision Numbe");
1545                 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1546                           "vrefqe_r0     (Loadreduced) DRAM VrefDQ for Package Rank 0");
1547                 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1548                           "vrefqe_r1     (Loadreduced) DRAM VrefDQ for Package Rank 1");
1549                 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1550                           "vrefqe_r2     (Loadreduced) DRAM VrefDQ for Package Rank 2");
1551                 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1552                           "vrefqe_r3     (Loadreduced) DRAM VrefDQ for Package Rank 3");
1553                 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1554                           "data_intf     (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1555                 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1556                           "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1557                 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1558                           "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1559                 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1560                           "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1561                 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1562                           "dram_drv      (Loadreduced) DRAM Drive Strength");
1563                 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1564                           "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1565                 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1566                           "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1567                 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1568                           "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1569                 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1570                           "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1571                 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1572                           "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1573                 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1574                           "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1575                 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1576                             spd->mod_section.loadreduced.crc[1],
1577                             "  Module CRC");
1578                 break;
1579         default:
1580                 /* Module-specific Section, Unsupported Module Type */
1581                 printf("%-3d-%3d: ", 128, 255);
1582
1583                 for (i = 128; i <= 255; i++)
1584                         printf("%02x", spd->mod_section.uc[i - 128]);
1585
1586                 break;
1587         }
1588
1589         /* Unique Module ID: Bytes 320-383 */
1590         PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1591         PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1592         PRINT_NXS(322, spd->mloc,     "Mfg Location");
1593         PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1594
1595         printf("%-3d-%3d: ", 325, 328);
1596
1597         for (i = 325; i <= 328; i++)
1598                 printf("%02x ", spd->sernum[i - 325]);
1599         printf("   Module Serial Number\n");
1600
1601         printf("%-3d-%3d: ", 329, 348);
1602         for (i = 329; i <= 348; i++)
1603                 printf("%02x ", spd->mpart[i - 329]);
1604         printf("   Mfg's Module Part Number\n");
1605
1606         PRINT_NXS(349, spd->mrev, "Module Revision code");
1607         PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1608         PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1609         PRINT_NXS(352, spd->stepping, "DRAM stepping");
1610
1611         printf("%-3d-%3d: ", 353, 381);
1612         for (i = 353; i <= 381; i++)
1613                 printf("%02x ", spd->msd[i - 353]);
1614         printf("   Mfg's Specific Data\n");
1615 }
1616 #endif
1617
1618 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1619 {
1620 #if defined(CONFIG_SYS_FSL_DDR1)
1621         ddr1_spd_dump(spd);
1622 #elif defined(CONFIG_SYS_FSL_DDR2)
1623         ddr2_spd_dump(spd);
1624 #elif defined(CONFIG_SYS_FSL_DDR3)
1625         ddr3_spd_dump(spd);
1626 #elif defined(CONFIG_SYS_FSL_DDR4)
1627         ddr4_spd_dump(spd);
1628 #endif
1629 }
1630
1631 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1632                         unsigned int ctrl_mask,
1633                         unsigned int dimm_mask,
1634                         unsigned int do_mask)
1635 {
1636         unsigned int i, j, retval;
1637
1638         /* STEP 1:  DIMM SPD data */
1639         if (do_mask & STEP_GET_SPD) {
1640                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1641                         if (!(ctrl_mask & (1 << i)))
1642                                 continue;
1643
1644                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1645                                 if (!(dimm_mask & (1 << j)))
1646                                         continue;
1647
1648                                 printf("SPD info:  Controller=%u "
1649                                                 "DIMM=%u\n", i, j);
1650                                 generic_spd_dump(
1651                                         &(pinfo->spd_installed_dimms[i][j]));
1652                                 printf("\n");
1653                         }
1654                         printf("\n");
1655                 }
1656                 printf("\n");
1657         }
1658
1659         /* STEP 2:  DIMM Parameters */
1660         if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1661                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1662                         if (!(ctrl_mask & (1 << i)))
1663                                 continue;
1664                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1665                                 if (!(dimm_mask & (1 << j)))
1666                                         continue;
1667                                 printf("DIMM parameters:  Controller=%u "
1668                                                 "DIMM=%u\n", i, j);
1669                                 print_dimm_parameters(
1670                                         &(pinfo->dimm_params[i][j]));
1671                                 printf("\n");
1672                         }
1673                         printf("\n");
1674                 }
1675                 printf("\n");
1676         }
1677
1678         /* STEP 3:  Common Parameters */
1679         if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1680                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1681                         if (!(ctrl_mask & (1 << i)))
1682                                 continue;
1683                         printf("\"lowest common\" DIMM parameters:  "
1684                                         "Controller=%u\n", i);
1685                         print_lowest_common_dimm_parameters(
1686                                 &pinfo->common_timing_params[i]);
1687                         printf("\n");
1688                 }
1689                 printf("\n");
1690         }
1691
1692         /* STEP 4:  User Configuration Options */
1693         if (do_mask & STEP_GATHER_OPTS) {
1694                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1695                         if (!(ctrl_mask & (1 << i)))
1696                                 continue;
1697                         printf("User Config Options: Controller=%u\n", i);
1698                         print_memctl_options(&pinfo->memctl_opts[i]);
1699                         printf("\n");
1700                 }
1701                 printf("\n");
1702         }
1703
1704         /* STEP 5:  Address assignment */
1705         if (do_mask & STEP_ASSIGN_ADDRESSES) {
1706                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1707                         if (!(ctrl_mask & (1 << i)))
1708                                 continue;
1709                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1710                                 printf("Address Assignment: Controller=%u "
1711                                                 "DIMM=%u\n", i, j);
1712                                 printf("Don't have this functionality yet\n");
1713                         }
1714                         printf("\n");
1715                 }
1716                 printf("\n");
1717         }
1718
1719         /* STEP 6:  computed controller register values */
1720         if (do_mask & STEP_COMPUTE_REGS) {
1721                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1722                         if (!(ctrl_mask & (1 << i)))
1723                                 continue;
1724                         printf("Computed Register Values: Controller=%u\n", i);
1725                         print_fsl_memctl_config_regs(
1726                                 &pinfo->fsl_ddr_config_reg[i]);
1727                         retval = check_fsl_memctl_config_regs(
1728                                 &pinfo->fsl_ddr_config_reg[i]);
1729                         if (retval) {
1730                                 printf("check_fsl_memctl_config_regs "
1731                                         "result = %u\n", retval);
1732                         }
1733                         printf("\n");
1734                 }
1735                 printf("\n");
1736         }
1737 }
1738
1739 struct data_strings {
1740         const char *data_name;
1741         unsigned int step_mask;
1742         unsigned int dimm_number_required;
1743 };
1744
1745 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1746
1747 static unsigned int fsl_ddr_parse_interactive_cmd(
1748         char **argv,
1749         int argc,
1750         unsigned int *pstep_mask,
1751         unsigned int *pctlr_mask,
1752         unsigned int *pdimm_mask,
1753         unsigned int *pdimm_number_required
1754          ) {
1755
1756         static const struct data_strings options[] = {
1757                 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1758                 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1759                 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1760                 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1761                 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1762                 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1763         };
1764         static const unsigned int n_opts = ARRAY_SIZE(options);
1765
1766         unsigned int i, j;
1767         unsigned int error = 0;
1768
1769         for (i = 1; i < argc; i++) {
1770                 unsigned int matched = 0;
1771
1772                 for (j = 0; j < n_opts; j++) {
1773                         if (strcmp(options[j].data_name, argv[i]) != 0)
1774                                 continue;
1775                         *pstep_mask |= options[j].step_mask;
1776                         *pdimm_number_required =
1777                                 options[j].dimm_number_required;
1778                         matched = 1;
1779                         break;
1780                 }
1781
1782                 if (matched)
1783                         continue;
1784
1785                 if (argv[i][0] == 'c') {
1786                         char c = argv[i][1];
1787                         if (isdigit(c))
1788                                 *pctlr_mask |= 1 << (c - '0');
1789                         continue;
1790                 }
1791
1792                 if (argv[i][0] == 'd') {
1793                         char c = argv[i][1];
1794                         if (isdigit(c))
1795                                 *pdimm_mask |= 1 << (c - '0');
1796                         continue;
1797                 }
1798
1799                 printf("unknown arg %s\n", argv[i]);
1800                 *pstep_mask = 0;
1801                 error = 1;
1802                 break;
1803         }
1804
1805         return error;
1806 }
1807
1808 int fsl_ddr_interactive_env_var_exists(void)
1809 {
1810         char buffer[CONFIG_SYS_CBSIZE];
1811
1812         if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1813                 return 1;
1814
1815         return 0;
1816 }
1817
1818 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
1819 {
1820         unsigned long long ddrsize;
1821         const char *prompt = "FSL DDR>";
1822         char buffer[CONFIG_SYS_CBSIZE];
1823         char buffer2[CONFIG_SYS_CBSIZE];
1824         char *p = NULL;
1825         char *argv[CONFIG_SYS_MAXARGS + 1];     /* NULL terminated */
1826         int argc;
1827         unsigned int next_step = STEP_GET_SPD;
1828         const char *usage = {
1829                 "commands:\n"
1830                 "print      print SPD and intermediate computed data\n"
1831                 "reset      reboot machine\n"
1832                 "recompute  reload SPD and options to default and recompute regs\n"
1833                 "edit       modify spd, parameter, or option\n"
1834                 "compute    recompute registers from current next_step to end\n"
1835                 "copy       copy parameters\n"
1836                 "next_step  shows current next_step\n"
1837                 "help       this message\n"
1838                 "go         program the memory controller and continue with u-boot\n"
1839         };
1840
1841         if (var_is_set) {
1842                 if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
1843                         p = buffer2;
1844                 } else {
1845                         var_is_set = 0;
1846                 }
1847         }
1848
1849         /*
1850          * The strategy for next_step is that it points to the next
1851          * step in the computation process that needs to be done.
1852          */
1853         while (1) {
1854                 if (var_is_set) {
1855                         char *pend = strchr(p, ';');
1856                         if (pend) {
1857                                 /* found command separator, copy sub-command */
1858                                 *pend = '\0';
1859                                 strcpy(buffer, p);
1860                                 p = pend + 1;
1861                         } else {
1862                                 /* separator not found, copy whole string */
1863                                 strcpy(buffer, p);
1864                                 p = NULL;
1865                                 var_is_set = 0;
1866                         }
1867                 } else {
1868                         /*
1869                          * No need to worry for buffer overflow here in
1870                          * this function;  cli_readline() maxes out at
1871                          * CFG_CBSIZE
1872                          */
1873                         cli_readline_into_buffer(prompt, buffer, 0);
1874                 }
1875                 argc = cli_simple_parse_line(buffer, argv);
1876                 if (argc == 0)
1877                         continue;
1878
1879
1880                 if (strcmp(argv[0], "help") == 0) {
1881                         puts(usage);
1882                         continue;
1883                 }
1884
1885                 if (strcmp(argv[0], "next_step") == 0) {
1886                         printf("next_step = 0x%02X (%s)\n",
1887                                next_step,
1888                                step_to_string(next_step));
1889                         continue;
1890                 }
1891
1892                 if (strcmp(argv[0], "copy") == 0) {
1893                         unsigned int error = 0;
1894                         unsigned int step_mask = 0;
1895                         unsigned int src_ctlr_mask = 0;
1896                         unsigned int src_dimm_mask = 0;
1897                         unsigned int dimm_number_required = 0;
1898                         unsigned int src_ctlr_num = 0;
1899                         unsigned int src_dimm_num = 0;
1900                         unsigned int dst_ctlr_num = -1;
1901                         unsigned int dst_dimm_num = -1;
1902                         unsigned int i, num_dest_parms;
1903
1904                         if (argc == 1) {
1905                                 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1906                                 continue;
1907                         }
1908
1909                         error = fsl_ddr_parse_interactive_cmd(
1910                                 argv, argc,
1911                                 &step_mask,
1912                                 &src_ctlr_mask,
1913                                 &src_dimm_mask,
1914                                 &dimm_number_required
1915                         );
1916
1917                         /* XXX: only dimm_number_required and step_mask will
1918                            be used by this function.  Parse the controller and
1919                            DIMM number separately because it is easier.  */
1920
1921                         if (error)
1922                                 continue;
1923
1924                         /* parse source destination controller / DIMM */
1925
1926                         num_dest_parms = dimm_number_required ? 2 : 1;
1927
1928                         for (i = 0; i < argc; i++) {
1929                                 if (argv[i][0] == 'c') {
1930                                         char c = argv[i][1];
1931                                         if (isdigit(c)) {
1932                                                 src_ctlr_num = (c - '0');
1933                                                 break;
1934                                         }
1935                                 }
1936                         }
1937
1938                         for (i = 0; i < argc; i++) {
1939                                 if (argv[i][0] == 'd') {
1940                                         char c = argv[i][1];
1941                                         if (isdigit(c)) {
1942                                                 src_dimm_num = (c - '0');
1943                                                 break;
1944                                         }
1945                                 }
1946                         }
1947
1948                         /* parse destination controller / DIMM */
1949
1950                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1951                                 if (argv[i][0] == 'c') {
1952                                         char c = argv[i][1];
1953                                         if (isdigit(c)) {
1954                                                 dst_ctlr_num = (c - '0');
1955                                                 break;
1956                                         }
1957                                 }
1958                         }
1959
1960                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1961                                 if (argv[i][0] == 'd') {
1962                                         char c = argv[i][1];
1963                                         if (isdigit(c)) {
1964                                                 dst_dimm_num = (c - '0');
1965                                                 break;
1966                                         }
1967                                 }
1968                         }
1969
1970                         /* TODO: validate inputs */
1971
1972                         debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
1973                                 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
1974
1975
1976                         switch (step_mask) {
1977
1978                         case STEP_GET_SPD:
1979                                 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
1980                                         &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
1981                                         sizeof(pinfo->spd_installed_dimms[0][0]));
1982                                 break;
1983
1984                         case STEP_COMPUTE_DIMM_PARMS:
1985                                 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
1986                                         &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
1987                                         sizeof(pinfo->dimm_params[0][0]));
1988                                 break;
1989
1990                         case STEP_COMPUTE_COMMON_PARMS:
1991                                 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
1992                                         &(pinfo->common_timing_params[src_ctlr_num]),
1993                                         sizeof(pinfo->common_timing_params[0]));
1994                                 break;
1995
1996                         case STEP_GATHER_OPTS:
1997                                 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
1998                                         &(pinfo->memctl_opts[src_ctlr_num]),
1999                                         sizeof(pinfo->memctl_opts[0]));
2000                                 break;
2001
2002                         /* someday be able to have addresses to copy addresses... */
2003
2004                         case STEP_COMPUTE_REGS:
2005                                 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2006                                         &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2007                                         sizeof(pinfo->memctl_opts[0]));
2008                                 break;
2009
2010                         default:
2011                                 printf("unexpected step_mask value\n");
2012                         }
2013
2014                         continue;
2015
2016                 }
2017
2018                 if (strcmp(argv[0], "edit") == 0) {
2019                         unsigned int error = 0;
2020                         unsigned int step_mask = 0;
2021                         unsigned int ctlr_mask = 0;
2022                         unsigned int dimm_mask = 0;
2023                         char *p_element = NULL;
2024                         char *p_value = NULL;
2025                         unsigned int dimm_number_required = 0;
2026                         unsigned int ctrl_num;
2027                         unsigned int dimm_num;
2028
2029                         if (argc == 1) {
2030                                 /* Only the element and value must be last */
2031                                 printf("edit <c#> <d#> "
2032                                         "<spd|dimmparms|commonparms|opts|"
2033                                         "addresses|regs> <element> <value>\n");
2034                                 printf("for spd, specify byte number for "
2035                                         "element\n");
2036                                 continue;
2037                         }
2038
2039                         error = fsl_ddr_parse_interactive_cmd(
2040                                 argv, argc - 2,
2041                                 &step_mask,
2042                                 &ctlr_mask,
2043                                 &dimm_mask,
2044                                 &dimm_number_required
2045                         );
2046
2047                         if (error)
2048                                 continue;
2049
2050
2051                         /* Check arguments */
2052
2053                         /* ERROR: If no steps were found */
2054                         if (step_mask == 0) {
2055                                 printf("Error: No valid steps were specified "
2056                                                 "in argument.\n");
2057                                 continue;
2058                         }
2059
2060                         /* ERROR: If multiple steps were found */
2061                         if (step_mask & (step_mask - 1)) {
2062                                 printf("Error: Multiple steps specified in "
2063                                                 "argument.\n");
2064                                 continue;
2065                         }
2066
2067                         /* ERROR: Controller not specified */
2068                         if (ctlr_mask == 0) {
2069                                 printf("Error: controller number not "
2070                                         "specified or no element and "
2071                                         "value specified\n");
2072                                 continue;
2073                         }
2074
2075                         if (ctlr_mask & (ctlr_mask - 1)) {
2076                                 printf("Error: multiple controllers "
2077                                                 "specified, %X\n", ctlr_mask);
2078                                 continue;
2079                         }
2080
2081                         /* ERROR: DIMM number not specified */
2082                         if (dimm_number_required && dimm_mask == 0) {
2083                                 printf("Error: DIMM number number not "
2084                                         "specified or no element and "
2085                                         "value specified\n");
2086                                 continue;
2087                         }
2088
2089                         if (dimm_mask & (dimm_mask - 1)) {
2090                                 printf("Error: multipled DIMMs specified\n");
2091                                 continue;
2092                         }
2093
2094                         p_element = argv[argc - 2];
2095                         p_value = argv[argc - 1];
2096
2097                         ctrl_num = __ilog2(ctlr_mask);
2098                         dimm_num = __ilog2(dimm_mask);
2099
2100                         switch (step_mask) {
2101                         case STEP_GET_SPD:
2102                                 {
2103                                         unsigned int element_num;
2104                                         unsigned int value;
2105
2106                                         element_num = simple_strtoul(p_element,
2107                                                                      NULL, 0);
2108                                         value = simple_strtoul(p_value,
2109                                                                NULL, 0);
2110                                         fsl_ddr_spd_edit(pinfo,
2111                                                                ctrl_num,
2112                                                                dimm_num,
2113                                                                element_num,
2114                                                                value);
2115                                         next_step = STEP_COMPUTE_DIMM_PARMS;
2116                                 }
2117                                 break;
2118
2119                         case STEP_COMPUTE_DIMM_PARMS:
2120                                 fsl_ddr_dimm_parameters_edit(
2121                                                  pinfo, ctrl_num, dimm_num,
2122                                                  p_element, p_value);
2123                                 next_step = STEP_COMPUTE_COMMON_PARMS;
2124                                 break;
2125
2126                         case STEP_COMPUTE_COMMON_PARMS:
2127                                 lowest_common_dimm_parameters_edit(pinfo,
2128                                                 ctrl_num, p_element, p_value);
2129                                 next_step = STEP_GATHER_OPTS;
2130                                 break;
2131
2132                         case STEP_GATHER_OPTS:
2133                                 fsl_ddr_options_edit(pinfo, ctrl_num,
2134                                                            p_element, p_value);
2135                                 next_step = STEP_ASSIGN_ADDRESSES;
2136                                 break;
2137
2138                         case STEP_ASSIGN_ADDRESSES:
2139                                 printf("editing of address assignment "
2140                                                 "not yet implemented\n");
2141                                 break;
2142
2143                         case STEP_COMPUTE_REGS:
2144                                 {
2145                                         fsl_ddr_regs_edit(pinfo,
2146                                                                 ctrl_num,
2147                                                                 p_element,
2148                                                                 p_value);
2149                                         next_step = STEP_PROGRAM_REGS;
2150                                 }
2151                                 break;
2152
2153                         default:
2154                                 printf("programming error\n");
2155                                 while (1)
2156                                         ;
2157                                 break;
2158                         }
2159                         continue;
2160                 }
2161
2162                 if (strcmp(argv[0], "reset") == 0) {
2163                         /*
2164                          * Reboot machine.
2165                          * Args don't seem to matter because this
2166                          * doesn't return
2167                          */
2168                         do_reset(NULL, 0, 0, NULL);
2169                         printf("Reset didn't work\n");
2170                 }
2171
2172                 if (strcmp(argv[0], "recompute") == 0) {
2173                         /*
2174                          * Recalculate everything, starting with
2175                          * loading SPD EEPROM from DIMMs
2176                          */
2177                         next_step = STEP_GET_SPD;
2178                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2179                         continue;
2180                 }
2181
2182                 if (strcmp(argv[0], "compute") == 0) {
2183                         /*
2184                          * Compute rest of steps starting at
2185                          * the current next_step/
2186                          */
2187                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2188                         continue;
2189                 }
2190
2191                 if (strcmp(argv[0], "print") == 0) {
2192                         unsigned int error = 0;
2193                         unsigned int step_mask = 0;
2194                         unsigned int ctlr_mask = 0;
2195                         unsigned int dimm_mask = 0;
2196                         unsigned int dimm_number_required = 0;
2197
2198                         if (argc == 1) {
2199                                 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2200                                   "[commonparms] [opts] [addresses] [regs]\n");
2201                                 continue;
2202                         }
2203
2204                         error = fsl_ddr_parse_interactive_cmd(
2205                                 argv, argc,
2206                                 &step_mask,
2207                                 &ctlr_mask,
2208                                 &dimm_mask,
2209                                 &dimm_number_required
2210                         );
2211
2212                         if (error)
2213                                 continue;
2214
2215                         /* If no particular controller was found, print all */
2216                         if (ctlr_mask == 0)
2217                                 ctlr_mask = 0xFF;
2218
2219                         /* If no particular dimm was found, print all dimms. */
2220                         if (dimm_mask == 0)
2221                                 dimm_mask = 0xFF;
2222
2223                         /* If no steps were found, print all steps. */
2224                         if (step_mask == 0)
2225                                 step_mask = STEP_ALL;
2226
2227                         fsl_ddr_printinfo(pinfo, ctlr_mask,
2228                                                 dimm_mask, step_mask);
2229                         continue;
2230                 }
2231
2232                 if (strcmp(argv[0], "go") == 0) {
2233                         if (next_step)
2234                                 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2235                         break;
2236                 }
2237
2238                 printf("unknown command %s\n", argv[0]);
2239         }
2240
2241         debug("end of memory = %llu\n", (u64)ddrsize);
2242
2243         return ddrsize;
2244 }