drivers/ddr/fsl/main.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <fsl_ddr.h>
  19
  20 /*
  21  * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  22  * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
  23  * all Power SoCs. But it could be different for ARM SoCs. For example,
  24  * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  25  * 0x00_8000_0000 ~ 0x00_ffff_ffff
  26  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  27  */
  28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
  29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
  30 #endif
  31
  32 #ifdef CONFIG_PPC
  33 #include <asm/fsl_law.h>
  34
  35 void fsl_ddr_set_lawbar(
  36                 const common_timing_params_t *memctl_common_params,
  37                 unsigned int memctl_interleaved,
  38                 unsigned int ctrl_num);
  39 #endif
  40
  41 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  42 #if defined(SPD_EEPROM_ADDRESS) || \
  43     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  44     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  45 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  47         [0][0] = SPD_EEPROM_ADDRESS,
  48 };
  49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  51         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  52         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  53 };
  54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  56         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  57         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  58 };
  59 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  60 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  61         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  62         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  63         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  64         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  65 };
  66 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  67 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  68         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  69         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  70         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  71 };
  72 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  73 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  74         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  75         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  76         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  77         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  78         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  79         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  80 };
  81
  82 #endif
  83
  84 #define SPD_SPA0_ADDRESS        0x36
  85 #define SPD_SPA1_ADDRESS        0x37
  86
  87 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  88 {
  89         int ret;
  90 #ifdef CONFIG_SYS_FSL_DDR4
  91         uint8_t dummy = 0;
  92 #endif
  93
  94         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  95
  96 #ifdef CONFIG_SYS_FSL_DDR4
  97         /*
  98          * DDR4 SPD has 384 to 512 bytes
  99          * To access the lower 256 bytes, we need to set EE page address to 0
 100          * To access the upper 256 bytes, we need to set EE page address to 1
 101          * See Jedec standar No. 21-C for detail
 102          */
 103         i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
 104         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
 105         if (!ret) {
 106                 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
 107                 ret = i2c_read(i2c_address, 0, 1,
 108                                (uchar *)((ulong)spd + 256),
 109                                min(256, sizeof(generic_spd_eeprom_t) - 256));
 110         }
 111 #else
 112         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
 113                                 sizeof(generic_spd_eeprom_t));
 114 #endif
 115
 116         if (ret) {
 117                 if (i2c_address ==
 118 #ifdef SPD_EEPROM_ADDRESS
 119                                 SPD_EEPROM_ADDRESS
 120 #elif defined(SPD_EEPROM_ADDRESS1)
 121                                 SPD_EEPROM_ADDRESS1
 122 #endif
 123                                 ) {
 124                         printf("DDR: failed to read SPD from address %u\n",
 125                                 i2c_address);
 126                 } else {
 127                         debug("DDR: failed to read SPD from address %u\n",
 128                                 i2c_address);
 129                 }
 130                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
 131         }
 132 }
 133
 134 __attribute__((weak, alias("__get_spd")))
 135 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 136
 137 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 138                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 139 {
 140         unsigned int i;
 141         unsigned int i2c_address = 0;
 142
 143         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
 144                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 145                 return;
 146         }
 147
 148         for (i = 0; i < dimm_slots_per_ctrl; i++) {
 149                 i2c_address = spd_i2c_addr[ctrl_num][i];
 150                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 151         }
 152 }
 153 #else
 154 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 155                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 156 {
 157 }
 158 #endif /* SPD_EEPROM_ADDRESSx */
 159
 160 /*
 161  * ASSUMPTIONS:
 162  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 163  *    - Same memory data bus width on all controllers
 164  *
 165  * NOTES:
 166  *
 167  * The memory controller and associated documentation use confusing
 168  * terminology when referring to the orgranization of DRAM.
 169  *
 170  * Here is a terminology translation table:
 171  *
 172  * memory controller/documention  |industry   |this code  |signals
 173  * -------------------------------|-----------|-----------|-----------------
 174  * physical bank/bank             |rank       |rank       |chip select (CS)
 175  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 176  * page/row                       |row        |page       |row address
 177  * ???                            |column     |column     |column address
 178  *
 179  * The naming confusion is further exacerbated by the descriptions of the
 180  * memory controller interleaving feature, where accesses are interleaved
 181  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 182  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 183  *
 184  * memory controller documentation | number of chip selects
 185  *                                 | per memory controller supported
 186  * --------------------------------|-----------------------------------------
 187  * cache line interleaving         | 1 (CS0 only)
 188  * page interleaving               | 1 (CS0 only)
 189  * bank interleaving               | 1 (CS0 only)
 190  * superbank interleraving         | depends on bank (chip select)
 191  *                                 |   interleraving [rank interleaving]
 192  *                                 |   mode used on every memory controller
 193  *
 194  * Even further confusing is the existence of the interleaving feature
 195  * _WITHIN_ each memory controller.  The feature is referred to in
 196  * documentation as chip select interleaving or bank interleaving,
 197  * although it is configured in the DDR_SDRAM_CFG field.
 198  *
 199  * Name of field                | documentation name    | this code
 200  * -----------------------------|-----------------------|------------------
 201  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 202  *                              |  interleaving
 203  */
 204
 205 const char *step_string_tbl[] = {
 206         "STEP_GET_SPD",
 207         "STEP_COMPUTE_DIMM_PARMS",
 208         "STEP_COMPUTE_COMMON_PARMS",
 209         "STEP_GATHER_OPTS",
 210         "STEP_ASSIGN_ADDRESSES",
 211         "STEP_COMPUTE_REGS",
 212         "STEP_PROGRAM_REGS",
 213         "STEP_ALL"
 214 };
 215
 216 const char * step_to_string(unsigned int step) {
 217
 218         unsigned int s = __ilog2(step);
 219
 220         if ((1 << s) != step)
 221                 return step_string_tbl[7];
 222
 223         if (s >= ARRAY_SIZE(step_string_tbl)) {
 224                 printf("Error for the step in %s\n", __func__);
 225                 s = 0;
 226         }
 227
 228         return step_string_tbl[s];
 229 }
 230
 231 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 232                           unsigned int dbw_cap_adj[])
 233 {
 234         unsigned int i, j;
 235         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 236         unsigned long long rank_density, ctlr_density = 0;
 237         unsigned int first_ctrl = pinfo->first_ctrl;
 238         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 239
 240         /*
 241          * If a reduced data width is requested, but the SPD
 242          * specifies a physically wider device, adjust the
 243          * computed dimm capacities accordingly before
 244          * assigning addresses.
 245          */
 246         for (i = first_ctrl; i <= last_ctrl; i++) {
 247                 unsigned int found = 0;
 248
 249                 switch (pinfo->memctl_opts[i].data_bus_width) {
 250                 case 2:
 251                         /* 16-bit */
 252                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 253                                 unsigned int dw;
 254                                 if (!pinfo->dimm_params[i][j].n_ranks)
 255                                         continue;
 256                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 257                                 if ((dw == 72 || dw == 64)) {
 258                                         dbw_cap_adj[i] = 2;
 259                                         break;
 260                                 } else if ((dw == 40 || dw == 32)) {
 261                                         dbw_cap_adj[i] = 1;
 262                                         break;
 263                                 }
 264                         }
 265                         break;
 266
 267                 case 1:
 268                         /* 32-bit */
 269                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 270                                 unsigned int dw;
 271                                 dw = pinfo->dimm_params[i][j].data_width;
 272                                 if (pinfo->dimm_params[i][j].n_ranks
 273                                     && (dw == 72 || dw == 64)) {
 274                                         /*
 275                                          * FIXME: can't really do it
 276                                          * like this because this just
 277                                          * further reduces the memory
 278                                          */
 279                                         found = 1;
 280                                         break;
 281                                 }
 282                         }
 283                         if (found) {
 284                                 dbw_cap_adj[i] = 1;
 285                         }
 286                         break;
 287
 288                 case 0:
 289                         /* 64-bit */
 290                         break;
 291
 292                 default:
 293                         printf("unexpected data bus width "
 294                                 "specified controller %u\n", i);
 295                         return 1;
 296                 }
 297                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 298         }
 299
 300         current_mem_base = pinfo->mem_base;
 301         total_mem = 0;
 302         if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
 303                 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
 304                                         dbw_cap_adj[first_ctrl];
 305                 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
 306                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 307                 case FSL_DDR_CS0_CS1_CS2_CS3:
 308                         ctlr_density = 4 * rank_density;
 309                         break;
 310                 case FSL_DDR_CS0_CS1:
 311                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 312                         ctlr_density = 2 * rank_density;
 313                         break;
 314                 case FSL_DDR_CS2_CS3:
 315                 default:
 316                         ctlr_density = rank_density;
 317                         break;
 318                 }
 319                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 320                         rank_density, ctlr_density);
 321                 for (i = first_ctrl; i <= last_ctrl; i++) {
 322                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 323                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 324                                 case FSL_DDR_256B_INTERLEAVING:
 325                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 326                                 case FSL_DDR_PAGE_INTERLEAVING:
 327                                 case FSL_DDR_BANK_INTERLEAVING:
 328                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 329                                         total_ctlr_mem = 2 * ctlr_density;
 330                                         break;
 331                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 332                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 333                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 334                                         total_ctlr_mem = 3 * ctlr_density;
 335                                         break;
 336                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 337                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 338                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 339                                         total_ctlr_mem = 4 * ctlr_density;
 340                                         break;
 341                                 default:
 342                                         panic("Unknown interleaving mode");
 343                                 }
 344                                 pinfo->common_timing_params[i].base_address =
 345                                                         current_mem_base;
 346                                 pinfo->common_timing_params[i].total_mem =
 347                                                         total_ctlr_mem;
 348                                 total_mem = current_mem_base + total_ctlr_mem;
 349                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 350                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 351                         } else {
 352                                 /* when 3rd controller not interleaved */
 353                                 current_mem_base = total_mem;
 354                                 total_ctlr_mem = 0;
 355                                 pinfo->common_timing_params[i].base_address =
 356                                                         current_mem_base;
 357                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 358                                         unsigned long long cap =
 359                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 360                                         pinfo->dimm_params[i][j].base_address =
 361                                                 current_mem_base;
 362                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 363                                         current_mem_base += cap;
 364                                         total_ctlr_mem += cap;
 365                                 }
 366                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 367                                 pinfo->common_timing_params[i].total_mem =
 368                                                         total_ctlr_mem;
 369                                 total_mem += total_ctlr_mem;
 370                         }
 371                 }
 372         } else {
 373                 /*
 374                  * Simple linear assignment if memory
 375                  * controllers are not interleaved.
 376                  */
 377                 for (i = first_ctrl; i <= last_ctrl; i++) {
 378                         total_ctlr_mem = 0;
 379                         pinfo->common_timing_params[i].base_address =
 380                                                 current_mem_base;
 381                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 382                                 /* Compute DIMM base addresses. */
 383                                 unsigned long long cap =
 384                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 385                                 pinfo->dimm_params[i][j].base_address =
 386                                         current_mem_base;
 387                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 388                                 current_mem_base += cap;
 389                                 total_ctlr_mem += cap;
 390                         }
 391                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 392                         pinfo->common_timing_params[i].total_mem =
 393                                                         total_ctlr_mem;
 394                         total_mem += total_ctlr_mem;
 395                 }
 396         }
 397         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 398
 399         return total_mem;
 400 }
 401
 402 /* Use weak function to allow board file to override the address assignment */
 403 __attribute__((weak, alias("__step_assign_addresses")))
 404 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 405                           unsigned int dbw_cap_adj[]);
 406
 407 unsigned long long
 408 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 409                                        unsigned int size_only)
 410 {
 411         unsigned int i, j;
 412         unsigned long long total_mem = 0;
 413         int assert_reset = 0;
 414         unsigned int first_ctrl =  pinfo->first_ctrl;
 415         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 416         __maybe_unused int retval;
 417         __maybe_unused bool goodspd = false;
 418         __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
 419
 420         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 421         common_timing_params_t *timing_params = pinfo->common_timing_params;
 422         if (pinfo->board_need_mem_reset)
 423                 assert_reset = pinfo->board_need_mem_reset();
 424
 425         /* data bus width capacity adjust shift amount */
 426         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 427
 428         for (i = first_ctrl; i <= last_ctrl; i++)
 429                 dbw_capacity_adjust[i] = 0;
 430
 431         debug("starting at step %u (%s)\n",
 432               start_step, step_to_string(start_step));
 433
 434         switch (start_step) {
 435         case STEP_GET_SPD:
 436 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 437                 /* STEP 1:  Gather all DIMM SPD data */
 438                 for (i = first_ctrl; i <= last_ctrl; i++) {
 439                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
 440                                         dimm_slots_per_ctrl);
 441                 }
 442
 443         case STEP_COMPUTE_DIMM_PARMS:
 444                 /* STEP 2:  Compute DIMM parameters from SPD data */
 445
 446                 for (i = first_ctrl; i <= last_ctrl; i++) {
 447                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 448                                 generic_spd_eeprom_t *spd =
 449                                         &(pinfo->spd_installed_dimms[i][j]);
 450                                 dimm_params_t *pdimm =
 451                                         &(pinfo->dimm_params[i][j]);
 452                                 retval = compute_dimm_parameters(spd, pdimm, i);
 453 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 454                                 if (!i && !j && retval) {
 455                                         printf("SPD error on controller %d! "
 456                                         "Trying fallback to raw timing "
 457                                         "calculation\n", i);
 458                                         retval = fsl_ddr_get_dimm_params(pdimm,
 459                                                                          i, j);
 460                                 }
 461 #else
 462                                 if (retval == 2) {
 463                                         printf("Error: compute_dimm_parameters"
 464                                         " non-zero returned FATAL value "
 465                                         "for memctl=%u dimm=%u\n", i, j);
 466                                         return 0;
 467                                 }
 468 #endif
 469                                 if (retval) {
 470                                         debug("Warning: compute_dimm_parameters"
 471                                         " non-zero return value for memctl=%u "
 472                                         "dimm=%u\n", i, j);
 473                                 } else {
 474                                         goodspd = true;
 475                                 }
 476                         }
 477                 }
 478                 if (!goodspd) {
 479                         /*
 480                          * No valid SPD found
 481                          * Throw an error if this is for main memory, i.e.
 482                          * first_ctrl == 0. Otherwise, siliently return 0
 483                          * as the memory size.
 484                          */
 485                         if (first_ctrl == 0)
 486                                 printf("Error: No valid SPD detected.\n");
 487
 488                         return 0;
 489                 }
 490 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 491         case STEP_COMPUTE_DIMM_PARMS:
 492                 for (i = first_ctrl; i <= last_ctrl; i++) {
 493                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 494                                 dimm_params_t *pdimm =
 495                                         &(pinfo->dimm_params[i][j]);
 496                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 497                         }
 498                 }
 499                 debug("Filling dimm parameters from board specific file\n");
 500 #endif
 501         case STEP_COMPUTE_COMMON_PARMS:
 502                 /*
 503                  * STEP 3: Compute a common set of timing parameters
 504                  * suitable for all of the DIMMs on each memory controller
 505                  */
 506                 for (i = first_ctrl; i <= last_ctrl; i++) {
 507                         debug("Computing lowest common DIMM"
 508                                 " parameters for memctl=%u\n", i);
 509                         compute_lowest_common_dimm_parameters(
 510                                 pinfo->dimm_params[i],
 511                                 &timing_params[i],
 512                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 513                 }
 514
 515         case STEP_GATHER_OPTS:
 516                 /* STEP 4:  Gather configuration requirements from user */
 517                 for (i = first_ctrl; i <= last_ctrl; i++) {
 518                         debug("Reloading memory controller "
 519                                 "configuration options for memctl=%u\n", i);
 520                         /*
 521                          * This "reloads" the memory controller options
 522                          * to defaults.  If the user "edits" an option,
 523                          * next_step points to the step after this,
 524                          * which is currently STEP_ASSIGN_ADDRESSES.
 525                          */
 526                         populate_memctl_options(
 527                                         timing_params[i].all_dimms_registered,
 528                                         &pinfo->memctl_opts[i],
 529                                         pinfo->dimm_params[i], i);
 530                         /*
 531                          * For RDIMMs, JEDEC spec requires clocks to be stable
 532                          * before reset signal is deasserted. For the boards
 533                          * using fixed parameters, this function should be
 534                          * be called from board init file.
 535                          */
 536                         if (timing_params[i].all_dimms_registered)
 537                                 assert_reset = 1;
 538                 }
 539                 if (assert_reset && !size_only) {
 540                         if (pinfo->board_mem_reset) {
 541                                 debug("Asserting mem reset\n");
 542                                 pinfo->board_mem_reset();
 543                         } else {
 544                                 debug("Asserting mem reset missing\n");
 545                         }
 546                 }
 547
 548         case STEP_ASSIGN_ADDRESSES:
 549                 /* STEP 5:  Assign addresses to chip selects */
 550                 check_interleaving_options(pinfo);
 551                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 552                 debug("Total mem %llu assigned\n", total_mem);
 553
 554         case STEP_COMPUTE_REGS:
 555                 /* STEP 6:  compute controller register values */
 556                 debug("FSL Memory ctrl register computation\n");
 557                 for (i = first_ctrl; i <= last_ctrl; i++) {
 558                         if (timing_params[i].ndimms_present == 0) {
 559                                 memset(&ddr_reg[i], 0,
 560                                         sizeof(fsl_ddr_cfg_regs_t));
 561                                 continue;
 562                         }
 563
 564                         compute_fsl_memctl_config_regs(
 565                                         &pinfo->memctl_opts[i],
 566                                         &ddr_reg[i], &timing_params[i],
 567                                         pinfo->dimm_params[i],
 568                                         dbw_capacity_adjust[i],
 569                                         size_only);
 570                 }
 571
 572         default:
 573                 break;
 574         }
 575
 576         {
 577                 /*
 578                  * Compute the amount of memory available just by
 579                  * looking for the highest valid CSn_BNDS value.
 580                  * This allows us to also experiment with using
 581                  * only CS0 when using dual-rank DIMMs.
 582                  */
 583                 unsigned int max_end = 0;
 584
 585                 for (i = first_ctrl; i <= last_ctrl; i++) {
 586                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 587                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 588                                 if (reg->cs[j].config & 0x80000000) {
 589                                         unsigned int end;
 590                                         /*
 591                                          * 0xfffffff is a special value we put
 592                                          * for unused bnds
 593                                          */
 594                                         if (reg->cs[j].bnds == 0xffffffff)
 595                                                 continue;
 596                                         end = reg->cs[j].bnds & 0xffff;
 597                                         if (end > max_end) {
 598                                                 max_end = end;
 599                                         }
 600                                 }
 601                         }
 602                 }
 603
 604                 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
 605                             0xFFFFFFULL) - pinfo->mem_base;
 606         }
 607
 608         return total_mem;
 609 }
 610
 611 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 612 {
 613         unsigned int i, first_ctrl, last_ctrl;
 614 #ifdef CONFIG_PPC
 615         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 616 #endif
 617         unsigned long long total_memory;
 618         int deassert_reset = 0;
 619
 620         first_ctrl = pinfo->first_ctrl;
 621         last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 622
 623         /* Compute it once normally. */
 624 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 625         if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 626                 total_memory = fsl_ddr_interactive(pinfo, 0);
 627         } else if (fsl_ddr_interactive_env_var_exists()) {
 628                 total_memory = fsl_ddr_interactive(pinfo, 1);
 629         } else
 630 #endif
 631                 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
 632
 633         /* setup 3-way interleaving before enabling DDRC */
 634         switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
 635         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 636         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 637         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 638                 fsl_ddr_set_intl3r(
 639                         pinfo->memctl_opts[first_ctrl].
 640                         memctl_interleaving_mode);
 641                 break;
 642         default:
 643                 break;
 644         }
 645
 646         /*
 647          * Program configuration registers.
 648          * JEDEC specs requires clocks to be stable before deasserting reset
 649          * for RDIMMs. Clocks start after chip select is enabled and clock
 650          * control register is set. During step 1, all controllers have their
 651          * registers set but not enabled. Step 2 proceeds after deasserting
 652          * reset through board FPGA or GPIO.
 653          * For non-registered DIMMs, initialization can go through but it is
 654          * also OK to follow the same flow.
 655          */
 656         if (pinfo->board_need_mem_reset)
 657                 deassert_reset = pinfo->board_need_mem_reset();
 658         for (i = first_ctrl; i <= last_ctrl; i++) {
 659                 if (pinfo->common_timing_params[i].all_dimms_registered)
 660                         deassert_reset = 1;
 661         }
 662         for (i = first_ctrl; i <= last_ctrl; i++) {
 663                 debug("Programming controller %u\n", i);
 664                 if (pinfo->common_timing_params[i].ndimms_present == 0) {
 665                         debug("No dimms present on controller %u; "
 666                                         "skipping programming\n", i);
 667                         continue;
 668                 }
 669                 /*
 670                  * The following call with step = 1 returns before enabling
 671                  * the controller. It has to finish with step = 2 later.
 672                  */
 673                 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
 674                                         deassert_reset ? 1 : 0);
 675         }
 676         if (deassert_reset) {
 677                 /* Use board FPGA or GPIO to deassert reset signal */
 678                 if (pinfo->board_mem_de_reset) {
 679                         debug("Deasserting mem reset\n");
 680                         pinfo->board_mem_de_reset();
 681                 } else {
 682                         debug("Deasserting mem reset missing\n");
 683                 }
 684                 for (i = first_ctrl; i <= last_ctrl; i++) {
 685                         /* Call with step = 2 to continue initialization */
 686                         fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
 687                                                 i, 2);
 688                 }
 689         }
 690
 691 #ifdef CONFIG_PPC
 692         /* program LAWs */
 693         for (i = first_ctrl; i <= last_ctrl; i++) {
 694                 if (pinfo->memctl_opts[i].memctl_interleaving) {
 695                         switch (pinfo->memctl_opts[i].
 696                                 memctl_interleaving_mode) {
 697                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 698                         case FSL_DDR_PAGE_INTERLEAVING:
 699                         case FSL_DDR_BANK_INTERLEAVING:
 700                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 701                                 if (i % 2)
 702                                         break;
 703                                 if (i == 0) {
 704                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 705                                         fsl_ddr_set_lawbar(
 706                                                 &pinfo->common_timing_params[i],
 707                                                 law_memctl, i);
 708                                 }
 709 #if CONFIG_NUM_DDR_CONTROLLERS > 3
 710                                 else if (i == 2) {
 711                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 712                                         fsl_ddr_set_lawbar(
 713                                                 &pinfo->common_timing_params[i],
 714                                                 law_memctl, i);
 715                                 }
 716 #endif
 717                                 break;
 718                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 719                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 720                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 721                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 722                                 if (i == 0) {
 723                                         fsl_ddr_set_lawbar(
 724                                                 &pinfo->common_timing_params[i],
 725                                                 law_memctl, i);
 726                                 }
 727                                 break;
 728                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 729                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 730                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 731                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 732                                 if (i == 0)
 733                                         fsl_ddr_set_lawbar(
 734                                                 &pinfo->common_timing_params[i],
 735                                                 law_memctl, i);
 736                                 /* place holder for future 4-way interleaving */
 737                                 break;
 738                         default:
 739                                 break;
 740                         }
 741                 } else {
 742                         switch (i) {
 743                         case 0:
 744                                 law_memctl = LAW_TRGT_IF_DDR_1;
 745                                 break;
 746                         case 1:
 747                                 law_memctl = LAW_TRGT_IF_DDR_2;
 748                                 break;
 749                         case 2:
 750                                 law_memctl = LAW_TRGT_IF_DDR_3;
 751                                 break;
 752                         case 3:
 753                                 law_memctl = LAW_TRGT_IF_DDR_4;
 754                                 break;
 755                         default:
 756                                 break;
 757                         }
 758                         fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
 759                                            law_memctl, i);
 760                 }
 761         }
 762 #endif
 763
 764         debug("total_memory by %s = %llu\n", __func__, total_memory);
 765
 766 #if !defined(CONFIG_PHYS_64BIT)
 767         /* Check for 4G or more.  Bad. */
 768         if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
 769                 puts("Detected ");
 770                 print_size(total_memory, " of memory\n");
 771                 printf("       This U-Boot only supports < 4G of DDR\n");
 772                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 773                 printf("       "); /* re-align to match init_func_ram print */
 774                 total_memory = CONFIG_MAX_MEM_MAPPED;
 775         }
 776 #endif
 777
 778         return total_memory;
 779 }
 780
 781 /*
 782  * fsl_ddr_sdram(void) -- this is the main function to be
 783  * called by initdram() in the board file.
 784  *
 785  * It returns amount of memory configured in bytes.
 786  */
 787 phys_size_t fsl_ddr_sdram(void)
 788 {
 789         fsl_ddr_info_t info;
 790
 791         /* Reset info structure. */
 792         memset(&info, 0, sizeof(fsl_ddr_info_t));
 793         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 794         info.first_ctrl = 0;
 795         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 796         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 797         info.board_need_mem_reset = board_need_mem_reset;
 798         info.board_mem_reset = board_assert_mem_reset;
 799         info.board_mem_de_reset = board_deassert_mem_reset;
 800
 801         return __fsl_ddr_sdram(&info);
 802 }
 803
 804 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 805 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
 806                                 unsigned int first_ctrl,
 807                                 unsigned int num_ctrls,
 808                                 unsigned int dimm_slots_per_ctrl,
 809                                 int (*board_need_reset)(void),
 810                                 void (*board_reset)(void),
 811                                 void (*board_de_reset)(void))
 812 {
 813         fsl_ddr_info_t info;
 814
 815         /* Reset info structure. */
 816         memset(&info, 0, sizeof(fsl_ddr_info_t));
 817         info.mem_base = base;
 818         info.first_ctrl = first_ctrl;
 819         info.num_ctrls = num_ctrls;
 820         info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
 821         info.board_need_mem_reset = board_need_reset;
 822         info.board_mem_reset = board_reset;
 823         info.board_mem_de_reset = board_de_reset;
 824
 825         return __fsl_ddr_sdram(&info);
 826 }
 827 #endif
 828
 829 /*
 830  * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
 831  * size of the total memory without setting ddr control registers.
 832  */
 833 phys_size_t
 834 fsl_ddr_sdram_size(void)
 835 {
 836         fsl_ddr_info_t  info;
 837         unsigned long long total_memory = 0;
 838
 839         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 840         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 841         info.first_ctrl = 0;
 842         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 843         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 844         info.board_need_mem_reset = NULL;
 845
 846         /* Compute it once normally. */
 847         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 848
 849         return total_memory;
 850 }