2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 DECLARE_GLOBAL_DATA_PTR;
54 /* Return the XFERTYP flags for a given command and data packet */
55 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
60 xfertyp |= XFERTYP_DPSEL;
61 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
62 xfertyp |= XFERTYP_DMAEN;
64 if (data->blocks > 1) {
65 xfertyp |= XFERTYP_MSBSEL;
66 xfertyp |= XFERTYP_BCEN;
67 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
68 xfertyp |= XFERTYP_AC12EN;
72 if (data->flags & MMC_DATA_READ)
73 xfertyp |= XFERTYP_DTDSEL;
76 if (cmd->resp_type & MMC_RSP_CRC)
77 xfertyp |= XFERTYP_CCCEN;
78 if (cmd->resp_type & MMC_RSP_OPCODE)
79 xfertyp |= XFERTYP_CICEN;
80 if (cmd->resp_type & MMC_RSP_136)
81 xfertyp |= XFERTYP_RSPTYP_136;
82 else if (cmd->resp_type & MMC_RSP_BUSY)
83 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
84 else if (cmd->resp_type & MMC_RSP_PRESENT)
85 xfertyp |= XFERTYP_RSPTYP_48;
87 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
88 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
89 xfertyp |= XFERTYP_CMDTYP_ABORT;
91 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
94 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
96 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
99 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
101 struct fsl_esdhc_cfg *cfg = mmc->priv;
102 struct fsl_esdhc *regs = cfg->esdhc_base;
108 int wml = esdhc_read32(®s->wml);
110 if (data->flags & MMC_DATA_READ) {
111 wml &= WML_RD_WML_MASK;
112 blocks = data->blocks;
115 timeout = PIO_TIMEOUT;
116 size = data->blocksize;
118 !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
122 while (!((prsstat = esdhc_read32(®s->prsstat)) &
123 PRSSTAT_BREN) && --timeout)
125 if (!(prsstat & PRSSTAT_BREN)) {
126 printf("%s: Data Read Failed in PIO Mode\n",
130 for (i = 0; i < wml && size; i++) {
131 databuf = in_le32(®s->datport);
132 memcpy(buffer, &databuf, sizeof(databuf));
140 wml = (wml & WML_WR_WML_MASK) >> 16;
141 blocks = data->blocks;
142 buffer = (char *)data->src; /* cast away 'const' */
144 timeout = PIO_TIMEOUT;
145 size = data->blocksize;
147 !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
151 while (!((prsstat = esdhc_read32(®s->prsstat)) &
152 PRSSTAT_BWEN) && --timeout)
154 if (!(prsstat & PRSSTAT_BWEN)) {
155 printf("%s: Data Write Failed in PIO Mode\n",
159 for (i = 0; i < wml && size; i++) {
160 memcpy(&databuf, buffer, sizeof(databuf));
161 out_le32(®s->datport, databuf);
172 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
175 struct fsl_esdhc_cfg *cfg = mmc->priv;
176 struct fsl_esdhc *regs = cfg->esdhc_base;
177 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
180 wml_value = data->blocksize / 4;
182 if (data->flags & MMC_DATA_READ) {
183 if (wml_value > WML_RD_WML_MAX)
184 wml_value = WML_RD_WML_MAX_VAL;
186 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
187 esdhc_write32(®s->dsaddr, (u32)data->dest);
189 if (wml_value > WML_WR_WML_MAX)
190 wml_value = WML_WR_WML_MAX_VAL;
191 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
192 printf("The SD card is locked. Can not write to a locked card.\n");
196 flush_dcache_range((unsigned long)data->src,
197 (unsigned long)data->src + data->blocks * data->blocksize);
198 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
200 esdhc_write32(®s->dsaddr, (u32)data->src);
202 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
203 if (!(data->flags & MMC_DATA_READ)) {
204 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
205 printf("The SD card is locked. Can not write to a locked card.\n");
208 esdhc_write32(®s->dsaddr, (u32)data->src);
210 esdhc_write32(®s->dsaddr, (u32)data->dest);
212 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
214 esdhc_write32(®s->blkattr, (data->blocks << 16) | data->blocksize);
216 /* Calculate the timeout period for data transactions */
218 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
219 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
220 * So, Number of SD Clock cycles for 0.25sec should be minimum
221 * (SD Clock/sec * 0.25 sec) SD Clock cycles
222 * = (mmc->tran_speed * 1/4) SD Clock cycles
224 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
225 * Taking log2 both the sides
226 * => timeout + 13 >= log2(mmc->tran_speed/4)
227 * Rounding up to next power of 2
228 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
229 * => timeout + 13 = fls(mmc->tran_speed/4)
231 timeout = fls(mmc->tran_speed / 4);
236 else if (timeout < 0)
239 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
240 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
243 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
248 static inline void check_and_invalidate_dcache_range(struct mmc_cmd *cmd,
249 struct mmc_data *data)
251 unsigned long start = (unsigned long)data->dest;
252 size_t start_ofs = start & (ARCH_DMA_MINALIGN - 1);
253 unsigned long size = data->blocks * data->blocksize;
254 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
257 invalidate_dcache_range(start, end);
261 * Sends a command out on the bus. Takes the mmc pointer,
262 * a command pointer, and an optional data pointer.
265 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
269 struct fsl_esdhc_cfg *cfg = mmc->priv;
270 volatile struct fsl_esdhc *regs = cfg->esdhc_base;
273 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
274 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
278 esdhc_write32(®s->irqstat, -1);
282 start = get_timer_masked();
283 /* Wait for the bus to be idle */
284 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
285 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) {
286 if (get_timer(start) > CONFIG_SYS_HZ) {
287 printf("%s: Timeout waiting for bus idle\n", __func__);
292 start = get_timer_masked();
293 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) {
294 if (get_timer(start) > CONFIG_SYS_HZ)
298 /* Wait at least 8 SD clock cycles before the next command */
300 * Note: This is way more than 8 cycles, but 1ms seems to
301 * resolve timing issues with some cards
305 /* Set up for a data transfer if we have one */
309 err = esdhc_setup_data(mmc, data);
314 /* Figure out the transfer arguments */
315 xfertyp = esdhc_xfertyp(cmd, data);
318 esdhc_write32(®s->irqsigen, 0);
320 /* Send the command */
321 esdhc_write32(®s->cmdarg, cmd->cmdarg);
322 #if defined(CONFIG_FSL_USDHC)
323 esdhc_write32(®s->mixctrl,
324 (esdhc_read32(®s->mixctrl) & ~0x7f) | (xfertyp & 0x7F));
325 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
327 esdhc_write32(®s->xfertyp, xfertyp);
331 esdhc_write32(®s->irqsigen, 0);
333 start = get_timer_masked();
334 /* Wait for the command to complete */
335 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) {
336 if (get_timer(start) > CONFIG_SYS_HZ) {
337 printf("%s: Timeout waiting for cmd completion\n", __func__);
342 if (data && (data->flags & MMC_DATA_READ))
343 check_and_invalidate_dcache_range(cmd, data);
345 irqstat = esdhc_read32(®s->irqstat);
347 /* Reset CMD and DATA portions on error */
348 if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
349 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
351 start = get_timer_masked();
352 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) {
353 if (get_timer(start) > CONFIG_SYS_HZ)
358 esdhc_write32(®s->sysctl,
359 esdhc_read32(®s->sysctl) |
361 start = get_timer_masked();
362 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) {
363 if (get_timer(start) > CONFIG_SYS_HZ)
369 if (irqstat & CMD_ERR)
372 if (irqstat & IRQSTAT_CTOE)
375 /* Workaround for ESDHC errata ENGcm03648 */
376 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
379 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
380 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
387 printf("Timeout waiting for DAT0 to go high!\n");
392 /* Copy the response to the response buffer */
393 if (cmd->resp_type & MMC_RSP_136) {
394 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
396 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
397 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
398 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
399 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
400 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
401 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
402 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
403 cmd->response[3] = (cmdrsp0 << 8);
405 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
407 /* Wait until all of the blocks are transferred */
409 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
410 esdhc_pio_read_write(mmc, data);
412 unsigned long start = get_timer_masked();
413 unsigned long data_timeout = data->blocks *
414 (data->blocksize + 100) * 8 / mmc->bus_width /
415 (mmc->tran_speed / CONFIG_SYS_HZ) + CONFIG_SYS_HZ;
418 irqstat = esdhc_read32(®s->irqstat);
420 if (irqstat & IRQSTAT_DTOE) {
421 printf("MMC/SD data %s timeout\n",
422 data->flags & MMC_DATA_READ ?
427 if (irqstat & DATA_ERR) {
428 printf("MMC/SD data error\n");
432 if (get_timer(start) > data_timeout) {
433 printf("MMC/SD timeout waiting for %s xfer completion\n",
434 data->flags & MMC_DATA_READ ?
438 } while (!(irqstat & IRQSTAT_TC) &&
439 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
441 check_and_invalidate_dcache_range(cmd, data);
445 esdhc_write32(®s->irqstat, irqstat);
450 static void set_sysctl(struct mmc *mmc, uint clock)
453 struct fsl_esdhc_cfg *cfg = mmc->priv;
454 volatile struct fsl_esdhc *regs = cfg->esdhc_base;
455 int sdhc_clk = cfg->sdhc_clk;
458 if (clock < mmc->f_min)
461 if (sdhc_clk / 16 > clock) {
462 for (pre_div = 2; pre_div < 256; pre_div *= 2)
463 if ((sdhc_clk / pre_div) <= (clock * 16))
468 for (div = 1; div <= 16; div++)
469 if ((sdhc_clk / (div * pre_div)) <= clock)
475 clk = (pre_div << 8) | (div << 4);
477 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
479 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
483 clk = SYSCTL_PEREN | SYSCTL_CKEN;
485 esdhc_setbits32(®s->sysctl, clk);
488 static void esdhc_set_ios(struct mmc *mmc)
490 struct fsl_esdhc_cfg *cfg = mmc->priv;
491 struct fsl_esdhc *regs = cfg->esdhc_base;
493 /* Set the clock speed */
494 set_sysctl(mmc, mmc->clock);
496 /* Set the bus width */
497 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
499 if (mmc->bus_width == 4)
500 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
501 else if (mmc->bus_width == 8)
502 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
506 static int esdhc_init(struct mmc *mmc)
508 struct fsl_esdhc_cfg *cfg = mmc->priv;
509 struct fsl_esdhc *regs = cfg->esdhc_base;
512 /* Reset the entire host controller */
513 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
515 /* Wait until the controller is available */
516 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
520 /* Enable cache snooping */
521 esdhc_write32(®s->scr, 0x00000040);
524 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
526 /* Set the initial clock speed */
527 mmc_set_clock(mmc, 400000);
529 /* Disable the BRR and BWR bits in IRQSTAT */
530 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
532 /* Put the PROCTL reg back to the default */
533 esdhc_write32(®s->proctl, PROCTL_INIT);
535 /* Set timout to the maximum value */
536 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
541 static int esdhc_getcd(struct mmc *mmc)
543 struct fsl_esdhc_cfg *cfg = mmc->priv;
544 struct fsl_esdhc *regs = cfg->esdhc_base;
547 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
553 static void esdhc_reset(struct fsl_esdhc *regs)
555 unsigned long timeout = 100; /* wait max 100 ms */
557 /* reset the controller */
558 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
560 /* hardware clears the bit when it is done */
561 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
564 printf("MMC/SD: Reset never completed.\n");
567 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
569 struct fsl_esdhc *regs;
571 u32 caps, voltage_caps;
576 mmc = kzalloc(sizeof(struct mmc), GFP_KERNEL);
580 sprintf(mmc->name, "FSL_SDHC");
581 regs = cfg->esdhc_base;
583 /* First reset the eSDHC controller */
586 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
587 | SYSCTL_IPGEN | SYSCTL_CKEN);
590 mmc->send_cmd = esdhc_send_cmd;
591 mmc->set_ios = esdhc_set_ios;
592 mmc->init = esdhc_init;
593 mmc->getcd = esdhc_getcd;
597 caps = regs->hostcapblt;
599 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
600 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
601 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
603 if (caps & ESDHC_HOSTCAPBLT_VS18)
604 voltage_caps |= MMC_VDD_165_195;
605 if (caps & ESDHC_HOSTCAPBLT_VS30)
606 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
607 if (caps & ESDHC_HOSTCAPBLT_VS33)
608 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
610 #ifdef CONFIG_SYS_SD_VOLTAGE
611 mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
613 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
615 if ((mmc->voltages & voltage_caps) == 0) {
616 printf("voltage not supported by controller\n");
620 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
622 if (cfg->max_bus_width > 0) {
623 if (cfg->max_bus_width < 8)
624 mmc->host_caps &= ~MMC_MODE_8BIT;
625 if (cfg->max_bus_width < 4)
626 mmc->host_caps &= ~MMC_MODE_4BIT;
629 if (caps & ESDHC_HOSTCAPBLT_HSS)
630 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
633 mmc->f_max = MIN(cfg->sdhc_clk, 52000000);
641 int fsl_esdhc_mmc_init(bd_t *bis)
643 struct fsl_esdhc_cfg *cfg;
645 cfg = kzalloc(sizeof(struct fsl_esdhc_cfg), GFP_KERNEL);
648 cfg->esdhc_base = (void __iomem *)CONFIG_SYS_FSL_ESDHC_ADDR;
649 cfg->sdhc_clk = gd->arch.sdhc_clk;
650 return fsl_esdhc_initialize(bis, cfg);
653 #ifdef CONFIG_OF_LIBFDT
654 void fdt_fixup_esdhc(void *blob, bd_t *bd)
656 const char *compat = "fsl,esdhc";
658 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
659 if (!hwconfig("esdhc")) {
660 do_fixup_by_compat(blob, compat, "status", "disabled",
666 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
667 gd->arch.sdhc_clk, 1);
669 do_fixup_by_compat(blob, compat, "status", "okay",