drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <mmc.h>
  29 #include <part.h>
  30 #include <i2c.h>
  31 #include <twl4030.h>
  32 #include <twl6030.h>
  33 #include <palmas.h>
  34 #include <asm/gpio.h>
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  40 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  41         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  42 #define OMAP_HSMMC_USE_GPIO
  43 #else
  44 #undef OMAP_HSMMC_USE_GPIO
  45 #endif
  46
  47 /* common definitions for all OMAPs */
  48 #define SYSCTL_SRC      (1 << 25)
  49 #define SYSCTL_SRD      (1 << 26)
  50
  51 struct omap_hsmmc_data {
  52         struct hsmmc *base_addr;
  53         struct mmc_config cfg;
  54 #ifdef OMAP_HSMMC_USE_GPIO
  55         int cd_gpio;
  56         int wp_gpio;
  57 #endif
  58 };
  59
  60 /* If we fail after 1 second wait, something is really bad */
  61 #define MAX_RETRY_MS    1000
  62
  63 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  64 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  65                         unsigned int siz);
  66
  67 #ifdef OMAP_HSMMC_USE_GPIO
  68 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  69 {
  70         int ret;
  71
  72 #ifndef CONFIG_DM_GPIO
  73         if (!gpio_is_valid(gpio))
  74                 return -1;
  75 #endif
  76         ret = gpio_request(gpio, label);
  77         if (ret)
  78                 return ret;
  79
  80         ret = gpio_direction_input(gpio);
  81         if (ret)
  82                 return ret;
  83
  84         return gpio;
  85 }
  86 #endif
  87
  88 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  89 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  90 {
  91         u32 value = 0;
  92
  93         value = readl((*ctrl)->control_pbiaslite);
  94         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
  95         writel(value, (*ctrl)->control_pbiaslite);
  96         /* set VMMC to 3V */
  97         twl6030_power_mmc_init();
  98         value = readl((*ctrl)->control_pbiaslite);
  99         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 100         writel(value, (*ctrl)->control_pbiaslite);
 101 }
 102 #endif
 103
 104 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 105 static void omap5_pbias_config(struct mmc *mmc)
 106 {
 107         u32 value = 0;
 108
 109         value = readl((*ctrl)->control_pbias);
 110         value &= ~SDCARD_PWRDNZ;
 111         writel(value, (*ctrl)->control_pbias);
 112         udelay(10); /* wait 10 us */
 113         value &= ~SDCARD_BIAS_PWRDNZ;
 114         writel(value, (*ctrl)->control_pbias);
 115
 116         palmas_mmc1_poweron_ldo();
 117
 118         value = readl((*ctrl)->control_pbias);
 119         value |= SDCARD_BIAS_PWRDNZ;
 120         writel(value, (*ctrl)->control_pbias);
 121         udelay(150); /* wait 150 us */
 122         value |= SDCARD_PWRDNZ;
 123         writel(value, (*ctrl)->control_pbias);
 124         udelay(150); /* wait 150 us */
 125 }
 126 #endif
 127
 128 static void mmc_board_init(struct mmc *mmc)
 129 {
 130 #if defined(CONFIG_OMAP34XX)
 131         t2_t *t2_base = (t2_t *)T2_BASE;
 132         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 133         u32 pbias_lite;
 134
 135         pbias_lite = readl(&t2_base->pbias_lite);
 136         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 137 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 138         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 139         pbias_lite &= ~PBIASLITEVMODE0;
 140 #endif
 141         writel(pbias_lite, &t2_base->pbias_lite);
 142
 143         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 144                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 145                 &t2_base->pbias_lite);
 146
 147         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 148                 &t2_base->devconf0);
 149
 150         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 151                 &t2_base->devconf1);
 152
 153         /* Change from default of 52MHz to 26MHz if necessary */
 154         if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
 155                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 156                         &t2_base->ctl_prog_io1);
 157
 158         writel(readl(&prcm_base->fclken1_core) |
 159                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 160                 &prcm_base->fclken1_core);
 161
 162         writel(readl(&prcm_base->iclken1_core) |
 163                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 164                 &prcm_base->iclken1_core);
 165 #endif
 166
 167 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 168         /* PBIAS config needed for MMC1 only */
 169         if (mmc->block_dev.dev == 0)
 170                 omap4_vmmc_pbias_config(mmc);
 171 #endif
 172 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 173         if (mmc->block_dev.dev == 0)
 174                 omap5_pbias_config(mmc);
 175 #endif
 176 }
 177
 178 void mmc_init_stream(struct hsmmc *mmc_base)
 179 {
 180         ulong start;
 181
 182         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 183
 184         writel(MMC_CMD0, &mmc_base->cmd);
 185         start = get_timer(0);
 186         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 187                 if (get_timer(start) > MAX_RETRY_MS)
 188                         break;
 189         }
 190         if (!(readl(&mmc_base->stat) & CC_MASK)) {
 191                 printf("%s: timeout waiting for cc!\n", __func__);
 192                 return;
 193         }
 194
 195         writel(CC_MASK, &mmc_base->stat);
 196         writel(MMC_CMD0, &mmc_base->cmd);
 197
 198         start = get_timer(0);
 199         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 200                 if (get_timer(start) > MAX_RETRY_MS)
 201                         break;
 202         }
 203         if (!(readl(&mmc_base->stat) & CC_MASK)) {
 204                 printf("%s: timeout waiting for cc2!\n", __func__);
 205                 return;
 206         }
 207         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 208 }
 209
 210
 211 static int omap_hsmmc_init_setup(struct mmc *mmc)
 212 {
 213         struct omap_hsmmc_data *priv_data = mmc->priv;
 214         struct hsmmc *mmc_base = priv_data->base_addr;
 215         unsigned int reg_val;
 216         unsigned int dsor;
 217         ulong start;
 218
 219         mmc_board_init(mmc);
 220
 221         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 222                 &mmc_base->sysconfig);
 223         start = get_timer(0);
 224         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 225                 if (get_timer(start) > MAX_RETRY_MS)
 226                         break;
 227         }
 228         if ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 229                 printf("%s: timeout %08x waiting for softreset done!\n", __func__,
 230                         readl(&mmc_base->sysstatus));
 231                 return TIMEOUT;
 232         }
 233         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 234         start = get_timer(0);
 235         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0) {
 236                 if (get_timer(start) > MAX_RETRY_MS)
 237                         break;
 238         }
 239         if ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0) {
 240                 printf("%s: timeout waiting for softresetall!\n", __func__);
 241                 return TIMEOUT;
 242         }
 243         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 244         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 245                 &mmc_base->capa);
 246
 247         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 248
 249         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 250                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 251                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 252
 253         dsor = 240;
 254         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 255                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 256         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 257                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 258         start = get_timer(0);
 259         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 260                 if (get_timer(start) > MAX_RETRY_MS)
 261                         break;
 262         }
 263         if ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 264                 printf("%s: timeout waiting for ics!\n", __func__);
 265                 return TIMEOUT;
 266         }
 267         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 268
 269         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 270
 271         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 272                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 273                 &mmc_base->ie);
 274
 275         mmc_init_stream(mmc_base);
 276
 277         return 0;
 278 }
 279
 280 /*
 281  * MMC controller internal finite state machine reset
 282  *
 283  * Used to reset command or data internal state machines, using respectively
 284  * SRC or SRD bit of SYSCTL register
 285  */
 286 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 287 {
 288         ulong start;
 289
 290         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 291
 292         /*
 293          * CMD(DAT) lines reset procedures are slightly different
 294          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 295          * According to OMAP3 TRM:
 296          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 297          * returns to 0x0.
 298          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 299          * procedure steps must be as follows:
 300          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 301          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 302          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 303          * 3. Wait until the SRC (SRD) bit returns to 0x0
 304          *    (reset procedure is completed).
 305          */
 306 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 307         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 308         if (!(readl(&mmc_base->sysctl) & bit)) {
 309                 start = get_timer(0);
 310                 while (!(readl(&mmc_base->sysctl) & bit)) {
 311                         if (get_timer(0) - start > MAX_RETRY_MS)
 312                                 return;
 313                 }
 314         }
 315 #endif
 316         start = get_timer(0);
 317         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 318                 if (get_timer(0) - start > MAX_RETRY_MS)
 319                         break;
 320         }
 321         if ((readl(&mmc_base->sysctl) & bit) != 0) {
 322                 printf("%s: timedout waiting for sysctl %x to clear\n", __func__, bit);
 323                 return;
 324         }
 325 }
 326
 327 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 328                         struct mmc_data *data)
 329 {
 330         struct omap_hsmmc_data *priv_data = mmc->priv;
 331         struct hsmmc *mmc_base = priv_data->base_addr;
 332         unsigned int flags, mmc_stat;
 333         ulong start;
 334
 335         start = get_timer(0);
 336         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 337                 if (get_timer(start) > MAX_RETRY_MS)
 338                         break;
 339         }
 340         if ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 341                 printf("%s: timeout waiting on cmd inhibit to clear\n", __func__);
 342                 return TIMEOUT;
 343         }
 344         writel(0xFFFFFFFF, &mmc_base->stat);
 345         start = get_timer(0);
 346         while (readl(&mmc_base->stat)) {
 347                 if (get_timer(start) > MAX_RETRY_MS)
 348                         break;
 349         }
 350         if (readl(&mmc_base->stat)) {
 351                 printf("%s: timeout waiting for stat!\n", __func__);
 352                 return TIMEOUT;
 353         }
 354         /*
 355          * CMDREG
 356          * CMDIDX[13:8] : Command index
 357          * DATAPRNT[5]  : Data Present Select
 358          * ENCMDIDX[4]  : Command Index Check Enable
 359          * ENCMDCRC[3]  : Command CRC Check Enable
 360          * RSPTYP[1:0]
 361          *      00 = No Response
 362          *      01 = Length 136
 363          *      10 = Length 48
 364          *      11 = Length 48 Check busy after response
 365          */
 366         /* Delay added before checking the status of frq change
 367          * retry not supported by mmc.c(core file)
 368          */
 369         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 370                 udelay(50000); /* wait 50 ms */
 371
 372         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 373                 flags = 0;
 374         else if (cmd->resp_type & MMC_RSP_136)
 375                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 376         else if (cmd->resp_type & MMC_RSP_BUSY)
 377                 flags = RSP_TYPE_LGHT48B;
 378         else
 379                 flags = RSP_TYPE_LGHT48;
 380
 381         /* enable default flags */
 382         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 383                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 384
 385         if (cmd->resp_type & MMC_RSP_CRC)
 386                 flags |= CCCE_CHECK;
 387         if (cmd->resp_type & MMC_RSP_OPCODE)
 388                 flags |= CICE_CHECK;
 389
 390         if (data) {
 391                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 392                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 393                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 394                         data->blocksize = 512;
 395                         writel(data->blocksize | (data->blocks << 16),
 396                                                         &mmc_base->blk);
 397                 } else
 398                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 399
 400                 if (data->flags & MMC_DATA_READ)
 401                         flags |= (DP_DATA | DDIR_READ);
 402                 else
 403                         flags |= (DP_DATA | DDIR_WRITE);
 404         }
 405
 406         writel(cmd->cmdarg, &mmc_base->arg);
 407         udelay(20);             /* To fix "No status update" error on eMMC */
 408         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 409
 410         start = get_timer(0);
 411         while (!(mmc_stat = readl(&mmc_base->stat))) {
 412                 if (get_timer(start) > MAX_RETRY_MS)
 413                         break;
 414         }
 415         if (!mmc_stat) {
 416                 printf("%s : timeout: No status update\n", __func__);
 417                 return TIMEOUT;
 418         }
 419
 420         if ((mmc_stat & IE_CTO) != 0) {
 421                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 422                 return TIMEOUT;
 423         } else if ((mmc_stat & ERRI_MASK) != 0)
 424                 return -1;
 425
 426         if (mmc_stat & CC_MASK) {
 427                 writel(CC_MASK, &mmc_base->stat);
 428                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 429                         if (cmd->resp_type & MMC_RSP_136) {
 430                                 /* response type 2 */
 431                                 cmd->response[3] = readl(&mmc_base->rsp10);
 432                                 cmd->response[2] = readl(&mmc_base->rsp32);
 433                                 cmd->response[1] = readl(&mmc_base->rsp54);
 434                                 cmd->response[0] = readl(&mmc_base->rsp76);
 435                         } else
 436                                 /* response types 1, 1b, 3, 4, 5, 6 */
 437                                 cmd->response[0] = readl(&mmc_base->rsp10);
 438                 }
 439         }
 440
 441         if (data && (data->flags & MMC_DATA_READ)) {
 442                 mmc_read_data(mmc_base, data->dest,
 443                                 data->blocksize * data->blocks);
 444         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 445                 mmc_write_data(mmc_base, data->src,
 446                                 data->blocksize * data->blocks);
 447         }
 448         return 0;
 449 }
 450
 451 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 452 {
 453         unsigned int *output_buf = (unsigned int *)buf;
 454         unsigned int mmc_stat;
 455         unsigned int count;
 456
 457         /*
 458          * Start Polled Read
 459          */
 460         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 461         count /= 4;
 462
 463         while (size) {
 464                 ulong start = get_timer(0);
 465
 466                 while (!(mmc_stat = readl(&mmc_base->stat))) {
 467                         if (get_timer(start) > MAX_RETRY_MS)
 468                                 break;
 469                 }
 470                 if (!mmc_stat) {
 471                         printf("%s: timeout waiting for status!\n", __func__);
 472                         return TIMEOUT;
 473                 }
 474
 475                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 476                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 477
 478                 if ((mmc_stat & ERRI_MASK) != 0)
 479                         return 1;
 480
 481                 if (mmc_stat & BRR_MASK) {
 482                         unsigned int k;
 483
 484                         writel(readl(&mmc_base->stat) | BRR_MASK,
 485                                 &mmc_base->stat);
 486                         for (k = 0; k < count; k++) {
 487                                 *output_buf = readl(&mmc_base->data);
 488                                 output_buf++;
 489                         }
 490                         size -= (count*4);
 491                 }
 492
 493                 if (mmc_stat & BWR_MASK)
 494                         writel(readl(&mmc_base->stat) | BWR_MASK,
 495                                 &mmc_base->stat);
 496
 497                 if (mmc_stat & TC_MASK) {
 498                         writel(readl(&mmc_base->stat) | TC_MASK,
 499                                 &mmc_base->stat);
 500                         break;
 501                 }
 502         }
 503         return 0;
 504 }
 505
 506 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 507                                 unsigned int size)
 508 {
 509         unsigned int *input_buf = (unsigned int *)buf;
 510         unsigned int mmc_stat;
 511         unsigned int count;
 512
 513         /*
 514          * Start Polled Write
 515          */
 516         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 517         count /= 4;
 518
 519         while (size) {
 520                 ulong start = get_timer(0);
 521
 522                 while (!(mmc_stat = readl(&mmc_base->stat))) {
 523                         if (get_timer(start) > MAX_RETRY_MS)
 524                                 break;
 525                 }
 526                 if (!mmc_stat) {
 527                         printf("%s: timeout waiting for status!\n", __func__);
 528                         return TIMEOUT;
 529                 }
 530
 531                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 532                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 533
 534                 if ((mmc_stat & ERRI_MASK) != 0)
 535                         return 1;
 536
 537                 if (mmc_stat & BWR_MASK) {
 538                         unsigned int k;
 539
 540                         writel(readl(&mmc_base->stat) | BWR_MASK,
 541                                         &mmc_base->stat);
 542                         for (k = 0; k < count; k++) {
 543                                 writel(*input_buf, &mmc_base->data);
 544                                 input_buf++;
 545                         }
 546                         size -= (count*4);
 547                 }
 548
 549                 if (mmc_stat & BRR_MASK)
 550                         writel(readl(&mmc_base->stat) | BRR_MASK,
 551                                 &mmc_base->stat);
 552
 553                 if (mmc_stat & TC_MASK) {
 554                         writel(readl(&mmc_base->stat) | TC_MASK,
 555                                 &mmc_base->stat);
 556                         break;
 557                 }
 558         }
 559         return 0;
 560 }
 561
 562 static void omap_hsmmc_set_ios(struct mmc *mmc)
 563 {
 564         struct omap_hsmmc_data *priv_data = mmc->priv;
 565         struct hsmmc *mmc_base = priv_data->base_addr;
 566         unsigned int dsor = 0;
 567         ulong start;
 568
 569         /* configue bus width */
 570         switch (mmc->bus_width) {
 571         case 8:
 572                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 573                         &mmc_base->con);
 574                 break;
 575
 576         case 4:
 577                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 578                         &mmc_base->con);
 579                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 580                         &mmc_base->hctl);
 581                 break;
 582
 583         case 1:
 584         default:
 585                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 586                         &mmc_base->con);
 587                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 588                         &mmc_base->hctl);
 589                 break;
 590         }
 591
 592         /* configure clock with 96Mhz system clock.
 593          */
 594         if (mmc->clock != 0) {
 595                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 596                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 597                         dsor++;
 598         }
 599
 600         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 601                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 602
 603         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 604                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 605
 606         start = get_timer(0);
 607         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 608                 if (get_timer(start) > MAX_RETRY_MS)
 609                         break;
 610         }
 611         if ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 612                 printf("%s: timeout waiting for ics!\n", __func__);
 613                 return;
 614         }
 615         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 616 }
 617
 618 #ifdef OMAP_HSMMC_USE_GPIO
 619 static int omap_hsmmc_getcd(struct mmc *mmc)
 620 {
 621         struct omap_hsmmc_data *priv_data = mmc->priv;
 622         int cd_gpio;
 623
 624         /* if no CD return as 1 */
 625         cd_gpio = priv_data->cd_gpio;
 626         if (cd_gpio < 0)
 627                 return 1;
 628
 629         /* NOTE: assumes card detect signal is active-low */
 630         return !gpio_get_value(cd_gpio);
 631 }
 632
 633 static int omap_hsmmc_getwp(struct mmc *mmc)
 634 {
 635         struct omap_hsmmc_data *priv_data = mmc->priv;
 636         int wp_gpio;
 637
 638         /* if no WP return as 0 */
 639         wp_gpio = priv_data->wp_gpio;
 640         if (wp_gpio < 0)
 641                 return 0;
 642
 643         /* NOTE: assumes write protect signal is active-high */
 644         return gpio_get_value(wp_gpio);
 645 }
 646 #endif
 647
 648 static const struct mmc_ops omap_hsmmc_ops = {
 649         .send_cmd       = omap_hsmmc_send_cmd,
 650         .set_ios        = omap_hsmmc_set_ios,
 651         .init           = omap_hsmmc_init_setup,
 652 #ifdef OMAP_HSMMC_USE_GPIO
 653         .getcd          = omap_hsmmc_getcd,
 654         .getwp          = omap_hsmmc_getwp,
 655 #endif
 656 };
 657
 658 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 659                 int wp_gpio)
 660 {
 661         int ret;
 662         struct mmc *mmc;
 663         struct omap_hsmmc_data *priv_data;
 664         struct mmc_config *cfg;
 665         uint host_caps_val;
 666
 667         priv_data = calloc(sizeof(*priv_data), 1);
 668         if (priv_data == NULL)
 669                 return -ENOMEM;
 670
 671         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 672
 673         switch (dev_index) {
 674         case 0:
 675                 base_addr = OMAP_HSMMC1_BASE;
 676                 break;
 677 #ifdef OMAP_HSMMC2_BASE
 678         case 1:
 679                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 680 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 681      defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
 682                 defined(CONFIG_HSMMC2_8BIT)
 683                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
 684                 host_caps_val |= MMC_MODE_8BIT;
 685 #endif
 686                 break;
 687 #endif
 688 #ifdef OMAP_HSMMC3_BASE
 689         case 2:
 690                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
 691 #if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
 692                 /* Enable 8-bit interface for eMMC on DRA7XX */
 693                 host_caps_val |= MMC_MODE_8BIT;
 694 #endif
 695                 break;
 696 #endif
 697         default:
 698                 printf("Invalid MMC device index: %d\n", dev_index);
 699                 ret = 1;
 700                 goto out;
 701         }
 702 #ifdef OMAP_HSMMC_USE_GPIO
 703         /* on error gpio values are set to -1, which is what we want */
 704         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 705         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 706 #endif
 707
 708         cfg = &priv_data->cfg;
 709
 710         cfg->name = "OMAP SD/MMC";
 711         cfg->ops = &omap_hsmmc_ops;
 712
 713         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 714         cfg->host_caps = host_caps_val & ~host_caps_mask;
 715
 716         cfg->f_min = 400000;
 717
 718         if (f_max != 0)
 719                 cfg->f_max = f_max;
 720         else {
 721                 if (cfg->host_caps & MMC_MODE_HS) {
 722                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
 723                                 cfg->f_max = 52000000;
 724                         else
 725                                 cfg->f_max = 26000000;
 726                 } else
 727                         cfg->f_max = 20000000;
 728         }
 729
 730         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 731
 732 #if defined(CONFIG_OMAP34XX)
 733         /*
 734          * Silicon revs 2.1 and older do not support multiblock transfers.
 735          */
 736         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 737                 cfg->b_max = 1;
 738 #endif
 739         mmc = mmc_create(cfg, priv_data);
 740         if (mmc == NULL) {
 741                 ret = -ENOMEM;
 742                 goto out;
 743         }
 744
 745         return 0;
 746
 747 out:
 748         free(priv_data);
 749         return ret;
 750 }