upgrade to upstream version 2013.07
[karo-tx-uboot.git] / drivers / mmc / omap_hsmmc.c
1 /*
2  * (C) Copyright 2008
3  * Texas Instruments, <www.ti.com>
4  * Sukumar Ghorai <s-ghorai@ti.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation's version 2 of
12  * the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 #include <config.h>
26 #include <common.h>
27 #include <mmc.h>
28 #include <part.h>
29 #include <i2c.h>
30 #include <twl4030.h>
31 #include <twl6030.h>
32 #include <palmas.h>
33 #include <asm/gpio.h>
34 #include <asm/io.h>
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
37
38 /* common definitions for all OMAPs */
39 #define SYSCTL_SRC      (1 << 25)
40 #define SYSCTL_SRD      (1 << 26)
41
42 struct omap_hsmmc_data {
43         struct hsmmc *base_addr;
44         int cd_gpio;
45         int wp_gpio;
46 };
47
48 /* If we fail after 1 second wait, something is really bad */
49 #define MAX_RETRY_MS    1000
50
51 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
52 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
53                         unsigned int siz);
54 static struct mmc hsmmc_dev[3];
55 static struct omap_hsmmc_data hsmmc_dev_data[3];
56
57 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
58         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
59 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
60 {
61         if (!gpio_is_valid(gpio))
62                 return -1;
63
64         if (gpio_request(gpio, label) < 0)
65                 return -1;
66
67         if (gpio_direction_input(gpio) < 0)
68                 return -1;
69
70         return gpio;
71 }
72
73 static int omap_mmc_getcd(struct mmc *mmc)
74 {
75         int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
76         return gpio_get_value(cd_gpio);
77 }
78
79 static int omap_mmc_getwp(struct mmc *mmc)
80 {
81         int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio;
82         return gpio_get_value(wp_gpio);
83 }
84 #else
85 static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
86 {
87         return -1;
88 }
89
90 #define omap_mmc_getcd NULL
91 #define omap_mmc_getwp NULL
92 #endif
93
94 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
95 static void omap4_vmmc_pbias_config(struct mmc *mmc)
96 {
97         u32 value = 0;
98
99         value = readl((*ctrl)->control_pbiaslite);
100         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
101         writel(value, (*ctrl)->control_pbiaslite);
102         /* set VMMC to 3V */
103         twl6030_power_mmc_init();
104         value = readl((*ctrl)->control_pbiaslite);
105         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
106         writel(value, (*ctrl)->control_pbiaslite);
107 }
108 #endif
109
110 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
111 static void omap5_pbias_config(struct mmc *mmc)
112 {
113         u32 value = 0;
114
115         value = readl((*ctrl)->control_pbias);
116         value &= ~SDCARD_PWRDNZ;
117         writel(value, (*ctrl)->control_pbias);
118         udelay(10); /* wait 10 us */
119         value &= ~SDCARD_BIAS_PWRDNZ;
120         writel(value, (*ctrl)->control_pbias);
121
122         palmas_mmc1_poweron_ldo();
123
124         value = readl((*ctrl)->control_pbias);
125         value |= SDCARD_BIAS_PWRDNZ;
126         writel(value, (*ctrl)->control_pbias);
127         udelay(150); /* wait 150 us */
128         value |= SDCARD_PWRDNZ;
129         writel(value, (*ctrl)->control_pbias);
130         udelay(150); /* wait 150 us */
131 }
132 #endif
133
134 unsigned char mmc_board_init(struct mmc *mmc)
135 {
136 #if defined(CONFIG_OMAP34XX)
137         t2_t *t2_base = (t2_t *)T2_BASE;
138         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
139         u32 pbias_lite;
140
141         pbias_lite = readl(&t2_base->pbias_lite);
142         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
143         writel(pbias_lite, &t2_base->pbias_lite);
144 #endif
145 #if defined(CONFIG_TWL4030_POWER)
146         twl4030_power_mmc_init();
147         mdelay(100);    /* ramp-up delay from Linux code */
148 #endif
149 #if defined(CONFIG_OMAP34XX)
150         writel(pbias_lite | PBIASLITEPWRDNZ1 |
151                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
152                 &t2_base->pbias_lite);
153
154         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
155                 &t2_base->devconf0);
156
157         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
158                 &t2_base->devconf1);
159
160         /* Change from default of 52MHz to 26MHz if necessary */
161         if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
162                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
163                         &t2_base->ctl_prog_io1);
164
165         writel(readl(&prcm_base->fclken1_core) |
166                 EN_MMC1 | EN_MMC2 | EN_MMC3,
167                 &prcm_base->fclken1_core);
168
169         writel(readl(&prcm_base->iclken1_core) |
170                 EN_MMC1 | EN_MMC2 | EN_MMC3,
171                 &prcm_base->iclken1_core);
172 #endif
173
174 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
175         /* PBIAS config needed for MMC1 only */
176         if (mmc->block_dev.dev == 0)
177                 omap4_vmmc_pbias_config(mmc);
178 #endif
179 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
180         if (mmc->block_dev.dev == 0)
181                 omap5_pbias_config(mmc);
182 #endif
183
184         return 0;
185 }
186
187 void mmc_init_stream(struct hsmmc *mmc_base)
188 {
189         ulong start;
190
191         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
192
193         writel(MMC_CMD0, &mmc_base->cmd);
194         start = get_timer(0);
195         while (!(readl(&mmc_base->stat) & CC_MASK)) {
196                 if (get_timer(start) > MAX_RETRY_MS) {
197                         printf("%s: timeout waiting for cc!\n", __func__);
198                         return;
199                 }
200         }
201         writel(CC_MASK, &mmc_base->stat)
202                 ;
203         writel(MMC_CMD0, &mmc_base->cmd)
204                 ;
205         start = get_timer(0);
206         while (!(readl(&mmc_base->stat) & CC_MASK)) {
207                 if (get_timer(start) > MAX_RETRY_MS) {
208                         printf("%s: timeout waiting for cc2!\n", __func__);
209                         return;
210                 }
211         }
212         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
213 }
214
215
216 static int mmc_init_setup(struct mmc *mmc)
217 {
218         struct omap_hsmmc_data *priv_data = mmc->priv;
219         struct hsmmc *mmc_base = priv_data->base_addr;
220         unsigned int reg_val;
221         unsigned int dsor;
222         ulong start;
223
224         mmc_board_init(mmc);
225
226         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
227                 &mmc_base->sysconfig);
228         start = get_timer(0);
229         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
230                 if (get_timer(start) > MAX_RETRY_MS) {
231                         printf("%s: timeout waiting for cc2!\n", __func__);
232                         return TIMEOUT;
233                 }
234         }
235         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
236         start = get_timer(0);
237         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
238                 if (get_timer(start) > MAX_RETRY_MS) {
239                         printf("%s: timeout waiting for softresetall!\n",
240                                 __func__);
241                         return TIMEOUT;
242                 }
243         }
244         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
245         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
246                 &mmc_base->capa);
247
248         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
249
250         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
251                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
252                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
253
254         dsor = 240;
255         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
256                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
257         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
258                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
259         start = get_timer(0);
260         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
261                 if (get_timer(start) > MAX_RETRY_MS) {
262                         printf("%s: timeout waiting for ics!\n", __func__);
263                         return TIMEOUT;
264                 }
265         }
266         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
267
268         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
269
270         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
271                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
272                 &mmc_base->ie);
273
274         mmc_init_stream(mmc_base);
275
276         return 0;
277 }
278
279 /*
280  * MMC controller internal finite state machine reset
281  *
282  * Used to reset command or data internal state machines, using respectively
283  * SRC or SRD bit of SYSCTL register
284  */
285 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
286 {
287         ulong start;
288
289         mmc_reg_out(&mmc_base->sysctl, bit, bit);
290
291         start = get_timer(0);
292         while ((readl(&mmc_base->sysctl) & bit) != 0) {
293                 if (get_timer(0) - start > MAX_RETRY_MS) {
294                         printf("%s: timedout waiting for sysctl %x to clear\n",
295                                 __func__, bit);
296                         return;
297                 }
298         }
299 }
300
301 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
302                         struct mmc_data *data)
303 {
304         struct omap_hsmmc_data *priv_data = mmc->priv;
305         struct hsmmc *mmc_base = priv_data->base_addr;
306         unsigned int flags, mmc_stat;
307         ulong start;
308
309         start = get_timer(0);
310         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
311                 if (get_timer(start) > MAX_RETRY_MS) {
312                         printf("%s: timeout waiting on cmd inhibit to clear\n",
313                                         __func__);
314                         return TIMEOUT;
315                 }
316         }
317         writel(0xFFFFFFFF, &mmc_base->stat);
318         start = get_timer(0);
319         while (readl(&mmc_base->stat)) {
320                 if (get_timer(start) > MAX_RETRY_MS) {
321                         printf("%s: timeout waiting for stat!\n", __func__);
322                         return TIMEOUT;
323                 }
324         }
325         /*
326          * CMDREG
327          * CMDIDX[13:8] : Command index
328          * DATAPRNT[5]  : Data Present Select
329          * ENCMDIDX[4]  : Command Index Check Enable
330          * ENCMDCRC[3]  : Command CRC Check Enable
331          * RSPTYP[1:0]
332          *      00 = No Response
333          *      01 = Length 136
334          *      10 = Length 48
335          *      11 = Length 48 Check busy after response
336          */
337         /* Delay added before checking the status of frq change
338          * retry not supported by mmc.c(core file)
339          */
340         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
341                 udelay(50000); /* wait 50 ms */
342
343         if (!(cmd->resp_type & MMC_RSP_PRESENT))
344                 flags = 0;
345         else if (cmd->resp_type & MMC_RSP_136)
346                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
347         else if (cmd->resp_type & MMC_RSP_BUSY)
348                 flags = RSP_TYPE_LGHT48B;
349         else
350                 flags = RSP_TYPE_LGHT48;
351
352         /* enable default flags */
353         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
354                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
355
356         if (cmd->resp_type & MMC_RSP_CRC)
357                 flags |= CCCE_CHECK;
358         if (cmd->resp_type & MMC_RSP_OPCODE)
359                 flags |= CICE_CHECK;
360
361         if (data) {
362                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
363                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
364                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
365                         data->blocksize = 512;
366                         writel(data->blocksize | (data->blocks << 16),
367                                                         &mmc_base->blk);
368                 } else
369                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
370
371                 if (data->flags & MMC_DATA_READ)
372                         flags |= (DP_DATA | DDIR_READ);
373                 else
374                         flags |= (DP_DATA | DDIR_WRITE);
375         }
376
377         writel(cmd->cmdarg, &mmc_base->arg);
378         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
379
380         start = get_timer(0);
381         do {
382                 mmc_stat = readl(&mmc_base->stat);
383                 if (get_timer(start) > MAX_RETRY_MS) {
384                         printf("%s : timeout: No status update\n", __func__);
385                         return TIMEOUT;
386                 }
387         } while (!mmc_stat);
388
389         if ((mmc_stat & IE_CTO) != 0) {
390                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
391                 return TIMEOUT;
392         } else if ((mmc_stat & ERRI_MASK) != 0)
393                 return -1;
394
395         if (mmc_stat & CC_MASK) {
396                 writel(CC_MASK, &mmc_base->stat);
397                 if (cmd->resp_type & MMC_RSP_PRESENT) {
398                         if (cmd->resp_type & MMC_RSP_136) {
399                                 /* response type 2 */
400                                 cmd->response[3] = readl(&mmc_base->rsp10);
401                                 cmd->response[2] = readl(&mmc_base->rsp32);
402                                 cmd->response[1] = readl(&mmc_base->rsp54);
403                                 cmd->response[0] = readl(&mmc_base->rsp76);
404                         } else
405                                 /* response types 1, 1b, 3, 4, 5, 6 */
406                                 cmd->response[0] = readl(&mmc_base->rsp10);
407                 }
408         }
409
410         if (data && (data->flags & MMC_DATA_READ)) {
411                 mmc_read_data(mmc_base, data->dest,
412                                 data->blocksize * data->blocks);
413         } else if (data && (data->flags & MMC_DATA_WRITE)) {
414                 mmc_write_data(mmc_base, data->src,
415                                 data->blocksize * data->blocks);
416         }
417         return 0;
418 }
419
420 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
421 {
422         unsigned int *output_buf = (unsigned int *)buf;
423         unsigned int mmc_stat;
424         unsigned int count;
425
426         /*
427          * Start Polled Read
428          */
429         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
430         count /= 4;
431
432         while (size) {
433                 ulong start = get_timer(0);
434                 do {
435                         mmc_stat = readl(&mmc_base->stat);
436                         if (get_timer(start) > MAX_RETRY_MS) {
437                                 printf("%s: timeout waiting for status!\n",
438                                                 __func__);
439                                 return TIMEOUT;
440                         }
441                 } while (mmc_stat == 0);
442
443                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
444                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
445
446                 if ((mmc_stat & ERRI_MASK) != 0)
447                         return 1;
448
449                 if (mmc_stat & BRR_MASK) {
450                         unsigned int k;
451
452                         writel(readl(&mmc_base->stat) | BRR_MASK,
453                                 &mmc_base->stat);
454                         for (k = 0; k < count; k++) {
455                                 *output_buf = readl(&mmc_base->data);
456                                 output_buf++;
457                         }
458                         size -= (count*4);
459                 }
460
461                 if (mmc_stat & BWR_MASK)
462                         writel(readl(&mmc_base->stat) | BWR_MASK,
463                                 &mmc_base->stat);
464
465                 if (mmc_stat & TC_MASK) {
466                         writel(readl(&mmc_base->stat) | TC_MASK,
467                                 &mmc_base->stat);
468                         break;
469                 }
470         }
471         return 0;
472 }
473
474 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
475                                 unsigned int size)
476 {
477         unsigned int *input_buf = (unsigned int *)buf;
478         unsigned int mmc_stat;
479         unsigned int count;
480
481         /*
482          * Start Polled Read
483          */
484         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
485         count /= 4;
486
487         while (size) {
488                 ulong start = get_timer(0);
489                 do {
490                         mmc_stat = readl(&mmc_base->stat);
491                         if (get_timer(start) > MAX_RETRY_MS) {
492                                 printf("%s: timeout waiting for status!\n",
493                                                 __func__);
494                                 return TIMEOUT;
495                         }
496                 } while (mmc_stat == 0);
497
498                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
499                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
500
501                 if ((mmc_stat & ERRI_MASK) != 0)
502                         return 1;
503
504                 if (mmc_stat & BWR_MASK) {
505                         unsigned int k;
506
507                         writel(readl(&mmc_base->stat) | BWR_MASK,
508                                         &mmc_base->stat);
509                         for (k = 0; k < count; k++) {
510                                 writel(*input_buf, &mmc_base->data);
511                                 input_buf++;
512                         }
513                         size -= (count*4);
514                 }
515
516                 if (mmc_stat & BRR_MASK)
517                         writel(readl(&mmc_base->stat) | BRR_MASK,
518                                 &mmc_base->stat);
519
520                 if (mmc_stat & TC_MASK) {
521                         writel(readl(&mmc_base->stat) | TC_MASK,
522                                 &mmc_base->stat);
523                         break;
524                 }
525         }
526         return 0;
527 }
528
529 static void mmc_set_ios(struct mmc *mmc)
530 {
531         struct omap_hsmmc_data *priv_data = mmc->priv;
532         struct hsmmc *mmc_base = priv_data->base_addr;
533         unsigned int dsor = 0;
534         ulong start;
535
536         /* configue bus width */
537         switch (mmc->bus_width) {
538         case 8:
539                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
540                         &mmc_base->con);
541                 break;
542
543         case 4:
544                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
545                         &mmc_base->con);
546                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
547                         &mmc_base->hctl);
548                 break;
549
550         case 1:
551         default:
552                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
553                         &mmc_base->con);
554                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
555                         &mmc_base->hctl);
556                 break;
557         }
558
559         /* configure clock with 96Mhz system clock.
560          */
561         if (mmc->clock != 0) {
562                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
563                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
564                         dsor++;
565         }
566
567         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
568                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
569
570         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
571                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
572
573         start = get_timer(0);
574         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
575                 if (get_timer(start) > MAX_RETRY_MS) {
576                         printf("%s: timeout waiting for ics!\n", __func__);
577                         return;
578                 }
579         }
580         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
581 }
582
583 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
584                 int wp_gpio)
585 {
586         struct mmc *mmc = &hsmmc_dev[dev_index];
587         struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
588
589         sprintf(mmc->name, "OMAP SD/MMC");
590         mmc->send_cmd = mmc_send_cmd;
591         mmc->set_ios = mmc_set_ios;
592         mmc->init = mmc_init_setup;
593         mmc->priv = priv_data;
594
595         switch (dev_index) {
596         case 0:
597                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
598                 break;
599 #ifdef OMAP_HSMMC2_BASE
600         case 1:
601                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
602                 break;
603 #endif
604 #ifdef OMAP_HSMMC3_BASE
605         case 2:
606                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
607                 break;
608 #endif
609         default:
610                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
611                 return 1;
612         }
613         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
614         if (priv_data->cd_gpio != -1)
615                 mmc->getcd = omap_mmc_getcd;
616
617         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
618         if (priv_data->wp_gpio != -1)
619                 mmc->getwp = omap_mmc_getwp;
620
621         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
622         mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
623                                 MMC_MODE_HC) & ~host_caps_mask;
624
625         mmc->f_min = 400000;
626
627         if (f_max != 0)
628                 mmc->f_max = f_max;
629         else {
630                 if (mmc->host_caps & MMC_MODE_HS) {
631                         if (mmc->host_caps & MMC_MODE_HS_52MHz)
632                                 mmc->f_max = 52000000;
633                         else
634                                 mmc->f_max = 26000000;
635                 } else
636                         mmc->f_max = 20000000;
637         }
638
639         mmc->b_max = 0;
640
641 #if defined(CONFIG_OMAP34XX)
642         /*
643          * Silicon revs 2.1 and older do not support multiblock transfers.
644          */
645         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
646                 mmc->b_max = 1;
647 #endif
648
649         mmc_register(mmc);
650
651         return 0;
652 }