drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <mmc.h>
  29 #include <part.h>
  30 #include <i2c.h>
  31 #include <twl4030.h>
  32 #include <twl6030.h>
  33 #include <palmas.h>
  34 #include <asm/gpio.h>
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  40 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  41         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  42 #define OMAP_HSMMC_USE_GPIO
  43 #else
  44 #undef OMAP_HSMMC_USE_GPIO
  45 #endif
  46
  47 /* common definitions for all OMAPs */
  48 #define SYSCTL_SRC      (1 << 25)
  49 #define SYSCTL_SRD      (1 << 26)
  50
  51 struct omap_hsmmc_data {
  52         struct hsmmc *base_addr;
  53         struct mmc_config cfg;
  54 #ifdef OMAP_HSMMC_USE_GPIO
  55         int cd_gpio;
  56         int wp_gpio;
  57 #endif
  58 };
  59
  60 /* If we fail after 1 second wait, something is really bad */
  61 #define MAX_RETRY_MS    1000
  62
  63 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  64 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  65                         unsigned int siz);
  66
  67 #ifdef OMAP_HSMMC_USE_GPIO
  68 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  69 {
  70         int ret;
  71
  72 #ifndef CONFIG_DM_GPIO
  73         if (!gpio_is_valid(gpio))
  74                 return -1;
  75 #endif
  76         ret = gpio_request(gpio, label);
  77         if (ret)
  78                 return ret;
  79
  80         ret = gpio_direction_input(gpio);
  81         if (ret)
  82                 return ret;
  83
  84         return gpio;
  85 }
  86 #endif
  87
  88 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  89 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  90 {
  91         u32 value = 0;
  92
  93         value = readl((*ctrl)->control_pbiaslite);
  94         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
  95         writel(value, (*ctrl)->control_pbiaslite);
  96         /* set VMMC to 3V */
  97         twl6030_power_mmc_init();
  98         value = readl((*ctrl)->control_pbiaslite);
  99         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 100         writel(value, (*ctrl)->control_pbiaslite);
 101 }
 102 #endif
 103
 104 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 105 static void omap5_pbias_config(struct mmc *mmc)
 106 {
 107         u32 value = 0;
 108
 109         value = readl((*ctrl)->control_pbias);
 110         value &= ~SDCARD_PWRDNZ;
 111         writel(value, (*ctrl)->control_pbias);
 112         udelay(10); /* wait 10 us */
 113         value &= ~SDCARD_BIAS_PWRDNZ;
 114         writel(value, (*ctrl)->control_pbias);
 115
 116         palmas_mmc1_poweron_ldo();
 117
 118         value = readl((*ctrl)->control_pbias);
 119         value |= SDCARD_BIAS_PWRDNZ;
 120         writel(value, (*ctrl)->control_pbias);
 121         udelay(150); /* wait 150 us */
 122         value |= SDCARD_PWRDNZ;
 123         writel(value, (*ctrl)->control_pbias);
 124         udelay(150); /* wait 150 us */
 125 }
 126 #endif
 127
 128 static void mmc_board_init(struct mmc *mmc)
 129 {
 130 #if defined(CONFIG_OMAP34XX)
 131         t2_t *t2_base = (t2_t *)T2_BASE;
 132         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 133         u32 pbias_lite;
 134
 135         pbias_lite = readl(&t2_base->pbias_lite);
 136         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 137         writel(pbias_lite, &t2_base->pbias_lite);
 138
 139         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 140                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 141                 &t2_base->pbias_lite);
 142
 143         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 144                 &t2_base->devconf0);
 145
 146         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 147                 &t2_base->devconf1);
 148
 149         /* Change from default of 52MHz to 26MHz if necessary */
 150         if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
 151                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 152                         &t2_base->ctl_prog_io1);
 153
 154         writel(readl(&prcm_base->fclken1_core) |
 155                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 156                 &prcm_base->fclken1_core);
 157
 158         writel(readl(&prcm_base->iclken1_core) |
 159                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 160                 &prcm_base->iclken1_core);
 161 #endif
 162
 163 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 164         /* PBIAS config needed for MMC1 only */
 165         if (mmc->block_dev.dev == 0)
 166                 omap4_vmmc_pbias_config(mmc);
 167 #endif
 168 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 169         if (mmc->block_dev.dev == 0)
 170                 omap5_pbias_config(mmc);
 171 #endif
 172 }
 173
 174 void mmc_init_stream(struct hsmmc *mmc_base)
 175 {
 176         ulong start;
 177
 178         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 179
 180         writel(MMC_CMD0, &mmc_base->cmd);
 181         start = get_timer(0);
 182         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 183                 if (get_timer(start) > MAX_RETRY_MS)
 184                         break;
 185         }
 186         if (!(readl(&mmc_base->stat) & CC_MASK)) {
 187                 printf("%s: timeout waiting for cc!\n", __func__);
 188                 return;
 189         }
 190
 191         writel(CC_MASK, &mmc_base->stat);
 192         writel(MMC_CMD0, &mmc_base->cmd);
 193
 194         start = get_timer(0);
 195         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 196                 if (get_timer(start) > MAX_RETRY_MS)
 197                         break;
 198         }
 199         if (!(readl(&mmc_base->stat) & CC_MASK)) {
 200                 printf("%s: timeout waiting for cc2!\n", __func__);
 201                 return;
 202         }
 203         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 204 }
 205
 206
 207 static int omap_hsmmc_init_setup(struct mmc *mmc)
 208 {
 209         struct omap_hsmmc_data *priv_data = mmc->priv;
 210         struct hsmmc *mmc_base = priv_data->base_addr;
 211         unsigned int reg_val;
 212         unsigned int dsor;
 213         ulong start;
 214
 215         mmc_board_init(mmc);
 216
 217         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 218                 &mmc_base->sysconfig);
 219         start = get_timer(0);
 220         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 221                 if (get_timer(start) > MAX_RETRY_MS)
 222                         break;
 223         }
 224         if ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 225                 printf("%s: timeout %08x waiting for softreset done!\n", __func__,
 226                         readl(&mmc_base->sysstatus));
 227                 return TIMEOUT;
 228         }
 229         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 230         start = get_timer(0);
 231         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0) {
 232                 if (get_timer(start) > MAX_RETRY_MS)
 233                         break;
 234         }
 235         if ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0) {
 236                 printf("%s: timeout waiting for softresetall!\n", __func__);
 237                 return TIMEOUT;
 238         }
 239         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 240         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 241                 &mmc_base->capa);
 242
 243         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 244
 245         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 246                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 247                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 248
 249         dsor = 240;
 250         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 251                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 252         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 253                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 254         start = get_timer(0);
 255         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 256                 if (get_timer(start) > MAX_RETRY_MS)
 257                         break;
 258         }
 259         if ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 260                 printf("%s: timeout waiting for ics!\n", __func__);
 261                 return TIMEOUT;
 262         }
 263         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 264
 265         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 266
 267         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 268                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 269                 &mmc_base->ie);
 270
 271         mmc_init_stream(mmc_base);
 272
 273         return 0;
 274 }
 275
 276 /*
 277  * MMC controller internal finite state machine reset
 278  *
 279  * Used to reset command or data internal state machines, using respectively
 280  * SRC or SRD bit of SYSCTL register
 281  */
 282 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 283 {
 284         ulong start;
 285
 286         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 287
 288         /*
 289          * CMD(DAT) lines reset procedures are slightly different
 290          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 291          * According to OMAP3 TRM:
 292          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 293          * returns to 0x0.
 294          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 295          * procedure steps must be as follows:
 296          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 297          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 298          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 299          * 3. Wait until the SRC (SRD) bit returns to 0x0
 300          *    (reset procedure is completed).
 301          */
 302 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 303         defined(CONFIG_AM33XX)
 304         if (!(readl(&mmc_base->sysctl) & bit)) {
 305                 start = get_timer(0);
 306                 while (!(readl(&mmc_base->sysctl) & bit)) {
 307                         if (get_timer(0) - start > MAX_RETRY_MS)
 308                                 return;
 309                 }
 310         }
 311 #endif
 312         start = get_timer(0);
 313         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 314                 if (get_timer(0) - start > MAX_RETRY_MS)
 315                         break;
 316         }
 317         if ((readl(&mmc_base->sysctl) & bit) != 0) {
 318                 printf("%s: timedout waiting for sysctl %x to clear\n", __func__, bit);
 319                 return;
 320         }
 321 }
 322
 323 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 324                         struct mmc_data *data)
 325 {
 326         struct omap_hsmmc_data *priv_data = mmc->priv;
 327         struct hsmmc *mmc_base = priv_data->base_addr;
 328         unsigned int flags, mmc_stat;
 329         ulong start;
 330
 331         start = get_timer(0);
 332         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 333                 if (get_timer(start) > MAX_RETRY_MS)
 334                         break;
 335         }
 336         if ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 337                 printf("%s: timeout waiting on cmd inhibit to clear\n", __func__);
 338                 return TIMEOUT;
 339         }
 340         writel(0xFFFFFFFF, &mmc_base->stat);
 341         start = get_timer(0);
 342         while (readl(&mmc_base->stat)) {
 343                 if (get_timer(start) > MAX_RETRY_MS)
 344                         break;
 345         }
 346         if (readl(&mmc_base->stat)) {
 347                 printf("%s: timeout waiting for stat!\n", __func__);
 348                 return TIMEOUT;
 349         }
 350         /*
 351          * CMDREG
 352          * CMDIDX[13:8] : Command index
 353          * DATAPRNT[5]  : Data Present Select
 354          * ENCMDIDX[4]  : Command Index Check Enable
 355          * ENCMDCRC[3]  : Command CRC Check Enable
 356          * RSPTYP[1:0]
 357          *      00 = No Response
 358          *      01 = Length 136
 359          *      10 = Length 48
 360          *      11 = Length 48 Check busy after response
 361          */
 362         /* Delay added before checking the status of frq change
 363          * retry not supported by mmc.c(core file)
 364          */
 365         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 366                 udelay(50000); /* wait 50 ms */
 367
 368         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 369                 flags = 0;
 370         else if (cmd->resp_type & MMC_RSP_136)
 371                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 372         else if (cmd->resp_type & MMC_RSP_BUSY)
 373                 flags = RSP_TYPE_LGHT48B;
 374         else
 375                 flags = RSP_TYPE_LGHT48;
 376
 377         /* enable default flags */
 378         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 379                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 380
 381         if (cmd->resp_type & MMC_RSP_CRC)
 382                 flags |= CCCE_CHECK;
 383         if (cmd->resp_type & MMC_RSP_OPCODE)
 384                 flags |= CICE_CHECK;
 385
 386         if (data) {
 387                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 388                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 389                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 390                         data->blocksize = 512;
 391                         writel(data->blocksize | (data->blocks << 16),
 392                                                         &mmc_base->blk);
 393                 } else
 394                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 395
 396                 if (data->flags & MMC_DATA_READ)
 397                         flags |= (DP_DATA | DDIR_READ);
 398                 else
 399                         flags |= (DP_DATA | DDIR_WRITE);
 400         }
 401
 402         writel(cmd->cmdarg, &mmc_base->arg);
 403         udelay(20);             /* To fix "No status update" error on eMMC */
 404         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 405
 406         start = get_timer(0);
 407         while (!(mmc_stat = readl(&mmc_base->stat))) {
 408                 if (get_timer(start) > MAX_RETRY_MS)
 409                         break;
 410         }
 411         if (!mmc_stat) {
 412                 printf("%s : timeout: No status update\n", __func__);
 413                 return TIMEOUT;
 414         }
 415
 416         if ((mmc_stat & IE_CTO) != 0) {
 417                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 418                 return TIMEOUT;
 419         } else if ((mmc_stat & ERRI_MASK) != 0)
 420                 return -1;
 421
 422         if (mmc_stat & CC_MASK) {
 423                 writel(CC_MASK, &mmc_base->stat);
 424                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 425                         if (cmd->resp_type & MMC_RSP_136) {
 426                                 /* response type 2 */
 427                                 cmd->response[3] = readl(&mmc_base->rsp10);
 428                                 cmd->response[2] = readl(&mmc_base->rsp32);
 429                                 cmd->response[1] = readl(&mmc_base->rsp54);
 430                                 cmd->response[0] = readl(&mmc_base->rsp76);
 431                         } else
 432                                 /* response types 1, 1b, 3, 4, 5, 6 */
 433                                 cmd->response[0] = readl(&mmc_base->rsp10);
 434                 }
 435         }
 436
 437         if (data && (data->flags & MMC_DATA_READ)) {
 438                 mmc_read_data(mmc_base, data->dest,
 439                                 data->blocksize * data->blocks);
 440         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 441                 mmc_write_data(mmc_base, data->src,
 442                                 data->blocksize * data->blocks);
 443         }
 444         return 0;
 445 }
 446
 447 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 448 {
 449         unsigned int *output_buf = (unsigned int *)buf;
 450         unsigned int mmc_stat;
 451         unsigned int count;
 452
 453         /*
 454          * Start Polled Read
 455          */
 456         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 457         count /= 4;
 458
 459         while (size) {
 460                 ulong start = get_timer(0);
 461
 462                 while (!(mmc_stat = readl(&mmc_base->stat))) {
 463                         if (get_timer(start) > MAX_RETRY_MS)
 464                                 break;
 465                 }
 466                 if (!mmc_stat) {
 467                         printf("%s: timeout waiting for status!\n", __func__);
 468                         return TIMEOUT;
 469                 }
 470
 471                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 472                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 473
 474                 if ((mmc_stat & ERRI_MASK) != 0)
 475                         return 1;
 476
 477                 if (mmc_stat & BRR_MASK) {
 478                         unsigned int k;
 479
 480                         writel(readl(&mmc_base->stat) | BRR_MASK,
 481                                 &mmc_base->stat);
 482                         for (k = 0; k < count; k++) {
 483                                 *output_buf = readl(&mmc_base->data);
 484                                 output_buf++;
 485                         }
 486                         size -= (count*4);
 487                 }
 488
 489                 if (mmc_stat & BWR_MASK)
 490                         writel(readl(&mmc_base->stat) | BWR_MASK,
 491                                 &mmc_base->stat);
 492
 493                 if (mmc_stat & TC_MASK) {
 494                         writel(readl(&mmc_base->stat) | TC_MASK,
 495                                 &mmc_base->stat);
 496                         break;
 497                 }
 498         }
 499         return 0;
 500 }
 501
 502 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 503                                 unsigned int size)
 504 {
 505         unsigned int *input_buf = (unsigned int *)buf;
 506         unsigned int mmc_stat;
 507         unsigned int count;
 508
 509         /*
 510          * Start Polled Write
 511          */
 512         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 513         count /= 4;
 514
 515         while (size) {
 516                 ulong start = get_timer(0);
 517
 518                 while (!(mmc_stat = readl(&mmc_base->stat))) {
 519                         if (get_timer(start) > MAX_RETRY_MS)
 520                                 break;
 521                 }
 522                 if (!mmc_stat) {
 523                         printf("%s: timeout waiting for status!\n", __func__);
 524                         return TIMEOUT;
 525                 }
 526
 527                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 528                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 529
 530                 if ((mmc_stat & ERRI_MASK) != 0)
 531                         return 1;
 532
 533                 if (mmc_stat & BWR_MASK) {
 534                         unsigned int k;
 535
 536                         writel(readl(&mmc_base->stat) | BWR_MASK,
 537                                         &mmc_base->stat);
 538                         for (k = 0; k < count; k++) {
 539                                 writel(*input_buf, &mmc_base->data);
 540                                 input_buf++;
 541                         }
 542                         size -= (count*4);
 543                 }
 544
 545                 if (mmc_stat & BRR_MASK)
 546                         writel(readl(&mmc_base->stat) | BRR_MASK,
 547                                 &mmc_base->stat);
 548
 549                 if (mmc_stat & TC_MASK) {
 550                         writel(readl(&mmc_base->stat) | TC_MASK,
 551                                 &mmc_base->stat);
 552                         break;
 553                 }
 554         }
 555         return 0;
 556 }
 557
 558 static void omap_hsmmc_set_ios(struct mmc *mmc)
 559 {
 560         struct omap_hsmmc_data *priv_data = mmc->priv;
 561         struct hsmmc *mmc_base = priv_data->base_addr;
 562         unsigned int dsor = 0;
 563         ulong start;
 564
 565         /* configue bus width */
 566         switch (mmc->bus_width) {
 567         case 8:
 568                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 569                         &mmc_base->con);
 570                 break;
 571
 572         case 4:
 573                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 574                         &mmc_base->con);
 575                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 576                         &mmc_base->hctl);
 577                 break;
 578
 579         case 1:
 580         default:
 581                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 582                         &mmc_base->con);
 583                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 584                         &mmc_base->hctl);
 585                 break;
 586         }
 587
 588         /* configure clock with 96Mhz system clock.
 589          */
 590         if (mmc->clock != 0) {
 591                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 592                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 593                         dsor++;
 594         }
 595
 596         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 597                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 598
 599         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 600                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 601
 602         start = get_timer(0);
 603         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 604                 if (get_timer(start) > MAX_RETRY_MS)
 605                         break;
 606         }
 607         if ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 608                 printf("%s: timeout waiting for ics!\n", __func__);
 609                 return;
 610         }
 611         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 612 }
 613
 614 #ifdef OMAP_HSMMC_USE_GPIO
 615 static int omap_hsmmc_getcd(struct mmc *mmc)
 616 {
 617         struct omap_hsmmc_data *priv_data = mmc->priv;
 618         int cd_gpio;
 619
 620         /* if no CD return as 1 */
 621         cd_gpio = priv_data->cd_gpio;
 622         if (cd_gpio < 0)
 623                 return 1;
 624
 625         /* NOTE: assumes card detect signal is active-low */
 626         return !gpio_get_value(cd_gpio);
 627 }
 628
 629 static int omap_hsmmc_getwp(struct mmc *mmc)
 630 {
 631         struct omap_hsmmc_data *priv_data = mmc->priv;
 632         int wp_gpio;
 633
 634         /* if no WP return as 0 */
 635         wp_gpio = priv_data->wp_gpio;
 636         if (wp_gpio < 0)
 637                 return 0;
 638
 639         /* NOTE: assumes write protect signal is active-high */
 640         return gpio_get_value(wp_gpio);
 641 }
 642 #endif
 643
 644 static const struct mmc_ops omap_hsmmc_ops = {
 645         .send_cmd       = omap_hsmmc_send_cmd,
 646         .set_ios        = omap_hsmmc_set_ios,
 647         .init           = omap_hsmmc_init_setup,
 648 #ifdef OMAP_HSMMC_USE_GPIO
 649         .getcd          = omap_hsmmc_getcd,
 650         .getwp          = omap_hsmmc_getwp,
 651 #endif
 652 };
 653
 654 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 655                 int wp_gpio)
 656 {
 657         int ret;
 658         struct mmc *mmc;
 659         struct omap_hsmmc_data *priv_data;
 660         struct mmc_config *cfg;
 661         uint host_caps_val;
 662
 663         priv_data = calloc(sizeof(*priv_data), 1);
 664         if (priv_data == NULL)
 665                 return -ENOMEM;
 666
 667         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
 668                              MMC_MODE_HC;
 669
 670         switch (dev_index) {
 671         case 0:
 672                 base_addr = OMAP_HSMMC1_BASE;
 673                 break;
 674 #ifdef OMAP_HSMMC2_BASE
 675         case 1:
 676                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 677 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 678      defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \
 679                 defined(CONFIG_HSMMC2_8BIT)
 680                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
 681                 host_caps_val |= MMC_MODE_8BIT;
 682 #endif
 683                 break;
 684 #endif
 685 #ifdef OMAP_HSMMC3_BASE
 686         case 2:
 687                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
 688 #if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
 689                 /* Enable 8-bit interface for eMMC on DRA7XX */
 690                 host_caps_val |= MMC_MODE_8BIT;
 691 #endif
 692                 break;
 693 #endif
 694         default:
 695                 printf("Invalid MMC device index: %d\n", dev_index);
 696                 ret = 1;
 697                 goto out;
 698         }
 699 #ifdef OMAP_HSMMC_USE_GPIO
 700         /* on error gpio values are set to -1, which is what we want */
 701         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 702         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 703 #endif
 704
 705         cfg = &priv_data->cfg;
 706
 707         cfg->name = "OMAP SD/MMC";
 708         cfg->ops = &omap_hsmmc_ops;
 709
 710         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 711         cfg->host_caps = host_caps_val & ~host_caps_mask;
 712
 713         cfg->f_min = 400000;
 714
 715         if (f_max != 0)
 716                 cfg->f_max = f_max;
 717         else {
 718                 if (cfg->host_caps & MMC_MODE_HS) {
 719                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
 720                                 cfg->f_max = 52000000;
 721                         else
 722                                 cfg->f_max = 26000000;
 723                 } else
 724                         cfg->f_max = 20000000;
 725         }
 726
 727         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 728
 729 #if defined(CONFIG_OMAP34XX)
 730         /*
 731          * Silicon revs 2.1 and older do not support multiblock transfers.
 732          */
 733         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 734                 cfg->b_max = 1;
 735 #endif
 736         mmc = mmc_create(cfg, priv_data);
 737         if (mmc == NULL) {
 738                 ret = -ENOMEM;
 739                 goto out;
 740         }
 741
 742         return 0;
 743
 744 out:
 745         free(priv_data);
 746         return ret;
 747 }