drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <mmc.h>
  28 #include <part.h>
  29 #include <i2c.h>
  30 #include <twl4030.h>
  31 #include <twl6030.h>
  32 #include <palmas.h>
  33 #include <asm/gpio.h>
  34 #include <asm/io.h>
  35 #include <asm/arch/mmc_host_def.h>
  36 #include <asm/arch/sys_proto.h>
  37
  38 /* common definitions for all OMAPs */
  39 #define SYSCTL_SRC      (1 << 25)
  40 #define SYSCTL_SRD      (1 << 26)
  41
  42 struct omap_hsmmc_data {
  43         struct hsmmc *base_addr;
  44         int cd_gpio;
  45         int wp_gpio;
  46 };
  47
  48 /* If we fail after 1 second wait, something is really bad */
  49 #define MAX_RETRY_MS    1000
  50
  51 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  52 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  53                         unsigned int siz);
  54 static struct mmc hsmmc_dev[3];
  55 static struct omap_hsmmc_data hsmmc_dev_data[3];
  56
  57 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  58         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  59 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  60 {
  61         if (!gpio_is_valid(gpio))
  62                 return -1;
  63
  64         if (gpio_request(gpio, label) < 0)
  65                 return -1;
  66
  67         if (gpio_direction_input(gpio) < 0)
  68                 return -1;
  69
  70         return gpio;
  71 }
  72
  73 static int omap_mmc_getcd(struct mmc *mmc)
  74 {
  75         int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
  76         return gpio_get_value(cd_gpio);
  77 }
  78
  79 static int omap_mmc_getwp(struct mmc *mmc)
  80 {
  81         int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio;
  82         return gpio_get_value(wp_gpio);
  83 }
  84 #else
  85 static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
  86 {
  87         return -1;
  88 }
  89
  90 #define omap_mmc_getcd NULL
  91 #define omap_mmc_getwp NULL
  92 #endif
  93
  94 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  95 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  96 {
  97         u32 value = 0;
  98
  99         value = readl((*ctrl)->control_pbiaslite);
 100         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
 101         writel(value, (*ctrl)->control_pbiaslite);
 102         /* set VMMC to 3V */
 103         twl6030_power_mmc_init();
 104         value = readl((*ctrl)->control_pbiaslite);
 105         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 106         writel(value, (*ctrl)->control_pbiaslite);
 107 }
 108 #endif
 109
 110 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 111 static void omap5_pbias_config(struct mmc *mmc)
 112 {
 113         u32 value = 0;
 114
 115         value = readl((*ctrl)->control_pbias);
 116         value &= ~SDCARD_PWRDNZ;
 117         writel(value, (*ctrl)->control_pbias);
 118         udelay(10); /* wait 10 us */
 119         value &= ~SDCARD_BIAS_PWRDNZ;
 120         writel(value, (*ctrl)->control_pbias);
 121
 122         palmas_mmc1_poweron_ldo();
 123
 124         value = readl((*ctrl)->control_pbias);
 125         value |= SDCARD_BIAS_PWRDNZ;
 126         writel(value, (*ctrl)->control_pbias);
 127         udelay(150); /* wait 150 us */
 128         value |= SDCARD_PWRDNZ;
 129         writel(value, (*ctrl)->control_pbias);
 130         udelay(150); /* wait 150 us */
 131 }
 132 #endif
 133
 134 static void mmc_board_init(struct mmc *mmc)
 135 {
 136 #if defined(CONFIG_OMAP34XX)
 137         t2_t *t2_base = (t2_t *)T2_BASE;
 138         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 139         u32 pbias_lite;
 140
 141         pbias_lite = readl(&t2_base->pbias_lite);
 142         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 143         writel(pbias_lite, &t2_base->pbias_lite);
 144 #endif
 145 #if defined(CONFIG_TWL4030_POWER)
 146         twl4030_power_mmc_init();
 147         mdelay(100);    /* ramp-up delay from Linux code */
 148 #endif
 149 #if defined(CONFIG_OMAP34XX)
 150         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 151                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 152                 &t2_base->pbias_lite);
 153
 154         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 155                 &t2_base->devconf0);
 156
 157         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 158                 &t2_base->devconf1);
 159
 160         /* Change from default of 52MHz to 26MHz if necessary */
 161         if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
 162                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 163                         &t2_base->ctl_prog_io1);
 164
 165         writel(readl(&prcm_base->fclken1_core) |
 166                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 167                 &prcm_base->fclken1_core);
 168
 169         writel(readl(&prcm_base->iclken1_core) |
 170                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 171                 &prcm_base->iclken1_core);
 172 #endif
 173
 174 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 175         /* PBIAS config needed for MMC1 only */
 176         if (mmc->block_dev.dev == 0)
 177                 omap4_vmmc_pbias_config(mmc);
 178 #endif
 179 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 180         if (mmc->block_dev.dev == 0)
 181                 omap5_pbias_config(mmc);
 182 #endif
 183 }
 184
 185 void mmc_init_stream(struct hsmmc *mmc_base)
 186 {
 187         ulong start;
 188
 189         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 190
 191         writel(MMC_CMD0, &mmc_base->cmd);
 192         start = get_timer(0);
 193         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 194                 if (get_timer(start) > MAX_RETRY_MS) {
 195                         printf("%s: timeout waiting for cc!\n", __func__);
 196                         return;
 197                 }
 198         }
 199         writel(CC_MASK, &mmc_base->stat)
 200                 ;
 201         writel(MMC_CMD0, &mmc_base->cmd)
 202                 ;
 203         start = get_timer(0);
 204         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 205                 if (get_timer(start) > MAX_RETRY_MS) {
 206                         printf("%s: timeout waiting for cc2!\n", __func__);
 207                         return;
 208                 }
 209         }
 210         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 211 }
 212
 213 static int mmc_init_setup(struct mmc *mmc)
 214 {
 215         struct omap_hsmmc_data *priv_data = mmc->priv;
 216         struct hsmmc *mmc_base = priv_data->base_addr;
 217         unsigned int reg_val;
 218         unsigned int dsor;
 219         ulong start;
 220
 221         mmc_board_init(mmc);
 222
 223         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 224                 &mmc_base->sysconfig);
 225         start = get_timer(0);
 226         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 227                 if (get_timer(start) > MAX_RETRY_MS) {
 228                         printf("%s: timeout waiting for cc2!\n", __func__);
 229                         return TIMEOUT;
 230                 }
 231         }
 232         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 233         start = get_timer(0);
 234         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 235                 if (get_timer(start) > MAX_RETRY_MS) {
 236                         printf("%s: timeout waiting for softresetall!\n",
 237                                 __func__);
 238                         return TIMEOUT;
 239                 }
 240         }
 241         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 242         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 243                 &mmc_base->capa);
 244
 245         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 246
 247         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 248                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 249                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 250
 251         dsor = 240;
 252         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 253                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 254         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 255                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 256         start = get_timer(0);
 257         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 258                 if (get_timer(start) > MAX_RETRY_MS) {
 259                         printf("%s: timeout waiting for ics!\n", __func__);
 260                         return TIMEOUT;
 261                 }
 262         }
 263         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 264
 265         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 266
 267         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 268                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 269                 &mmc_base->ie);
 270
 271         mmc_init_stream(mmc_base);
 272
 273         return 0;
 274 }
 275
 276 /*
 277  * MMC controller internal finite state machine reset
 278  *
 279  * Used to reset command or data internal state machines, using respectively
 280  * SRC or SRD bit of SYSCTL register
 281  */
 282 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 283 {
 284         ulong start;
 285
 286         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 287
 288         start = get_timer(0);
 289         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 290                 if (get_timer(0) - start > MAX_RETRY_MS) {
 291                         printf("%s: timedout waiting for sysctl %x to clear\n",
 292                                 __func__, bit);
 293                         return;
 294                 }
 295         }
 296 }
 297
 298 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 299                         struct mmc_data *data)
 300 {
 301         struct omap_hsmmc_data *priv_data = mmc->priv;
 302         struct hsmmc *mmc_base = priv_data->base_addr;
 303         unsigned int flags, mmc_stat;
 304         ulong start;
 305
 306         start = get_timer(0);
 307         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 308                 if (get_timer(start) > MAX_RETRY_MS) {
 309                         printf("%s: timeout waiting on cmd inhibit to clear\n",
 310                                         __func__);
 311                         return TIMEOUT;
 312                 }
 313         }
 314         writel(0xFFFFFFFF, &mmc_base->stat);
 315         start = get_timer(0);
 316         while (readl(&mmc_base->stat)) {
 317                 if (get_timer(start) > MAX_RETRY_MS) {
 318                         printf("%s: timeout waiting for stat!\n", __func__);
 319                         return TIMEOUT;
 320                 }
 321         }
 322         /*
 323          * CMDREG
 324          * CMDIDX[13:8] : Command index
 325          * DATAPRNT[5]  : Data Present Select
 326          * ENCMDIDX[4]  : Command Index Check Enable
 327          * ENCMDCRC[3]  : Command CRC Check Enable
 328          * RSPTYP[1:0]
 329          *      00 = No Response
 330          *      01 = Length 136
 331          *      10 = Length 48
 332          *      11 = Length 48 Check busy after response
 333          */
 334         /* Delay added before checking the status of frq change
 335          * retry not supported by mmc.c(core file)
 336          */
 337         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 338                 udelay(50000); /* wait 50 ms */
 339
 340         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 341                 flags = 0;
 342         else if (cmd->resp_type & MMC_RSP_136)
 343                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 344         else if (cmd->resp_type & MMC_RSP_BUSY)
 345                 flags = RSP_TYPE_LGHT48B;
 346         else
 347                 flags = RSP_TYPE_LGHT48;
 348
 349         /* enable default flags */
 350         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 351                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 352
 353         if (cmd->resp_type & MMC_RSP_CRC)
 354                 flags |= CCCE_CHECK;
 355         if (cmd->resp_type & MMC_RSP_OPCODE)
 356                 flags |= CICE_CHECK;
 357
 358         if (data) {
 359                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 360                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 361                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 362                         data->blocksize = 512;
 363                         writel(data->blocksize | (data->blocks << 16),
 364                                                         &mmc_base->blk);
 365                 } else
 366                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 367
 368                 if (data->flags & MMC_DATA_READ)
 369                         flags |= (DP_DATA | DDIR_READ);
 370                 else
 371                         flags |= (DP_DATA | DDIR_WRITE);
 372         }
 373
 374         writel(cmd->cmdarg, &mmc_base->arg);
 375         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 376
 377         start = get_timer(0);
 378         do {
 379                 mmc_stat = readl(&mmc_base->stat);
 380                 if (get_timer(start) > MAX_RETRY_MS) {
 381                         printf("%s : timeout: No status update\n", __func__);
 382                         return TIMEOUT;
 383                 }
 384         } while (!mmc_stat);
 385
 386         if ((mmc_stat & IE_CTO) != 0) {
 387                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 388                 return TIMEOUT;
 389         } else if ((mmc_stat & ERRI_MASK) != 0)
 390                 return -1;
 391
 392         if (mmc_stat & CC_MASK) {
 393                 writel(CC_MASK, &mmc_base->stat);
 394                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 395                         if (cmd->resp_type & MMC_RSP_136) {
 396                                 /* response type 2 */
 397                                 cmd->response[3] = readl(&mmc_base->rsp10);
 398                                 cmd->response[2] = readl(&mmc_base->rsp32);
 399                                 cmd->response[1] = readl(&mmc_base->rsp54);
 400                                 cmd->response[0] = readl(&mmc_base->rsp76);
 401                         } else
 402                                 /* response types 1, 1b, 3, 4, 5, 6 */
 403                                 cmd->response[0] = readl(&mmc_base->rsp10);
 404                 }
 405         }
 406
 407         if (data && (data->flags & MMC_DATA_READ)) {
 408                 mmc_read_data(mmc_base, data->dest,
 409                                 data->blocksize * data->blocks);
 410         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 411                 mmc_write_data(mmc_base, data->src,
 412                                 data->blocksize * data->blocks);
 413         }
 414         return 0;
 415 }
 416
 417 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 418 {
 419         unsigned int *output_buf = (unsigned int *)buf;
 420         unsigned int mmc_stat;
 421         unsigned int count;
 422
 423         /*
 424          * Start Polled Read
 425          */
 426         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 427         count /= 4;
 428
 429         while (size) {
 430                 ulong start = get_timer(0);
 431                 do {
 432                         mmc_stat = readl(&mmc_base->stat);
 433                         if (get_timer(start) > MAX_RETRY_MS) {
 434                                 printf("%s: timeout waiting for status!\n",
 435                                                 __func__);
 436                                 return TIMEOUT;
 437                         }
 438                 } while (mmc_stat == 0);
 439
 440                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 441                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 442
 443                 if ((mmc_stat & ERRI_MASK) != 0)
 444                         return 1;
 445
 446                 if (mmc_stat & BRR_MASK) {
 447                         unsigned int k;
 448
 449                         writel(readl(&mmc_base->stat) | BRR_MASK,
 450                                 &mmc_base->stat);
 451                         for (k = 0; k < count; k++) {
 452                                 *output_buf = readl(&mmc_base->data);
 453                                 output_buf++;
 454                         }
 455                         size -= (count*4);
 456                 }
 457
 458                 if (mmc_stat & BWR_MASK)
 459                         writel(readl(&mmc_base->stat) | BWR_MASK,
 460                                 &mmc_base->stat);
 461
 462                 if (mmc_stat & TC_MASK) {
 463                         writel(readl(&mmc_base->stat) | TC_MASK,
 464                                 &mmc_base->stat);
 465                         break;
 466                 }
 467         }
 468         return 0;
 469 }
 470
 471 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 472                                 unsigned int size)
 473 {
 474         unsigned int *input_buf = (unsigned int *)buf;
 475         unsigned int mmc_stat;
 476         unsigned int count;
 477
 478         /*
 479          * Start Polled Read
 480          */
 481         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 482         count /= 4;
 483
 484         while (size) {
 485                 ulong start = get_timer(0);
 486                 do {
 487                         mmc_stat = readl(&mmc_base->stat);
 488                         if (get_timer(start) > MAX_RETRY_MS) {
 489                                 printf("%s: timeout waiting for status!\n",
 490                                                 __func__);
 491                                 return TIMEOUT;
 492                         }
 493                 } while (mmc_stat == 0);
 494
 495                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 496                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 497
 498                 if ((mmc_stat & ERRI_MASK) != 0)
 499                         return 1;
 500
 501                 if (mmc_stat & BWR_MASK) {
 502                         unsigned int k;
 503
 504                         writel(readl(&mmc_base->stat) | BWR_MASK,
 505                                         &mmc_base->stat);
 506                         for (k = 0; k < count; k++) {
 507                                 writel(*input_buf, &mmc_base->data);
 508                                 input_buf++;
 509                         }
 510                         size -= (count*4);
 511                 }
 512
 513                 if (mmc_stat & BRR_MASK)
 514                         writel(readl(&mmc_base->stat) | BRR_MASK,
 515                                 &mmc_base->stat);
 516
 517                 if (mmc_stat & TC_MASK) {
 518                         writel(readl(&mmc_base->stat) | TC_MASK,
 519                                 &mmc_base->stat);
 520                         break;
 521                 }
 522         }
 523         return 0;
 524 }
 525
 526 static void mmc_set_ios(struct mmc *mmc)
 527 {
 528         struct omap_hsmmc_data *priv_data = mmc->priv;
 529         struct hsmmc *mmc_base = priv_data->base_addr;
 530         unsigned int dsor = 0;
 531         ulong start;
 532
 533         /* configue bus width */
 534         switch (mmc->bus_width) {
 535         case 8:
 536                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 537                         &mmc_base->con);
 538                 break;
 539
 540         case 4:
 541                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 542                         &mmc_base->con);
 543                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 544                         &mmc_base->hctl);
 545                 break;
 546
 547         case 1:
 548         default:
 549                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 550                         &mmc_base->con);
 551                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 552                         &mmc_base->hctl);
 553                 break;
 554         }
 555
 556         /* configure clock with 96Mhz system clock.
 557          */
 558         if (mmc->clock != 0) {
 559                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 560                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 561                         dsor++;
 562         }
 563
 564         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 565                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 566
 567         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 568                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 569
 570         start = get_timer(0);
 571         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 572                 if (get_timer(start) > MAX_RETRY_MS) {
 573                         printf("%s: timeout waiting for ics!\n", __func__);
 574                         return;
 575                 }
 576         }
 577         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 578 }
 579
 580 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 581                 int wp_gpio)
 582 {
 583         struct mmc *mmc;
 584         struct omap_hsmmc_data *priv_data;
 585         unsigned long base_addr;
 586
 587         switch (dev_index) {
 588         case 0:
 589                 base_addr = OMAP_HSMMC1_BASE;
 590                 break;
 591 #ifdef OMAP_HSMMC2_BASE
 592         case 1:
 593                 base_addr = OMAP_HSMMC2_BASE;
 594                 break;
 595 #endif
 596 #ifdef OMAP_HSMMC3_BASE
 597         case 2:
 598                 base_addr = OMAP_HSMMC3_BASE;
 599                 break;
 600 #endif
 601         default:
 602                 printf("Invalid MMC device index: %d\n", dev_index);
 603                 return 1;
 604         }
 605
 606         mmc = &hsmmc_dev[dev_index];
 607         priv_data = &hsmmc_dev_data[dev_index];
 608         priv_data->base_addr = (void *)base_addr;
 609
 610         sprintf(mmc->name, "OMAP SD/MMC");
 611         mmc->send_cmd = mmc_send_cmd;
 612         mmc->set_ios = mmc_set_ios;
 613         mmc->init = mmc_init_setup;
 614         mmc->priv = priv_data;
 615
 616         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 617         if (priv_data->cd_gpio != -1)
 618                 mmc->getcd = omap_mmc_getcd;
 619
 620         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 621         if (priv_data->wp_gpio != -1)
 622                 mmc->getwp = omap_mmc_getwp;
 623
 624         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 625         mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
 626                                 MMC_MODE_HC) & ~host_caps_mask;
 627
 628         mmc->f_min = 400000;
 629
 630         if (f_max != 0)
 631                 mmc->f_max = f_max;
 632         else {
 633                 if (mmc->host_caps & MMC_MODE_HS) {
 634                         if (mmc->host_caps & MMC_MODE_HS_52MHz)
 635                                 mmc->f_max = 52000000;
 636                         else
 637                                 mmc->f_max = 26000000;
 638                 } else
 639                         mmc->f_max = 20000000;
 640         }
 641
 642         mmc->b_max = 0;
 643
 644 #if defined(CONFIG_OMAP34XX)
 645         /*
 646          * Silicon revs 2.1 and older do not support multiblock transfers.
 647          */
 648         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 649                 mmc->b_max = 1;
 650 #endif
 651
 652         mmc_register(mmc);
 653
 654         return 0;
 655 }