2 * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on ti81xx_nand.c
4 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
5 * Mansoor Ahamed <mansoor.ahamed@ti.com>
7 * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/mem.h>
33 #include <asm/arch/nand.h>
34 #include <linux/mtd/nand_ecc.h>
37 struct nand_bch_priv {
47 /* BCH nibbles for diff bch levels */
48 #define ECC_BCH4_NIBBLES 13
49 #define ECC_BCH8_NIBBLES 26
50 #define ECC_BCH16_NIBBLES 52
53 #ifndef CONFIG_SPL_BUILD
54 static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT_KERNEL;
55 static struct nand_ecclayout hw_bch4_nand_oob = GPMC_NAND_HW_BCH4_ECC_LAYOUT;
56 static struct nand_ecclayout hw_bch16_nand_oob = GPMC_NAND_HW_BCH16_ECC_LAYOUT;
58 static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
60 static struct nand_bch_priv bch_priv = {
62 .nibbles = ECC_BCH8_NIBBLES,
65 #ifndef CONFIG_SYS_NAND_NO_OOB
66 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
67 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
69 static struct nand_bbt_descr bbt_main_descr = {
70 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
71 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
76 .pattern = bbt_pattern,
79 static struct nand_bbt_descr bbt_mirror_descr = {
80 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
81 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
86 .pattern = mirror_pattern,
91 * am33xx_read_bch8_result - Read BCH result for BCH8 level
93 * @mtd: MTD device structure
94 * @big_endian: When set read register 3 first
95 * @ecc_code: Read syndrome from BCH result registers
97 static void am33xx_read_bch8_result(struct mtd_info *mtd, int big_endian,
105 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
107 ecc_code[i++] = res & 0xFF;
108 for (j = 0; j < 3; j++) {
109 u32 res = readl(--ptr);
111 ecc_code[i++] = (res >> 24) & 0xFF;
112 ecc_code[i++] = (res >> 16) & 0xFF;
113 ecc_code[i++] = (res >> 8) & 0xFF;
114 ecc_code[i++] = res & 0xFF;
117 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
118 for (j = 0; j < 3; j++) {
119 u32 res = readl(ptr++);
121 ecc_code[i++] = res & 0xFF;
122 ecc_code[i++] = (res >> 8) & 0xFF;
123 ecc_code[i++] = (res >> 16) & 0xFF;
124 ecc_code[i++] = (res >> 24) & 0xFF;
126 ecc_code[i++] = readl(ptr) & 0xFF;
132 * am33xx_ecc_disable - Disable H/W ECC calculation
134 * @mtd: MTD device structure
137 static void am33xx_ecc_disable(struct mtd_info *mtd)
139 writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
140 &gpmc_cfg->ecc_config);
144 * am33xx_nand_hwcontrol - Set the address pointers correctly for the
145 * following address/data/command operation
147 static void am33xx_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
150 register struct nand_chip *this = mtd->priv;
152 debug("nand cmd %08x ctrl %08x\n", cmd, ctrl);
154 * Point the IO_ADDR to DATA and ADDRESS registers instead
158 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
159 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
161 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
162 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
164 case NAND_CTRL_CHANGE | NAND_NCE:
165 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
168 if (cmd != NAND_CMD_NONE)
169 writeb(cmd, this->IO_ADDR_W);
173 * am33xx_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
175 * @mtd: MTD device structure
176 * @mode: Read/Write mode
178 static void am33xx_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
180 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
181 uint32_t unused_length = 0;
182 struct nand_bch_priv *bch = chip->priv;
184 switch (bch->nibbles) {
185 case ECC_BCH4_NIBBLES:
188 case ECC_BCH8_NIBBLES:
191 case ECC_BCH16_NIBBLES:
195 /* Clear the ecc result registers, select ecc reg as 1 */
196 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
200 /* eccsize1 config */
201 val = ((unused_length + bch->nibbles) << 22);
206 /* by default eccsize0 selected for ecc1resultsize */
207 /* eccsize0 config */
208 val = (bch->nibbles << 12);
209 /* eccsize1 config */
210 val |= (unused_length << 22);
212 /* ecc size configuration */
213 writel(val, &gpmc_cfg->ecc_size_config);
214 /* by default 512bytes sector page is selected */
217 /* bch4 / bch8 / bch16 */
218 val |= (bch->type << 12);
219 /* set wrap mode to 1 */
221 val |= (dev_width << 7);
224 /* val |= (1); */ /* should not enable ECC just init i.e. config */
225 writel(val, &gpmc_cfg->ecc_config);
228 #ifndef CONFIG_SPL_BUILD
230 * am33xx_hwecc_init - Initialize the Hardware ECC for NAND flash in
232 * @mtd: MTD device structure
235 static void am33xx_hwecc_init(struct nand_chip *chip)
238 * Init ECC Control Register
239 * Clear all ECC | Enable Reg1
241 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
242 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
246 * gen_true_ecc - This function will generate true ECC value, which
247 * can be used when correcting data read from NAND flash memory core
249 * @ecc_buf: buffer to store ecc code
251 * @return: re-formatted ECC value
253 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
255 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
256 ((ecc_buf[2] & 0x0F) << 8);
261 * am33xx_rotate_ecc_bch - Rotate the syndrome bytes
263 * @mtd: MTD device structure
264 * @calc_ecc: ECC read from ECC registers
265 * @syndrome: Rotated syndrome will be retuned in this array
268 static inline void am33xx_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
271 struct nand_chip *chip = mtd->priv;
272 struct nand_bch_priv *bch = chip->priv;
290 for (i = 0, j = (n_bytes - 1); i < n_bytes; i++, j--)
291 syndrome[i] = calc_ecc[j];
297 * am33xx_fix_errors_bch - Correct bch error in the data
299 * @mtd: MTD device structure
300 * @data: Data read from flash
301 * @error_count:Number of errors in data
302 * @error_loc: Locations of errors in the data
305 static void am33xx_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
306 uint32_t error_count, uint32_t *error_loc)
308 struct nand_chip *chip = mtd->priv;
309 struct nand_bch_priv *bch = chip->priv;
311 uint32_t error_byte_pos;
312 uint32_t error_bit_mask;
313 uint32_t last_bit = (bch->nibbles * 4) - 1;
315 /* Flip all bits as specified by the error location array. */
316 /* FOR( each found error location flip the bit ) */
317 for (count = 0; count < error_count; count++) {
318 if (error_loc[count] > last_bit) {
319 /* Remove the ECC spare bits from correction. */
320 error_loc[count] -= (last_bit + 1);
321 /* Offset bit in data region */
322 error_byte_pos = ((512 * 8) - (error_loc[count]) - 1) / 8;
324 error_bit_mask = 0x1 << (error_loc[count] % 8);
325 /* Toggle the error bit to make the correction. */
326 data[error_byte_pos] ^= error_bit_mask;
332 * am33xx_correct_data_bch - Compares the ecc read from nand spare area
333 * with ECC registers values and corrects one bit error if it has occured
335 * @mtd: MTD device structure
337 * @read_ecc: ecc read from nand flash (ignored)
338 * @calc_ecc: ecc read from ECC registers
340 * @return 0 if data is OK or corrected, else returns -1
342 static inline int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
343 uint8_t *buf, int page);
345 static int am33xx_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
346 uint8_t *read_ecc, uint8_t *calc_ecc)
348 struct nand_chip *chip = mtd->priv;
349 struct nand_bch_priv *bch = chip->priv;
350 uint8_t syndrome[28];
351 uint32_t error_count = 0;
352 uint32_t error_loc[8];
353 uint32_t i, ecc_flag;
356 for (i = 0; i < (chip->ecc.bytes - 1); i++)
357 if (read_ecc[i] != 0xff)
364 elm_config(bch->type);
366 /* while reading ECC result we read it in big endian.
367 * Hence while loading to ELM we have rotate to get the right endian.
369 am33xx_rotate_ecc_bch(mtd, calc_ecc, syndrome);
371 /* use elm module to check for errors */
372 if (elm_check_error(syndrome, bch->nibbles, &error_count, error_loc) != 0) {
373 printf("uncorrectable ECC error\n");
377 /* correct bch error */
378 if (error_count > 0) {
379 am33xx_fix_errors_bch(mtd, dat, error_count, error_loc);
385 #ifndef CONFIG_SPL_BUILD
387 * am33xx_correct_data - Compares the ecc read from nand spare area with ECC
388 * registers values and corrects one bit error if it has occured
389 * Further details can be had from Am33xx TRM and the following selected links:
390 * http://en.wikipedia.org/wiki/Hamming_code
391 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
393 * @mtd: MTD device structure
395 * @read_ecc: ecc read from nand flash
396 * @calc_ecc: ecc read from ECC registers
398 * @return 0 if data is OK or corrected, else returns -1
400 static int am33xx_correct_data(struct mtd_info *mtd, uint8_t *dat,
401 uint8_t *read_ecc, uint8_t *calc_ecc)
403 uint32_t orig_ecc, new_ecc, res, hm;
404 uint16_t parity_bits, byte;
407 /* Regenerate the orginal ECC */
408 orig_ecc = gen_true_ecc(read_ecc);
409 new_ecc = gen_true_ecc(calc_ecc);
410 /* Get the XOR of real ecc */
411 res = orig_ecc ^ new_ecc;
413 /* Get the hamming width */
415 /* Single bit errors can be corrected! */
417 /* Correctable data! */
418 parity_bits = res >> 16;
419 bit = (parity_bits & 0x7);
420 byte = (parity_bits >> 3) & 0x1FF;
421 /* Flip the bit to correct */
422 dat[byte] ^= (0x1 << bit);
423 } else if (hm == 1) {
424 printf("am33xx_nand: Error: Corrupted ECC\n");
425 /* ECC itself is corrupted */
429 * hm distance != parity pairs OR one, could mean 2 bit
430 * error OR potentially be on a blank page..
431 * orig_ecc: contains spare area data from nand flash.
432 * new_ecc: generated ecc while reading data area.
433 * Note: if the ecc = 0, all data bits from which it was
434 * generated are 0xFF.
435 * The 3 byte(24 bits) ecc is generated per 512byte
436 * chunk of a page. If orig_ecc(from spare area)
437 * is 0xFF && new_ecc(computed now from data area)=0x0,
438 * this means that data area is 0xFF and spare area is
439 * 0xFF. A sure sign of an erased page!
441 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
443 printf("am33xx_nand: Error: Multibit error detected; hm=%d\n",
445 /* detected 2 bit error */
454 * am33xx_calculate_ecc_bch - Read BCH ECC result
456 * @mtd: MTD structure
458 * @ecc_code: ecc_code buffer
460 static int am33xx_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
463 struct nand_chip *chip = mtd->priv;
464 struct nand_bch_priv *bch = chip->priv;
468 if (bch->type == ECC_BCH8)
469 am33xx_read_bch8_result(mtd, big_endian, ecc_code);
470 else /* BCH4 and BCH16 currently not supported */
474 * Stop reading anymore ECC vals and clear old results
475 * enable will be called if more reads are required
477 am33xx_ecc_disable(mtd);
482 #ifndef CONFIG_SPL_BUILD
484 * am33xx_calculate_ecc - Generate non-inverted ECC bytes.
486 * Using noninverted ECC can be considered ugly since writing a blank
487 * page ie. padding will clear the ECC bytes. This is no problem as
488 * long nobody is trying to write data on the seemingly unused page.
489 * Reading an erased page will produce an ECC mismatch between
490 * generated and read ECC bytes that has to be dealt with separately.
491 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
492 * is used, the result of read will be 0x0 while the ECC offsets of the
493 * spare area will be 0xFF which will result in an ECC mismatch.
494 * @mtd: MTD structure
496 * @ecc_code: ecc_code buffer
498 static int am33xx_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
503 /* Start Reading from HW ECC1_Result = 0x200 */
504 val = readl(&gpmc_cfg->ecc1_result);
506 ecc_code[0] = val & 0xFF;
507 ecc_code[1] = (val >> 16) & 0xFF;
508 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
511 * Stop reading anymore ECC vals and clear old results
512 * enable will be called if more reads are required
514 writel(0x000, &gpmc_cfg->ecc_config);
520 #ifdef CONFIG_SPL_BUILD
521 static void am33xx_spl_nand_command(struct mtd_info *mtd, unsigned int cmd,
524 struct nand_chip *chip = mtd->priv;
526 while (!chip->dev_ready(mtd))
529 /* Emulate NAND_CMD_READOOB */
530 if (cmd == NAND_CMD_READOOB) {
531 col += CONFIG_SYS_NAND_PAGE_SIZE;
532 cmd = NAND_CMD_READ0;
535 /* Shift the offset from byte addressing to word addressing. */
536 if (chip->options & NAND_BUSWIDTH_16)
539 /* Begin command latch cycle */
540 chip->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
541 /* Set ALE and clear CLE to start address cycle */
543 chip->cmd_ctrl(mtd, col & 0xff,
544 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
545 chip->cmd_ctrl(mtd, (col >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
547 chip->cmd_ctrl(mtd, page & 0xff, NAND_CTRL_ALE); /* A[19:12] */
548 chip->cmd_ctrl(mtd, (page >> 8) & 0xff,
549 NAND_CTRL_ALE); /* A[27:20] */
550 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
551 /* One more address cycle for devices > 128MiB */
552 chip->cmd_ctrl(mtd, (page >> 16) & 0x0f,
553 NAND_CTRL_ALE); /* A[31:28] */
555 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
557 /* Latch in address */
558 chip->cmd_ctrl(mtd, cmd == NAND_CMD_RNDOUT ?
559 NAND_CMD_RNDOUTSTART : NAND_CMD_READSTART,
560 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
561 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
564 * Wait a while for the data to be ready
566 while (!chip->dev_ready(mtd))
572 * am33xx_read_page_bch - hardware ecc based page read function
573 * @mtd: mtd info structure
574 * @chip: nand chip info structure
575 * @buf: buffer to store read data
576 * @page: page number to read
579 static inline int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
580 uint8_t *buf, int page)
583 int i, eccsize = chip->ecc.size;
584 int eccbytes = chip->ecc.bytes;
585 int eccsteps = chip->ecc.steps;
587 uint8_t *ecc_calc = chip->buffers->ecccalc;
588 uint8_t *ecc_code = chip->buffers->ecccode;
589 uint32_t *eccpos = chip->ecc.layout->eccpos;
590 uint8_t *oob = chip->oob_poi;
591 uint32_t data_pos = 0;
592 uint32_t oob_pos = (eccsize * eccsteps) + eccpos[0];
594 chip->cmdfunc(mtd, NAND_CMD_READ0, data_pos, page);
596 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
598 chip->ecc.hwctl(mtd, NAND_ECC_READ);
600 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
601 chip->read_buf(mtd, p, eccsize);
602 /* read respective ecc from oob area */
603 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
604 chip->read_buf(mtd, oob, eccbytes);
606 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
612 for (i = 0; i < chip->ecc.total; i++) {
613 ecc_code[i] = chip->oob_poi[i];
616 eccsteps = chip->ecc.steps;
619 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
622 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
624 printf("am33xx_nand: uncorrectable ECC error in page %5d\n",
626 mtd->ecc_stats.failed++;
629 mtd->ecc_stats.corrected += stat;
630 printf("%s: corrected ECC errors: %d\n", __func__, stat);
638 * am33xx_enable_ecc_bch- This function enables the bch h/w ecc functionality
639 * @mtd: MTD device structure
640 * @mode: Read/Write mode
643 static void am33xx_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
645 struct nand_chip *chip = mtd->priv;
647 am33xx_hwecc_init_bch(chip, mode);
649 writel(readl(&gpmc_cfg->ecc_config) | 0x1, &gpmc_cfg->ecc_config);
652 #ifndef CONFIG_SPL_BUILD
654 * am33xx_enable_ecc - This function enables the hardware ecc functionality
655 * @mtd: MTD device structure
656 * @mode: Read/Write mode
658 static void am33xx_enable_ecc(struct mtd_info *mtd, int32_t mode)
660 struct nand_chip *chip = mtd->priv;
661 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
666 /* Clear the ecc result registers, select ecc reg as 1 */
667 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
670 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
671 * tell all regs to generate size0 sized regs
672 * we just have a single ECC engine for all CS
674 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
675 &gpmc_cfg->ecc_size_config);
676 val = (dev_width << 7) | (cs << 1) | (1 << 0);
677 writel(val, &gpmc_cfg->ecc_config);
680 printf("Error: Unrecognized Mode[%d]!\n", mode);
685 * __am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc
686 * (i.e. hamming / bch) and s/w ecc.
687 * The default is to come up on s/w ecc
689 * @nand: NAND chip datastructure
690 * @hardware: NAND_ECC_HW -switch to h/w ecc
691 * NAND_ECC_SOFT -switch to s/w ecc
693 * @mode: 0 - hamming code
698 static void __am33xx_nand_switch_ecc(struct nand_chip *nand,
699 nand_ecc_modes_t hardware, int32_t mode)
701 struct nand_bch_priv *bch;
705 /* Reset ecc interface */
706 nand->ecc.read_page = NULL;
707 nand->ecc.write_page = NULL;
708 nand->ecc.read_oob = NULL;
709 nand->ecc.write_oob = NULL;
710 nand->ecc.hwctl = NULL;
711 nand->ecc.correct = NULL;
712 nand->ecc.calculate = NULL;
714 nand->ecc.mode = hardware;
715 /* Setup the ecc configurations again */
716 if (hardware == NAND_ECC_HW) {
718 /* -1 for converting mode to bch type */
719 bch->type = mode - 1;
724 nand->ecc.layout = &hw_bch4_nand_oob;
725 bch->nibbles = ECC_BCH4_NIBBLES;
726 debug("4 not supported\n");
730 nand->ecc.bytes = 26;
731 nand->ecc.layout = &hw_bch16_nand_oob;
732 bch->nibbles = ECC_BCH16_NIBBLES;
733 debug("16 not supported\n");
738 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
739 nand->ecc.layout = &hw_bch8_nand_oob;
740 bch->nibbles = ECC_BCH8_NIBBLES;
741 debug("8 Selected\n");
743 nand->ecc.mode = NAND_ECC_HW;
744 nand->ecc.size = 512;
745 nand->ecc.read_page = am33xx_read_page_bch;
746 nand->ecc.hwctl = am33xx_enable_ecc_bch;
747 nand->ecc.correct = am33xx_correct_data_bch;
748 nand->ecc.calculate = am33xx_calculate_ecc_bch;
749 am33xx_hwecc_init_bch(nand, NAND_ECC_READ);
751 nand->ecc.layout = &hw_nand_oob;
752 nand->ecc.size = 512;
754 nand->ecc.hwctl = am33xx_enable_ecc;
755 nand->ecc.correct = am33xx_correct_data;
756 nand->ecc.calculate = am33xx_calculate_ecc;
757 am33xx_hwecc_init(nand);
758 debug("HW ECC Hamming Code selected\n");
760 } else if (hardware == NAND_ECC_SOFT) {
761 /* Use mtd default settings */
762 nand->ecc.layout = NULL;
763 debug("SW ECC selected\n");
765 debug("ECC Disabled\n");
770 * am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc
771 * (i.e. hamming / bch) and s/w ecc.
772 * The default is to come up on s/w ecc
774 * @hardware - NAND_ECC_HW -switch to h/w ecc
775 * NAND_ECC_SOFT -switch to s/w ecc
777 * @mode - 0 - hamming code
782 void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode)
784 struct nand_chip *nand;
785 struct mtd_info *mtd;
787 if (nand_curr_device < 0 ||
788 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
789 printf("Error: Can't switch ecc, no devices available\n");
793 mtd = &nand_info[nand_curr_device];
796 __am33xx_nand_switch_ecc(nand, hardware, mode);
798 nand->options |= NAND_OWN_BUFFERS;
799 /* Update NAND handling after ECC mode switch */
801 nand->options &= ~NAND_OWN_BUFFERS;
804 #else /* CONFIG_SPL_BUILD */
805 /* Check wait pin as dev ready indicator */
806 static int am33xx_spl_dev_ready(struct mtd_info *mtd)
810 // printf("dev status: ");
811 ret = readl(&gpmc_cfg->status) & (1 << 8);
812 // printf("%d %08x\n", ret, gpmc_cfg->status);
818 * Board-specific NAND initialization. The following members of the
819 * argument are board-specific:
820 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
821 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
822 * - cmd_ctrl: hardwarespecific function for accesing control-lines
823 * - waitfunc: hardwarespecific function for accesing device ready/busy line
824 * - ecc.hwctl: function to enable (reset) hardware ecc generator
825 * - ecc.mode: mode of ecc, see defines
826 * - chip_delay: chip dependent delay for transfering data from array to
828 * - options: various chip options. They can partly be set to inform
829 * nand_scan about special functionality. See the defines for further
832 int board_nand_init(struct nand_chip *nand)
834 /* int32_t gpmc_config = 0; */
838 * xloader/Uboot's gpmc configuration would have configured GPMC for
839 * nand type of memory. The following logic scans and latches on to the
840 * first CS with NAND type memory.
841 * TBD: need to make this logic generic to handle multiple CS NAND
844 while (cs < GPMC_MAX_CS) {
845 /* Check if NAND type is set */
846 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
848 debug("Searching for NAND device @ GPMC CS:%d\n", cs);
853 if (cs >= GPMC_MAX_CS) {
854 printf("NAND: Unable to find NAND settings in "
855 "GPMC Configuration - quitting\n");
859 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
860 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
862 nand->cmd_ctrl = am33xx_nand_hwcontrol;
863 nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
864 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
865 #ifdef CONFIG_SYS_NAND_NO_OOB
866 nand->options |= NAND_USE_FLASH_BBT | NAND_USE_FLASH_BBT_NO_OOB;
868 nand->options |= NAND_USE_FLASH_BBT;
869 nand->bbt_td = &bbt_main_descr;
870 nand->bbt_md = &bbt_mirror_descr;
871 #endif /* CONFIG_SYS_NAND_NO_OOB */
872 #endif /* CONFIG_SYS_NAND_USE_FLASH_BBT */
874 /* If we are 16 bit dev, our gpmc config tells us that */
875 if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) {
876 nand->options |= NAND_BUSWIDTH_16;
879 nand->chip_delay = 100;
881 /* required in case of BCH */
884 /* BCH info that will be correct for SPL or overridden otherwise. */
885 nand->priv = &bch_priv;
887 bch_priv.nibbles = ECC_BCH8_NIBBLES;
888 bch_priv.type = ECC_BCH8;
889 nand->ecc.mode = NAND_ECC_HW;
890 nand->ecc.layout = &hw_bch8_nand_oob;
891 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
892 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
893 nand->ecc.hwctl = am33xx_enable_ecc_bch;
894 nand->ecc.read_page = am33xx_read_page_bch;
895 nand->ecc.correct = am33xx_correct_data_bch;
896 nand->ecc.calculate = am33xx_calculate_ecc_bch;
898 #ifndef CONFIG_SPL_BUILD
899 nand_curr_device = 0;
901 nand->cmdfunc = am33xx_spl_nand_command;
903 nand->ecc.steps = CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE;
904 nand->ecc.total = CONFIG_SYS_NAND_ECCBYTES * nand->ecc.steps;
906 if (nand->options & NAND_BUSWIDTH_16)
907 nand->read_buf = nand_read_buf16;
909 nand->read_buf = nand_read_buf;
911 nand->dev_ready = am33xx_spl_dev_ready;
912 #endif /* CONFIG_SPL_BUILD */
913 am33xx_hwecc_init_bch(nand, NAND_ECC_READ);