a2016e7945d0f06a6c33bc9703e2bdb33665d998
[karo-tx-uboot.git] / drivers / mtd / nand / atmel_nand.c
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
7  *
8  * Add Programmable Multibit ECC support for various AT91 SoC
9  *     (C) Copyright 2012 ATMEL, Hong Xu
10  *
11  * SPDX-License-Identifier:     GPL-2.0+
12  */
13
14 #include <common.h>
15 #include <asm/gpio.h>
16 #include <asm/arch/gpio.h>
17
18 #include <malloc.h>
19 #include <nand.h>
20 #include <watchdog.h>
21 #include <linux/mtd/nand_ecc.h>
22
23 #ifdef CONFIG_ATMEL_NAND_HWECC
24
25 /* Register access macros */
26 #define ecc_readl(add, reg)                             \
27         readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
28 #define ecc_writel(add, reg, value)                     \
29         writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
30
31 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
32
33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
34
35 #ifdef CONFIG_SPL_BUILD
36 #undef CONFIG_SYS_NAND_ONFI_DETECTION
37 #endif
38
39 struct atmel_nand_host {
40         struct pmecc_regs __iomem *pmecc;
41         struct pmecc_errloc_regs __iomem *pmerrloc;
42         void __iomem            *pmecc_rom_base;
43
44         u8              pmecc_corr_cap;
45         u16             pmecc_sector_size;
46         u32             pmecc_index_table_offset;
47         u32             pmecc_version;
48
49         int             pmecc_bytes_per_sector;
50         int             pmecc_sector_number;
51         int             pmecc_degree;   /* Degree of remainders */
52         int             pmecc_cw_len;   /* Length of codeword */
53
54         /* lookup table for alpha_to and index_of */
55         void __iomem    *pmecc_alpha_to;
56         void __iomem    *pmecc_index_of;
57
58         /* data for pmecc computation */
59         int16_t *pmecc_smu;
60         int16_t *pmecc_partial_syn;
61         int16_t *pmecc_si;
62         int16_t *pmecc_lmu; /* polynomal order */
63         int     *pmecc_mu;
64         int     *pmecc_dmu;
65         int     *pmecc_delta;
66 };
67
68 static struct atmel_nand_host pmecc_host;
69 static struct nand_ecclayout atmel_pmecc_oobinfo;
70
71 /*
72  * Return number of ecc bytes per sector according to sector size and
73  * correction capability
74  *
75  * Following table shows what at91 PMECC supported:
76  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
77  * =====================        ================        =================
78  *                2-bits                 4-bytes                  4-bytes
79  *                4-bits                 7-bytes                  7-bytes
80  *                8-bits                13-bytes                 14-bytes
81  *               12-bits                20-bytes                 21-bytes
82  *               24-bits                39-bytes                 42-bytes
83  */
84 static int pmecc_get_ecc_bytes(int cap, int sector_size)
85 {
86         int m = 12 + sector_size / 512;
87         return (m * cap + 7) / 8;
88 }
89
90 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
91         int oobsize, int ecc_len)
92 {
93         int i;
94
95         layout->eccbytes = ecc_len;
96
97         /* ECC will occupy the last ecc_len bytes continuously */
98         for (i = 0; i < ecc_len; i++)
99                 layout->eccpos[i] = oobsize - ecc_len + i;
100
101         layout->oobfree[0].offset = 2;
102         layout->oobfree[0].length =
103                 oobsize - ecc_len - layout->oobfree[0].offset;
104 }
105
106 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
107 {
108         int table_size;
109
110         table_size = host->pmecc_sector_size == 512 ?
111                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
112
113         /* the ALPHA lookup table is right behind the INDEX lookup table. */
114         return host->pmecc_rom_base + host->pmecc_index_table_offset +
115                         table_size * sizeof(int16_t);
116 }
117
118 static void pmecc_data_free(struct atmel_nand_host *host)
119 {
120         free(host->pmecc_partial_syn);
121         free(host->pmecc_si);
122         free(host->pmecc_lmu);
123         free(host->pmecc_smu);
124         free(host->pmecc_mu);
125         free(host->pmecc_dmu);
126         free(host->pmecc_delta);
127 }
128
129 static int pmecc_data_alloc(struct atmel_nand_host *host)
130 {
131         const int cap = host->pmecc_corr_cap;
132         int size;
133
134         size = (2 * cap + 1) * sizeof(int16_t);
135         host->pmecc_partial_syn = malloc(size);
136         host->pmecc_si = malloc(size);
137         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
138         host->pmecc_smu = malloc((cap + 2) * size);
139
140         size = (cap + 1) * sizeof(int);
141         host->pmecc_mu = malloc(size);
142         host->pmecc_dmu = malloc(size);
143         host->pmecc_delta = malloc(size);
144
145         if (host->pmecc_partial_syn &&
146                         host->pmecc_si &&
147                         host->pmecc_lmu &&
148                         host->pmecc_smu &&
149                         host->pmecc_mu &&
150                         host->pmecc_dmu &&
151                         host->pmecc_delta)
152                 return 0;
153
154         /* error happened */
155         pmecc_data_free(host);
156         return -ENOMEM;
157
158 }
159
160 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
161 {
162         struct nand_chip *nand_chip = mtd->priv;
163         struct atmel_nand_host *host = nand_chip->priv;
164         int i;
165         uint32_t value;
166
167         /* Fill odd syndromes */
168         for (i = 0; i < host->pmecc_corr_cap; i++) {
169                 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
170                 if (i & 1)
171                         value >>= 16;
172                 value &= 0xffff;
173                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
174         }
175 }
176
177 static void pmecc_substitute(struct mtd_info *mtd)
178 {
179         struct nand_chip *nand_chip = mtd->priv;
180         struct atmel_nand_host *host = nand_chip->priv;
181         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
182         int16_t __iomem *index_of = host->pmecc_index_of;
183         int16_t *partial_syn = host->pmecc_partial_syn;
184         const int cap = host->pmecc_corr_cap;
185         int16_t *si;
186         int i, j;
187
188         /* si[] is a table that holds the current syndrome value,
189          * an element of that table belongs to the field
190          */
191         si = host->pmecc_si;
192
193         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
194
195         /* Computation 2t syndromes based on S(x) */
196         /* Odd syndromes */
197         for (i = 1; i < 2 * cap; i += 2) {
198                 for (j = 0; j < host->pmecc_degree; j++) {
199                         if (partial_syn[i] & (0x1 << j))
200                                 si[i] = readw(alpha_to + i * j) ^ si[i];
201                 }
202         }
203         /* Even syndrome = (Odd syndrome) ** 2 */
204         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
205                 if (si[j] == 0) {
206                         si[i] = 0;
207                 } else {
208                         int16_t tmp;
209
210                         tmp = readw(index_of + si[j]);
211                         tmp = (tmp * 2) % host->pmecc_cw_len;
212                         si[i] = readw(alpha_to + tmp);
213                 }
214         }
215 }
216
217 /*
218  * This function defines a Berlekamp iterative procedure for
219  * finding the value of the error location polynomial.
220  * The input is si[], initialize by pmecc_substitute().
221  * The output is smu[][].
222  *
223  * This function is written according to chip datasheet Chapter:
224  * Find the Error Location Polynomial Sigma(x) of Section:
225  * Programmable Multibit ECC Control (PMECC).
226  */
227 static void pmecc_get_sigma(struct mtd_info *mtd)
228 {
229         struct nand_chip *nand_chip = mtd->priv;
230         struct atmel_nand_host *host = nand_chip->priv;
231
232         int16_t *lmu = host->pmecc_lmu;
233         int16_t *si = host->pmecc_si;
234         int *mu = host->pmecc_mu;
235         int *dmu = host->pmecc_dmu;     /* Discrepancy */
236         int *delta = host->pmecc_delta; /* Delta order */
237         int cw_len = host->pmecc_cw_len;
238         const int16_t cap = host->pmecc_corr_cap;
239         const int num = 2 * cap + 1;
240         int16_t __iomem *index_of = host->pmecc_index_of;
241         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
242         int i, j, k;
243         uint32_t dmu_0_count, tmp;
244         int16_t *smu = host->pmecc_smu;
245
246         /* index of largest delta */
247         int ro;
248         int largest;
249         int diff;
250
251         /* Init the Sigma(x) */
252         memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
253
254         dmu_0_count = 0;
255
256         /* First Row */
257
258         /* Mu */
259         mu[0] = -1;
260
261         smu[0] = 1;
262
263         /* discrepancy set to 1 */
264         dmu[0] = 1;
265         /* polynom order set to 0 */
266         lmu[0] = 0;
267         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
268         delta[0] = -1;
269
270         /* Second Row */
271
272         /* Mu */
273         mu[1] = 0;
274         /* Sigma(x) set to 1 */
275         smu[num] = 1;
276
277         /* discrepancy set to S1 */
278         dmu[1] = si[1];
279
280         /* polynom order set to 0 */
281         lmu[1] = 0;
282
283         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
284         delta[1] = 0;
285
286         for (i = 1; i <= cap; i++) {
287                 mu[i + 1] = i << 1;
288                 /* Begin Computing Sigma (Mu+1) and L(mu) */
289                 /* check if discrepancy is set to 0 */
290                 if (dmu[i] == 0) {
291                         dmu_0_count++;
292
293                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
294                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
295                                 tmp += 2;
296                         else
297                                 tmp += 1;
298
299                         if (dmu_0_count == tmp) {
300                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
301                                         smu[(cap + 1) * num + j] =
302                                                         smu[i * num + j];
303
304                                 lmu[cap + 1] = lmu[i];
305                                 return;
306                         }
307
308                         /* copy polynom */
309                         for (j = 0; j <= lmu[i] >> 1; j++)
310                                 smu[(i + 1) * num + j] = smu[i * num + j];
311
312                         /* copy previous polynom order to the next */
313                         lmu[i + 1] = lmu[i];
314                 } else {
315                         ro = 0;
316                         largest = -1;
317                         /* find largest delta with dmu != 0 */
318                         for (j = 0; j < i; j++) {
319                                 if ((dmu[j]) && (delta[j] > largest)) {
320                                         largest = delta[j];
321                                         ro = j;
322                                 }
323                         }
324
325                         /* compute difference */
326                         diff = (mu[i] - mu[ro]);
327
328                         /* Compute degree of the new smu polynomial */
329                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
330                                 lmu[i + 1] = lmu[i];
331                         else
332                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
333
334                         /* Init smu[i+1] with 0 */
335                         for (k = 0; k < num; k++)
336                                 smu[(i + 1) * num + k] = 0;
337
338                         /* Compute smu[i+1] */
339                         for (k = 0; k <= lmu[ro] >> 1; k++) {
340                                 int16_t a, b, c;
341
342                                 if (!(smu[ro * num + k] && dmu[i]))
343                                         continue;
344                                 a = readw(index_of + dmu[i]);
345                                 b = readw(index_of + dmu[ro]);
346                                 c = readw(index_of + smu[ro * num + k]);
347                                 tmp = a + (cw_len - b) + c;
348                                 a = readw(alpha_to + tmp % cw_len);
349                                 smu[(i + 1) * num + (k + diff)] = a;
350                         }
351
352                         for (k = 0; k <= lmu[i] >> 1; k++)
353                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
354                 }
355
356                 /* End Computing Sigma (Mu+1) and L(mu) */
357                 /* In either case compute delta */
358                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
359
360                 /* Do not compute discrepancy for the last iteration */
361                 if (i >= cap)
362                         continue;
363
364                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
365                         tmp = 2 * (i - 1);
366                         if (k == 0) {
367                                 dmu[i + 1] = si[tmp + 3];
368                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
369                                 int16_t a, b, c;
370                                 a = readw(index_of +
371                                                 smu[(i + 1) * num + k]);
372                                 b = si[2 * (i - 1) + 3 - k];
373                                 c = readw(index_of + b);
374                                 tmp = a + c;
375                                 tmp %= cw_len;
376                                 dmu[i + 1] = readw(alpha_to + tmp) ^
377                                         dmu[i + 1];
378                         }
379                 }
380         }
381 }
382
383 static int pmecc_err_location(struct mtd_info *mtd)
384 {
385         struct nand_chip *nand_chip = mtd->priv;
386         struct atmel_nand_host *host = nand_chip->priv;
387         const int cap = host->pmecc_corr_cap;
388         const int num = 2 * cap + 1;
389         int sector_size = host->pmecc_sector_size;
390         int err_nbr = 0;        /* number of error */
391         int roots_nbr;          /* number of roots */
392         int i;
393         uint32_t val;
394         int16_t *smu = host->pmecc_smu;
395         int timeout = PMECC_MAX_TIMEOUT_US;
396
397         pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
398
399         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
400                 pmecc_writel(host->pmerrloc, sigma[i],
401                              smu[(cap + 1) * num + i]);
402                 err_nbr++;
403         }
404
405         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
406         if (sector_size == 1024)
407                 val |= PMERRLOC_ELCFG_SECTOR_1024;
408
409         pmecc_writel(host->pmerrloc, elcfg, val);
410         pmecc_writel(host->pmerrloc, elen,
411                      sector_size * 8 + host->pmecc_degree * cap);
412
413         while (--timeout) {
414                 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
415                         break;
416                 WATCHDOG_RESET();
417                 udelay(1);
418         }
419
420         if (!timeout) {
421                 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
422                 return -1;
423         }
424
425         roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
426                         >> 8;
427         /* Number of roots == degree of smu hence <= cap */
428         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
429                 return err_nbr - 1;
430
431         /* Number of roots does not match the degree of smu
432          * unable to correct error */
433         return -1;
434 }
435
436 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
437                 int sector_num, int extra_bytes, int err_nbr)
438 {
439         struct nand_chip *nand_chip = mtd->priv;
440         struct atmel_nand_host *host = nand_chip->priv;
441         int i = 0;
442         int byte_pos, bit_pos, sector_size, pos;
443         uint32_t tmp;
444         uint8_t err_byte;
445
446         sector_size = host->pmecc_sector_size;
447
448         while (err_nbr) {
449                 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
450                 byte_pos = tmp / 8;
451                 bit_pos  = tmp % 8;
452
453                 if (byte_pos >= (sector_size + extra_bytes))
454                         BUG();  /* should never happen */
455
456                 if (byte_pos < sector_size) {
457                         err_byte = *(buf + byte_pos);
458                         *(buf + byte_pos) ^= (1 << bit_pos);
459
460                         pos = sector_num * host->pmecc_sector_size + byte_pos;
461                         dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
462                                 pos, bit_pos, err_byte, *(buf + byte_pos));
463                 } else {
464                         /* Bit flip in OOB area */
465                         tmp = sector_num * host->pmecc_bytes_per_sector
466                                         + (byte_pos - sector_size);
467                         err_byte = ecc[tmp];
468                         ecc[tmp] ^= (1 << bit_pos);
469
470                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
471                         dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
472                                 pos, bit_pos, err_byte, ecc[tmp]);
473                 }
474
475                 i++;
476                 err_nbr--;
477         }
478
479         return;
480 }
481
482 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
483         u8 *ecc)
484 {
485         struct nand_chip *nand_chip = mtd->priv;
486         struct atmel_nand_host *host = nand_chip->priv;
487         int i, err_nbr, eccbytes;
488         uint8_t *buf_pos;
489
490         /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
491         if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
492                 goto normal_check;
493
494         eccbytes = nand_chip->ecc.bytes;
495         for (i = 0; i < eccbytes; i++)
496                 if (ecc[i] != 0xff)
497                         goto normal_check;
498         /* Erased page, return OK */
499         return 0;
500
501 normal_check:
502         for (i = 0; i < host->pmecc_sector_number; i++) {
503                 err_nbr = 0;
504                 if (pmecc_stat & 0x1) {
505                         buf_pos = buf + i * host->pmecc_sector_size;
506
507                         pmecc_gen_syndrome(mtd, i);
508                         pmecc_substitute(mtd);
509                         pmecc_get_sigma(mtd);
510
511                         err_nbr = pmecc_err_location(mtd);
512                         if (err_nbr == -1) {
513                                 dev_err(host->dev, "PMECC: Too many errors\n");
514                                 mtd->ecc_stats.failed++;
515                                 return -EIO;
516                         } else {
517                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
518                                         host->pmecc_bytes_per_sector, err_nbr);
519                                 mtd->ecc_stats.corrected += err_nbr;
520                         }
521                 }
522                 pmecc_stat >>= 1;
523         }
524
525         return 0;
526 }
527
528 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
529         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
530 {
531         struct atmel_nand_host *host = chip->priv;
532         int eccsize = chip->ecc.size;
533         uint8_t *oob = chip->oob_poi;
534         uint32_t *eccpos = chip->ecc.layout->eccpos;
535         uint32_t stat;
536         int timeout = PMECC_MAX_TIMEOUT_US;
537
538         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
539         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
540         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
541                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
542
543         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
544         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
545
546         chip->read_buf(mtd, buf, eccsize);
547         chip->read_buf(mtd, oob, mtd->oobsize);
548
549         while (--timeout) {
550                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
551                         break;
552                 WATCHDOG_RESET();
553                 udelay(1);
554         }
555
556         if (!timeout) {
557                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
558                 return -1;
559         }
560
561         stat = pmecc_readl(host->pmecc, isr);
562         if (stat != 0)
563                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
564                         return -EIO;
565
566         return 0;
567 }
568
569 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
570                 struct nand_chip *chip, const uint8_t *buf,
571                 int oob_required)
572 {
573         struct atmel_nand_host *host = chip->priv;
574         uint32_t *eccpos = chip->ecc.layout->eccpos;
575         int i, j;
576         int timeout = PMECC_MAX_TIMEOUT_US;
577
578         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
579         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
580
581         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
582                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
583
584         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
585         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
586
587         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
588
589         while (--timeout) {
590                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
591                         break;
592                 WATCHDOG_RESET();
593                 udelay(1);
594         }
595
596         if (!timeout) {
597                 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
598                 goto out;
599         }
600
601         for (i = 0; i < host->pmecc_sector_number; i++) {
602                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
603                         int pos;
604
605                         pos = i * host->pmecc_bytes_per_sector + j;
606                         chip->oob_poi[eccpos[pos]] =
607                                 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
608                 }
609         }
610         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
611 out:
612         return 0;
613 }
614
615 static void atmel_pmecc_core_init(struct mtd_info *mtd)
616 {
617         struct nand_chip *nand_chip = mtd->priv;
618         struct atmel_nand_host *host = nand_chip->priv;
619         uint32_t val = 0;
620         struct nand_ecclayout *ecc_layout;
621
622         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
623         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
624
625         switch (host->pmecc_corr_cap) {
626         case 2:
627                 val = PMECC_CFG_BCH_ERR2;
628                 break;
629         case 4:
630                 val = PMECC_CFG_BCH_ERR4;
631                 break;
632         case 8:
633                 val = PMECC_CFG_BCH_ERR8;
634                 break;
635         case 12:
636                 val = PMECC_CFG_BCH_ERR12;
637                 break;
638         case 24:
639                 val = PMECC_CFG_BCH_ERR24;
640                 break;
641         }
642
643         if (host->pmecc_sector_size == 512)
644                 val |= PMECC_CFG_SECTOR512;
645         else if (host->pmecc_sector_size == 1024)
646                 val |= PMECC_CFG_SECTOR1024;
647
648         switch (host->pmecc_sector_number) {
649         case 1:
650                 val |= PMECC_CFG_PAGE_1SECTOR;
651                 break;
652         case 2:
653                 val |= PMECC_CFG_PAGE_2SECTORS;
654                 break;
655         case 4:
656                 val |= PMECC_CFG_PAGE_4SECTORS;
657                 break;
658         case 8:
659                 val |= PMECC_CFG_PAGE_8SECTORS;
660                 break;
661         }
662
663         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
664                 | PMECC_CFG_AUTO_DISABLE);
665         pmecc_writel(host->pmecc, cfg, val);
666
667         ecc_layout = nand_chip->ecc.layout;
668         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
669         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
670         pmecc_writel(host->pmecc, eaddr,
671                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
672         /* See datasheet about PMECC Clock Control Register */
673         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
674         pmecc_writel(host->pmecc, idr, 0xff);
675         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
676 }
677
678 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
679 /*
680  * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
681  * @ecc_bits: store the ONFI ECC correct bits capbility
682  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
683  *
684  * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
685  * @sector_size are initialize to 0.
686  * Return 0 if success to get the ECC requirement.
687  */
688 static int get_onfi_ecc_param(struct nand_chip *chip,
689                 int *ecc_bits, int *sector_size)
690 {
691         *ecc_bits = *sector_size = 0;
692
693         if (chip->onfi_params.ecc_bits == 0xff)
694                 /* TODO: the sector_size and ecc_bits need to be find in
695                  * extended ecc parameter, currently we don't support it.
696                  */
697                 return -1;
698
699         *ecc_bits = chip->onfi_params.ecc_bits;
700
701         /* The default sector size (ecc codeword size) is 512 */
702         *sector_size = 512;
703
704         return 0;
705 }
706
707 /*
708  * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
709  *                    pmecc_corr_cap or pmecc_sector_size is 0, then set it as
710  *                    ONFI ECC parameters.
711  * @host: point to an atmel_nand_host structure.
712  *        if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
713  *        if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
714  * @chip: point to an nand_chip structure.
715  * @cap: store the ONFI ECC correct bits capbility
716  * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
717  *
718  * Return 0 if success. otherwise return the error code.
719  */
720 static int pmecc_choose_ecc(struct atmel_nand_host *host,
721                 struct nand_chip *chip,
722                 int *cap, int *sector_size)
723 {
724         /* Get ECC requirement from ONFI parameters */
725         *cap = *sector_size = 0;
726         if (chip->onfi_version) {
727                 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
728                         MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
729                                 *cap, *sector_size);
730                 } else {
731                         dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
732                 }
733         } else {
734                 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
735         }
736         if (*cap == 0 && *sector_size == 0) {
737                 /* Non-ONFI compliant or use extended ONFI parameters */
738                 *cap = 2;
739                 *sector_size = 512;
740         }
741
742         /* If head file doesn't specify then use the one in ONFI parameters */
743         if (host->pmecc_corr_cap == 0) {
744                 /* use the most fitable ecc bits (the near bigger one ) */
745                 if (*cap <= 2)
746                         host->pmecc_corr_cap = 2;
747                 else if (*cap <= 4)
748                         host->pmecc_corr_cap = 4;
749                 else if (*cap <= 8)
750                         host->pmecc_corr_cap = 8;
751                 else if (*cap <= 12)
752                         host->pmecc_corr_cap = 12;
753                 else if (*cap <= 24)
754                         host->pmecc_corr_cap = 24;
755                 else
756                         return -EINVAL;
757         }
758         if (host->pmecc_sector_size == 0) {
759                 /* use the most fitable sector size (the near smaller one ) */
760                 if (*sector_size >= 1024)
761                         host->pmecc_sector_size = 1024;
762                 else if (*sector_size >= 512)
763                         host->pmecc_sector_size = 512;
764                 else
765                         return -EINVAL;
766         }
767         return 0;
768 }
769 #endif
770
771 #if defined(NO_GALOIS_TABLE_IN_ROM)
772 static uint16_t *pmecc_galois_table;
773 static inline int deg(unsigned int poly)
774 {
775         /* polynomial degree is the most-significant bit index */
776         return fls(poly) - 1;
777 }
778
779 static int build_gf_tables(int mm, unsigned int poly,
780                            int16_t *index_of, int16_t *alpha_to)
781 {
782         unsigned int i, x = 1;
783         const unsigned int k = 1 << deg(poly);
784         unsigned int nn = (1 << mm) - 1;
785
786         /* primitive polynomial must be of degree m */
787         if (k != (1u << mm))
788                 return -EINVAL;
789
790         for (i = 0; i < nn; i++) {
791                 alpha_to[i] = x;
792                 index_of[x] = i;
793                 if (i && (x == 1))
794                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
795                         return -EINVAL;
796                 x <<= 1;
797                 if (x & k)
798                         x ^= poly;
799         }
800
801         alpha_to[nn] = 1;
802         index_of[0] = 0;
803
804         return 0;
805 }
806
807 static uint16_t *create_lookup_table(int sector_size)
808 {
809         int degree = (sector_size == 512) ?
810                         PMECC_GF_DIMENSION_13 :
811                         PMECC_GF_DIMENSION_14;
812         unsigned int poly = (sector_size == 512) ?
813                         PMECC_GF_13_PRIMITIVE_POLY :
814                         PMECC_GF_14_PRIMITIVE_POLY;
815         int table_size = (sector_size == 512) ?
816                         PMECC_INDEX_TABLE_SIZE_512 :
817                         PMECC_INDEX_TABLE_SIZE_1024;
818
819         int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
820         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
821                 return NULL;
822
823         return (uint16_t *)addr;
824 }
825 #endif
826
827 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
828                 struct mtd_info *mtd)
829 {
830         struct atmel_nand_host *host;
831         int cap, sector_size;
832
833         host = nand->priv = &pmecc_host;
834
835         nand->ecc.mode = NAND_ECC_HW;
836         nand->ecc.calculate = NULL;
837         nand->ecc.correct = NULL;
838         nand->ecc.hwctl = NULL;
839
840 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
841         host->pmecc_corr_cap = host->pmecc_sector_size = 0;
842
843 #ifdef CONFIG_PMECC_CAP
844         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
845 #endif
846 #ifdef CONFIG_PMECC_SECTOR_SIZE
847         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
848 #endif
849         /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
850          * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
851          * from ONFI.
852          */
853         if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
854                 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
855                                 cap, sector_size);
856                 return -EINVAL;
857         }
858
859         if (cap > host->pmecc_corr_cap)
860                 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
861                                 host->pmecc_corr_cap, cap);
862         if (sector_size < host->pmecc_sector_size)
863                 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
864                                 host->pmecc_sector_size, sector_size);
865 #else   /* CONFIG_SYS_NAND_ONFI_DETECTION */
866         host->pmecc_corr_cap = CONFIG_PMECC_CAP;
867         host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
868 #endif
869
870         cap = host->pmecc_corr_cap;
871         sector_size = host->pmecc_sector_size;
872
873         /* TODO: need check whether cap & sector_size is validate */
874 #if defined(NO_GALOIS_TABLE_IN_ROM)
875         /*
876          * As pmecc_rom_base is the begin of the gallois field table, So the
877          * index offset just set as 0.
878          */
879         host->pmecc_index_table_offset = 0;
880 #else
881         if (host->pmecc_sector_size == 512)
882                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
883         else
884                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
885 #endif
886
887         MTDDEBUG(MTD_DEBUG_LEVEL1,
888                 "Initialize PMECC params, cap: %d, sector: %d\n",
889                 cap, sector_size);
890
891         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
892         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
893                         ATMEL_BASE_PMERRLOC;
894 #if defined(NO_GALOIS_TABLE_IN_ROM)
895         pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
896         if (!pmecc_galois_table) {
897                 dev_err(host->dev, "out of memory\n");
898                 return -ENOMEM;
899         }
900
901         host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
902 #else
903         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
904 #endif
905
906         /* ECC is calculated for the whole page (1 step) */
907         nand->ecc.size = mtd->writesize;
908
909         /* set ECC page size and oob layout */
910         switch (mtd->writesize) {
911         case 2048:
912         case 4096:
913         case 8192:
914                 host->pmecc_degree = (sector_size == 512) ?
915                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
916                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
917                 host->pmecc_sector_number = mtd->writesize / sector_size;
918                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
919                         cap, sector_size);
920                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
921                 host->pmecc_index_of = host->pmecc_rom_base +
922                         host->pmecc_index_table_offset;
923
924                 nand->ecc.steps = 1;
925                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
926                                        host->pmecc_sector_number;
927
928                 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
929                         dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
930                                         MTD_MAX_ECCPOS_ENTRIES_LARGE);
931                         return -EINVAL;
932                 }
933
934                 if (nand->ecc.bytes > mtd->oobsize - 2) {
935                         dev_err(host->dev, "No room for ECC bytes\n");
936                         return -EINVAL;
937                 }
938                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
939                                         mtd->oobsize,
940                                         nand->ecc.bytes);
941                 nand->ecc.layout = &atmel_pmecc_oobinfo;
942                 break;
943         case 512:
944         case 1024:
945                 /* TODO */
946                 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
947         default:
948                 /* page size not handled by HW ECC */
949                 /* switching back to soft ECC */
950                 nand->ecc.mode = NAND_ECC_SOFT;
951                 nand->ecc.read_page = NULL;
952                 nand->ecc.postpad = 0;
953                 nand->ecc.prepad = 0;
954                 nand->ecc.bytes = 0;
955                 return 0;
956         }
957
958         /* Allocate data for PMECC computation */
959         if (pmecc_data_alloc(host)) {
960                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
961                 return -ENOMEM;
962         }
963
964         nand->options |= NAND_NO_SUBPAGE_WRITE;
965         nand->ecc.read_page = atmel_nand_pmecc_read_page;
966         nand->ecc.write_page = atmel_nand_pmecc_write_page;
967         nand->ecc.strength = cap;
968
969         /* Check the PMECC ip version */
970         host->pmecc_version = pmecc_readl(host->pmerrloc, version);
971         dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
972
973         atmel_pmecc_core_init(mtd);
974
975         return 0;
976 }
977
978 #else
979
980 /* oob layout for large page size
981  * bad block info is on bytes 0 and 1
982  * the bytes have to be consecutives to avoid
983  * several NAND_CMD_RNDOUT during read
984  */
985 static struct nand_ecclayout atmel_oobinfo_large = {
986         .eccbytes = 4,
987         .eccpos = {60, 61, 62, 63},
988         .oobfree = {
989                 {2, 58}
990         },
991 };
992
993 /* oob layout for small page size
994  * bad block info is on bytes 4 and 5
995  * the bytes have to be consecutives to avoid
996  * several NAND_CMD_RNDOUT during read
997  */
998 static struct nand_ecclayout atmel_oobinfo_small = {
999         .eccbytes = 4,
1000         .eccpos = {0, 1, 2, 3},
1001         .oobfree = {
1002                 {6, 10}
1003         },
1004 };
1005
1006 /*
1007  * Calculate HW ECC
1008  *
1009  * function called after a write
1010  *
1011  * mtd:        MTD block structure
1012  * dat:        raw data (unused)
1013  * ecc_code:   buffer for ECC
1014  */
1015 static int atmel_nand_calculate(struct mtd_info *mtd,
1016                 const u_char *dat, unsigned char *ecc_code)
1017 {
1018         unsigned int ecc_value;
1019
1020         /* get the first 2 ECC bytes */
1021         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1022
1023         ecc_code[0] = ecc_value & 0xFF;
1024         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1025
1026         /* get the last 2 ECC bytes */
1027         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1028
1029         ecc_code[2] = ecc_value & 0xFF;
1030         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1031
1032         return 0;
1033 }
1034
1035 /*
1036  * HW ECC read page function
1037  *
1038  * mtd:        mtd info structure
1039  * chip:       nand chip info structure
1040  * buf:        buffer to store read data
1041  * oob_required:    caller expects OOB data read to chip->oob_poi
1042  */
1043 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1044                                 uint8_t *buf, int oob_required, int page)
1045 {
1046         int eccsize = chip->ecc.size;
1047         int eccbytes = chip->ecc.bytes;
1048         uint32_t *eccpos = chip->ecc.layout->eccpos;
1049         uint8_t *p = buf;
1050         uint8_t *oob = chip->oob_poi;
1051         uint8_t *ecc_pos;
1052         int stat;
1053
1054         /* read the page */
1055         chip->read_buf(mtd, p, eccsize);
1056
1057         /* move to ECC position if needed */
1058         if (eccpos[0] != 0) {
1059                 /* This only works on large pages
1060                  * because the ECC controller waits for
1061                  * NAND_CMD_RNDOUTSTART after the
1062                  * NAND_CMD_RNDOUT.
1063                  * anyway, for small pages, the eccpos[0] == 0
1064                  */
1065                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1066                                 mtd->writesize + eccpos[0], -1);
1067         }
1068
1069         /* the ECC controller needs to read the ECC just after the data */
1070         ecc_pos = oob + eccpos[0];
1071         chip->read_buf(mtd, ecc_pos, eccbytes);
1072
1073         /* check if there's an error */
1074         stat = chip->ecc.correct(mtd, p, oob, NULL);
1075
1076         if (stat < 0)
1077                 mtd->ecc_stats.failed++;
1078         else
1079                 mtd->ecc_stats.corrected += stat;
1080
1081         /* get back to oob start (end of page) */
1082         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1083
1084         /* read the oob */
1085         chip->read_buf(mtd, oob, mtd->oobsize);
1086
1087         return 0;
1088 }
1089
1090 /*
1091  * HW ECC Correction
1092  *
1093  * function called after a read
1094  *
1095  * mtd:        MTD block structure
1096  * dat:        raw data read from the chip
1097  * read_ecc:   ECC from the chip (unused)
1098  * isnull:     unused
1099  *
1100  * Detect and correct a 1 bit error for a page
1101  */
1102 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1103                 u_char *read_ecc, u_char *isnull)
1104 {
1105         struct nand_chip *nand_chip = mtd->priv;
1106         unsigned int ecc_status;
1107         unsigned int ecc_word, ecc_bit;
1108
1109         /* get the status from the Status Register */
1110         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1111
1112         /* if there's no error */
1113         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1114                 return 0;
1115
1116         /* get error bit offset (4 bits) */
1117         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1118         /* get word address (12 bits) */
1119         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1120         ecc_word >>= 4;
1121
1122         /* if there are multiple errors */
1123         if (ecc_status & ATMEL_ECC_MULERR) {
1124                 /* check if it is a freshly erased block
1125                  * (filled with 0xff) */
1126                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1127                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1128                         /* the block has just been erased, return OK */
1129                         return 0;
1130                 }
1131                 /* it doesn't seems to be a freshly
1132                  * erased block.
1133                  * We can't correct so many errors */
1134                 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1135                                 " Unable to correct.\n");
1136                 return -EIO;
1137         }
1138
1139         /* if there's a single bit error : we can correct it */
1140         if (ecc_status & ATMEL_ECC_ECCERR) {
1141                 /* there's nothing much to do here.
1142                  * the bit error is on the ECC itself.
1143                  */
1144                 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1145                                 " Nothing to correct\n");
1146                 return 0;
1147         }
1148
1149         dev_warn(host->dev, "atmel_nand : one bit error on data."
1150                         " (word offset in the page :"
1151                         " 0x%x bit offset : 0x%x)\n",
1152                         ecc_word, ecc_bit);
1153         /* correct the error */
1154         if (nand_chip->options & NAND_BUSWIDTH_16) {
1155                 /* 16 bits words */
1156                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1157         } else {
1158                 /* 8 bits words */
1159                 dat[ecc_word] ^= (1 << ecc_bit);
1160         }
1161         dev_warn(host->dev, "atmel_nand : error corrected\n");
1162         return 1;
1163 }
1164
1165 /*
1166  * Enable HW ECC : unused on most chips
1167  */
1168 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1169 {
1170 }
1171
1172 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1173 {
1174         nand->ecc.mode = NAND_ECC_HW;
1175         nand->ecc.calculate = atmel_nand_calculate;
1176         nand->ecc.correct = atmel_nand_correct;
1177         nand->ecc.hwctl = atmel_nand_hwctl;
1178         nand->ecc.read_page = atmel_nand_read_page;
1179         nand->ecc.bytes = 4;
1180
1181         if (nand->ecc.mode == NAND_ECC_HW) {
1182                 /* ECC is calculated for the whole page (1 step) */
1183                 nand->ecc.size = mtd->writesize;
1184
1185                 /* set ECC page size and oob layout */
1186                 switch (mtd->writesize) {
1187                 case 512:
1188                         nand->ecc.layout = &atmel_oobinfo_small;
1189                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1190                                         ATMEL_ECC_PAGESIZE_528);
1191                         break;
1192                 case 1024:
1193                         nand->ecc.layout = &atmel_oobinfo_large;
1194                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1195                                         ATMEL_ECC_PAGESIZE_1056);
1196                         break;
1197                 case 2048:
1198                         nand->ecc.layout = &atmel_oobinfo_large;
1199                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1200                                         ATMEL_ECC_PAGESIZE_2112);
1201                         break;
1202                 case 4096:
1203                         nand->ecc.layout = &atmel_oobinfo_large;
1204                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1205                                         ATMEL_ECC_PAGESIZE_4224);
1206                         break;
1207                 default:
1208                         /* page size not handled by HW ECC */
1209                         /* switching back to soft ECC */
1210                         nand->ecc.mode = NAND_ECC_SOFT;
1211                         nand->ecc.calculate = NULL;
1212                         nand->ecc.correct = NULL;
1213                         nand->ecc.hwctl = NULL;
1214                         nand->ecc.read_page = NULL;
1215                         nand->ecc.postpad = 0;
1216                         nand->ecc.prepad = 0;
1217                         nand->ecc.bytes = 0;
1218                         break;
1219                 }
1220         }
1221
1222         return 0;
1223 }
1224
1225 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1226
1227 #endif /* CONFIG_ATMEL_NAND_HWECC */
1228
1229 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1230                                          int cmd, unsigned int ctrl)
1231 {
1232         struct nand_chip *this = mtd->priv;
1233
1234         if (ctrl & NAND_CTRL_CHANGE) {
1235                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1236                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1237                              | CONFIG_SYS_NAND_MASK_CLE);
1238
1239                 if (ctrl & NAND_CLE)
1240                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1241                 if (ctrl & NAND_ALE)
1242                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1243
1244 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1245                 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
1246 #endif
1247                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1248         }
1249
1250         if (cmd != NAND_CMD_NONE)
1251                 writeb(cmd, this->IO_ADDR_W);
1252 }
1253
1254 #ifdef CONFIG_SYS_NAND_READY_PIN
1255 static int at91_nand_ready(struct mtd_info *mtd)
1256 {
1257         return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1258 }
1259 #endif
1260
1261 #ifdef CONFIG_SPL_BUILD
1262 /* The following code is for SPL */
1263 static nand_info_t mtd;
1264 static struct nand_chip nand_chip;
1265
1266 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1267 {
1268         struct nand_chip *this = mtd.priv;
1269         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1270         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1271                         unsigned int ctrl) = this->cmd_ctrl;
1272
1273         while (!this->dev_ready(&mtd))
1274                 ;
1275
1276         if (cmd == NAND_CMD_READOOB) {
1277                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1278                 cmd = NAND_CMD_READ0;
1279         }
1280
1281         hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1282
1283         if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1284                 offs >>= 1;
1285
1286         hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1287         hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1288         hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1289         hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1290 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1291         hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1292 #endif
1293         hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1294
1295         hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1296         hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1297
1298         while (!this->dev_ready(&mtd))
1299                 ;
1300
1301         return 0;
1302 }
1303
1304 static int nand_is_bad_block(int block)
1305 {
1306         struct nand_chip *this = mtd.priv;
1307
1308         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1309
1310         if (this->options & NAND_BUSWIDTH_16) {
1311                 if (readw(this->IO_ADDR_R) != 0xffff)
1312                         return 1;
1313         } else {
1314                 if (readb(this->IO_ADDR_R) != 0xff)
1315                         return 1;
1316         }
1317
1318         return 0;
1319 }
1320
1321 #ifdef CONFIG_SPL_NAND_ECC
1322 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1323 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1324                   CONFIG_SYS_NAND_ECCSIZE)
1325 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1326
1327 static int nand_read_page(int block, int page, void *dst)
1328 {
1329         struct nand_chip *this = mtd.priv;
1330         u_char ecc_calc[ECCTOTAL];
1331         u_char ecc_code[ECCTOTAL];
1332         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1333         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1334         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1335         int eccsteps = ECCSTEPS;
1336         int i;
1337         uint8_t *p = dst;
1338         nand_command(block, page, 0, NAND_CMD_READ0);
1339
1340         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1341                 if (this->ecc.mode != NAND_ECC_SOFT)
1342                         this->ecc.hwctl(&mtd, NAND_ECC_READ);
1343                 this->read_buf(&mtd, p, eccsize);
1344                 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
1345         }
1346         this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1347
1348         for (i = 0; i < ECCTOTAL; i++)
1349                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1350
1351         eccsteps = ECCSTEPS;
1352         p = dst;
1353
1354         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1355                 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
1356
1357         return 0;
1358 }
1359
1360 int spl_nand_erase_one(int block, int page)
1361 {
1362         struct nand_chip *this = mtd.priv;
1363         void (*hwctrl)(struct mtd_info *mtd, int cmd,
1364                         unsigned int ctrl) = this->cmd_ctrl;
1365         int page_addr;
1366
1367         if (nand_chip.select_chip)
1368                 nand_chip.select_chip(&mtd, 0);
1369
1370         page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1371         hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1372         /* Row address */
1373         hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1374         hwctrl(&mtd, ((page_addr >> 8) & 0xff),
1375                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1376 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1377         /* One more address cycle for devices > 128MiB */
1378         hwctrl(&mtd, (page_addr >> 16) & 0x0f,
1379                NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1380 #endif
1381
1382         hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1383         udelay(2000);
1384
1385         while (!this->dev_ready(&mtd))
1386                 ;
1387
1388         nand_deselect();
1389
1390         return 0;
1391 }
1392 #else
1393 static int nand_read_page(int block, int page, void *dst)
1394 {
1395         struct nand_chip *this = mtd.priv;
1396
1397         nand_command(block, page, 0, NAND_CMD_READ0);
1398         atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
1399
1400         return 0;
1401 }
1402 #endif /* CONFIG_SPL_NAND_ECC */
1403
1404 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
1405 {
1406         unsigned int block, lastblock;
1407         unsigned int page;
1408
1409         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
1410         lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
1411         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
1412
1413         while (block <= lastblock) {
1414                 if (!nand_is_bad_block(block)) {
1415                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
1416                                 nand_read_page(block, page, dst);
1417                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
1418                                 page++;
1419                         }
1420
1421                         page = 0;
1422                 } else {
1423                         lastblock++;
1424                 }
1425
1426                 block++;
1427         }
1428
1429         return 0;
1430 }
1431
1432 int at91_nand_wait_ready(struct mtd_info *mtd)
1433 {
1434         struct nand_chip *this = mtd->priv;
1435
1436         udelay(this->chip_delay);
1437
1438         return 1;
1439 }
1440
1441 int board_nand_init(struct nand_chip *nand)
1442 {
1443         int ret = 0;
1444
1445         nand->ecc.mode = NAND_ECC_SOFT;
1446 #ifdef CONFIG_SYS_NAND_DBW_16
1447         nand->options = NAND_BUSWIDTH_16;
1448         nand->read_buf = nand_read_buf16;
1449 #else
1450         nand->read_buf = nand_read_buf;
1451 #endif
1452         nand->cmd_ctrl = at91_nand_hwcontrol;
1453 #ifdef CONFIG_SYS_NAND_READY_PIN
1454         nand->dev_ready = at91_nand_ready;
1455 #else
1456         nand->dev_ready = at91_nand_wait_ready;
1457 #endif
1458         nand->chip_delay = 20;
1459 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1460         nand->bbt_options |= NAND_BBT_USE_FLASH;
1461 #endif
1462
1463 #ifdef CONFIG_ATMEL_NAND_HWECC
1464 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1465         ret = atmel_pmecc_nand_init_params(nand, &mtd);
1466 #endif
1467 #endif
1468
1469         return ret;
1470 }
1471
1472 void nand_init(void)
1473 {
1474         mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1475         mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
1476         mtd.priv = &nand_chip;
1477         nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1478         nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1479         board_nand_init(&nand_chip);
1480
1481 #ifdef CONFIG_SPL_NAND_ECC
1482         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1483                 nand_chip.ecc.calculate = nand_calculate_ecc;
1484                 nand_chip.ecc.correct = nand_correct_data;
1485         }
1486 #endif
1487
1488         if (nand_chip.select_chip)
1489                 nand_chip.select_chip(&mtd, 0);
1490 }
1491
1492 void nand_deselect(void)
1493 {
1494         if (nand_chip.select_chip)
1495                 nand_chip.select_chip(&mtd, -1);
1496 }
1497
1498 #else
1499
1500 #ifndef CONFIG_SYS_NAND_BASE_LIST
1501 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1502 #endif
1503 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1504 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1505
1506 int atmel_nand_chip_init(int devnum, ulong base_addr)
1507 {
1508         int ret;
1509         struct mtd_info *mtd = &nand_info[devnum];
1510         struct nand_chip *nand = &nand_chip[devnum];
1511
1512         mtd->priv = nand;
1513         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1514
1515 #ifdef CONFIG_NAND_ECC_BCH
1516         nand->ecc.mode = NAND_ECC_SOFT_BCH;
1517 #else
1518         nand->ecc.mode = NAND_ECC_SOFT;
1519 #endif
1520 #ifdef CONFIG_SYS_NAND_DBW_16
1521         nand->options = NAND_BUSWIDTH_16;
1522 #endif
1523         nand->cmd_ctrl = at91_nand_hwcontrol;
1524 #ifdef CONFIG_SYS_NAND_READY_PIN
1525         nand->dev_ready = at91_nand_ready;
1526 #endif
1527         nand->chip_delay = 75;
1528 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1529         nand->bbt_options |= NAND_BBT_USE_FLASH;
1530 #endif
1531
1532         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1533         if (ret)
1534                 return ret;
1535
1536 #ifdef CONFIG_ATMEL_NAND_HWECC
1537 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1538         ret = atmel_pmecc_nand_init_params(nand, mtd);
1539 #else
1540         ret = atmel_hwecc_nand_init_param(nand, mtd);
1541 #endif
1542         if (ret)
1543                 return ret;
1544 #endif
1545
1546         ret = nand_scan_tail(mtd);
1547         if (!ret)
1548                 nand_register(devnum);
1549
1550         return ret;
1551 }
1552
1553 void board_nand_init(void)
1554 {
1555         int i;
1556         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1557                 if (atmel_nand_chip_init(i, base_addr[i]))
1558                         dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1559                                 i);
1560 }
1561 #endif /* CONFIG_SPL_BUILD */