drivers/mtd/nand/atmel_nand.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
   7  *
   8  * Add Programmable Multibit ECC support for various AT91 SoC
   9  *     (C) Copyright 2012 ATMEL, Hong Xu
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/at91_pio.h>
  18
  19 #include <malloc.h>
  20 #include <nand.h>
  21 #include <watchdog.h>
  22
  23 #ifdef CONFIG_ATMEL_NAND_HWECC
  24
  25 /* Register access macros */
  26 #define ecc_readl(add, reg)                             \
  27         readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
  28 #define ecc_writel(add, reg, value)                     \
  29         writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
  30
  31 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  32
  33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  34
  35 struct atmel_nand_host {
  36         struct pmecc_regs __iomem *pmecc;
  37         struct pmecc_errloc_regs __iomem *pmerrloc;
  38         void __iomem            *pmecc_rom_base;
  39
  40         u8              pmecc_corr_cap;
  41         u16             pmecc_sector_size;
  42         u32             pmecc_index_table_offset;
  43
  44         int             pmecc_bytes_per_sector;
  45         int             pmecc_sector_number;
  46         int             pmecc_degree;   /* Degree of remainders */
  47         int             pmecc_cw_len;   /* Length of codeword */
  48
  49         /* lookup table for alpha_to and index_of */
  50         void __iomem    *pmecc_alpha_to;
  51         void __iomem    *pmecc_index_of;
  52
  53         /* data for pmecc computation */
  54         int16_t *pmecc_smu;
  55         int16_t *pmecc_partial_syn;
  56         int16_t *pmecc_si;
  57         int16_t *pmecc_lmu; /* polynomal order */
  58         int     *pmecc_mu;
  59         int     *pmecc_dmu;
  60         int     *pmecc_delta;
  61 };
  62
  63 static struct atmel_nand_host pmecc_host;
  64 static struct nand_ecclayout atmel_pmecc_oobinfo;
  65
  66 /*
  67  * Return number of ecc bytes per sector according to sector size and
  68  * correction capability
  69  *
  70  * Following table shows what at91 PMECC supported:
  71  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
  72  * =====================        ================        =================
  73  *                2-bits                 4-bytes                  4-bytes
  74  *                4-bits                 7-bytes                  7-bytes
  75  *                8-bits                13-bytes                 14-bytes
  76  *               12-bits                20-bytes                 21-bytes
  77  *               24-bits                39-bytes                 42-bytes
  78  */
  79 static int pmecc_get_ecc_bytes(int cap, int sector_size)
  80 {
  81         int m = 12 + sector_size / 512;
  82         return (m * cap + 7) / 8;
  83 }
  84
  85 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  86         int oobsize, int ecc_len)
  87 {
  88         int i;
  89
  90         layout->eccbytes = ecc_len;
  91
  92         /* ECC will occupy the last ecc_len bytes continuously */
  93         for (i = 0; i < ecc_len; i++)
  94                 layout->eccpos[i] = oobsize - ecc_len + i;
  95
  96         layout->oobfree[0].offset = 2;
  97         layout->oobfree[0].length =
  98                 oobsize - ecc_len - layout->oobfree[0].offset;
  99 }
 100
 101 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 102 {
 103         int table_size;
 104
 105         table_size = host->pmecc_sector_size == 512 ?
 106                 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
 107
 108         /* the ALPHA lookup table is right behind the INDEX lookup table. */
 109         return host->pmecc_rom_base + host->pmecc_index_table_offset +
 110                         table_size * sizeof(int16_t);
 111 }
 112
 113 static void pmecc_data_free(struct atmel_nand_host *host)
 114 {
 115         free(host->pmecc_partial_syn);
 116         free(host->pmecc_si);
 117         free(host->pmecc_lmu);
 118         free(host->pmecc_smu);
 119         free(host->pmecc_mu);
 120         free(host->pmecc_dmu);
 121         free(host->pmecc_delta);
 122 }
 123
 124 static int pmecc_data_alloc(struct atmel_nand_host *host)
 125 {
 126         const int cap = host->pmecc_corr_cap;
 127         int size;
 128
 129         size = (2 * cap + 1) * sizeof(int16_t);
 130         host->pmecc_partial_syn = malloc(size);
 131         host->pmecc_si = malloc(size);
 132         host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
 133         host->pmecc_smu = malloc((cap + 2) * size);
 134
 135         size = (cap + 1) * sizeof(int);
 136         host->pmecc_mu = malloc(size);
 137         host->pmecc_dmu = malloc(size);
 138         host->pmecc_delta = malloc(size);
 139
 140         if (host->pmecc_partial_syn &&
 141                         host->pmecc_si &&
 142                         host->pmecc_lmu &&
 143                         host->pmecc_smu &&
 144                         host->pmecc_mu &&
 145                         host->pmecc_dmu &&
 146                         host->pmecc_delta)
 147                 return 0;
 148
 149         /* error happened */
 150         pmecc_data_free(host);
 151         return -ENOMEM;
 152
 153 }
 154
 155 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 156 {
 157         struct nand_chip *nand_chip = mtd->priv;
 158         struct atmel_nand_host *host = nand_chip->priv;
 159         int i;
 160         uint32_t value;
 161
 162         /* Fill odd syndromes */
 163         for (i = 0; i < host->pmecc_corr_cap; i++) {
 164                 value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
 165                 if (i & 1)
 166                         value >>= 16;
 167                 value &= 0xffff;
 168                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 169         }
 170 }
 171
 172 static void pmecc_substitute(struct mtd_info *mtd)
 173 {
 174         struct nand_chip *nand_chip = mtd->priv;
 175         struct atmel_nand_host *host = nand_chip->priv;
 176         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 177         int16_t __iomem *index_of = host->pmecc_index_of;
 178         int16_t *partial_syn = host->pmecc_partial_syn;
 179         const int cap = host->pmecc_corr_cap;
 180         int16_t *si;
 181         int i, j;
 182
 183         /* si[] is a table that holds the current syndrome value,
 184          * an element of that table belongs to the field
 185          */
 186         si = host->pmecc_si;
 187
 188         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 189
 190         /* Computation 2t syndromes based on S(x) */
 191         /* Odd syndromes */
 192         for (i = 1; i < 2 * cap; i += 2) {
 193                 for (j = 0; j < host->pmecc_degree; j++) {
 194                         if (partial_syn[i] & (0x1 << j))
 195                                 si[i] = readw(alpha_to + i * j) ^ si[i];
 196                 }
 197         }
 198         /* Even syndrome = (Odd syndrome) ** 2 */
 199         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 200                 if (si[j] == 0) {
 201                         si[i] = 0;
 202                 } else {
 203                         int16_t tmp;
 204
 205                         tmp = readw(index_of + si[j]);
 206                         tmp = (tmp * 2) % host->pmecc_cw_len;
 207                         si[i] = readw(alpha_to + tmp);
 208                 }
 209         }
 210 }
 211
 212 /*
 213  * This function defines a Berlekamp iterative procedure for
 214  * finding the value of the error location polynomial.
 215  * The input is si[], initialize by pmecc_substitute().
 216  * The output is smu[][].
 217  *
 218  * This function is written according to chip datasheet Chapter:
 219  * Find the Error Location Polynomial Sigma(x) of Section:
 220  * Programmable Multibit ECC Control (PMECC).
 221  */
 222 static void pmecc_get_sigma(struct mtd_info *mtd)
 223 {
 224         struct nand_chip *nand_chip = mtd->priv;
 225         struct atmel_nand_host *host = nand_chip->priv;
 226
 227         int16_t *lmu = host->pmecc_lmu;
 228         int16_t *si = host->pmecc_si;
 229         int *mu = host->pmecc_mu;
 230         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 231         int *delta = host->pmecc_delta; /* Delta order */
 232         int cw_len = host->pmecc_cw_len;
 233         const int16_t cap = host->pmecc_corr_cap;
 234         const int num = 2 * cap + 1;
 235         int16_t __iomem *index_of = host->pmecc_index_of;
 236         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 237         int i, j, k;
 238         uint32_t dmu_0_count, tmp;
 239         int16_t *smu = host->pmecc_smu;
 240
 241         /* index of largest delta */
 242         int ro;
 243         int largest;
 244         int diff;
 245
 246         /* Init the Sigma(x) */
 247         memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
 248
 249         dmu_0_count = 0;
 250
 251         /* First Row */
 252
 253         /* Mu */
 254         mu[0] = -1;
 255
 256         smu[0] = 1;
 257
 258         /* discrepancy set to 1 */
 259         dmu[0] = 1;
 260         /* polynom order set to 0 */
 261         lmu[0] = 0;
 262         /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
 263         delta[0] = -1;
 264
 265         /* Second Row */
 266
 267         /* Mu */
 268         mu[1] = 0;
 269         /* Sigma(x) set to 1 */
 270         smu[num] = 1;
 271
 272         /* discrepancy set to S1 */
 273         dmu[1] = si[1];
 274
 275         /* polynom order set to 0 */
 276         lmu[1] = 0;
 277
 278         /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
 279         delta[1] = 0;
 280
 281         for (i = 1; i <= cap; i++) {
 282                 mu[i + 1] = i << 1;
 283                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 284                 /* check if discrepancy is set to 0 */
 285                 if (dmu[i] == 0) {
 286                         dmu_0_count++;
 287
 288                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 289                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 290                                 tmp += 2;
 291                         else
 292                                 tmp += 1;
 293
 294                         if (dmu_0_count == tmp) {
 295                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 296                                         smu[(cap + 1) * num + j] =
 297                                                         smu[i * num + j];
 298
 299                                 lmu[cap + 1] = lmu[i];
 300                                 return;
 301                         }
 302
 303                         /* copy polynom */
 304                         for (j = 0; j <= lmu[i] >> 1; j++)
 305                                 smu[(i + 1) * num + j] = smu[i * num + j];
 306
 307                         /* copy previous polynom order to the next */
 308                         lmu[i + 1] = lmu[i];
 309                 } else {
 310                         ro = 0;
 311                         largest = -1;
 312                         /* find largest delta with dmu != 0 */
 313                         for (j = 0; j < i; j++) {
 314                                 if ((dmu[j]) && (delta[j] > largest)) {
 315                                         largest = delta[j];
 316                                         ro = j;
 317                                 }
 318                         }
 319
 320                         /* compute difference */
 321                         diff = (mu[i] - mu[ro]);
 322
 323                         /* Compute degree of the new smu polynomial */
 324                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 325                                 lmu[i + 1] = lmu[i];
 326                         else
 327                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 328
 329                         /* Init smu[i+1] with 0 */
 330                         for (k = 0; k < num; k++)
 331                                 smu[(i + 1) * num + k] = 0;
 332
 333                         /* Compute smu[i+1] */
 334                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 335                                 int16_t a, b, c;
 336
 337                                 if (!(smu[ro * num + k] && dmu[i]))
 338                                         continue;
 339                                 a = readw(index_of + dmu[i]);
 340                                 b = readw(index_of + dmu[ro]);
 341                                 c = readw(index_of + smu[ro * num + k]);
 342                                 tmp = a + (cw_len - b) + c;
 343                                 a = readw(alpha_to + tmp % cw_len);
 344                                 smu[(i + 1) * num + (k + diff)] = a;
 345                         }
 346
 347                         for (k = 0; k <= lmu[i] >> 1; k++)
 348                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 349                 }
 350
 351                 /* End Computing Sigma (Mu+1) and L(mu) */
 352                 /* In either case compute delta */
 353                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 354
 355                 /* Do not compute discrepancy for the last iteration */
 356                 if (i >= cap)
 357                         continue;
 358
 359                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 360                         tmp = 2 * (i - 1);
 361                         if (k == 0) {
 362                                 dmu[i + 1] = si[tmp + 3];
 363                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 364                                 int16_t a, b, c;
 365                                 a = readw(index_of +
 366                                                 smu[(i + 1) * num + k]);
 367                                 b = si[2 * (i - 1) + 3 - k];
 368                                 c = readw(index_of + b);
 369                                 tmp = a + c;
 370                                 tmp %= cw_len;
 371                                 dmu[i + 1] = readw(alpha_to + tmp) ^
 372                                         dmu[i + 1];
 373                         }
 374                 }
 375         }
 376 }
 377
 378 static int pmecc_err_location(struct mtd_info *mtd)
 379 {
 380         struct nand_chip *nand_chip = mtd->priv;
 381         struct atmel_nand_host *host = nand_chip->priv;
 382         const int cap = host->pmecc_corr_cap;
 383         const int num = 2 * cap + 1;
 384         int sector_size = host->pmecc_sector_size;
 385         int err_nbr = 0;        /* number of error */
 386         int roots_nbr;          /* number of roots */
 387         int i;
 388         uint32_t val;
 389         int16_t *smu = host->pmecc_smu;
 390         int timeout = PMECC_MAX_TIMEOUT_US;
 391
 392         writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
 393
 394         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 395                 writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
 396                 err_nbr++;
 397         }
 398
 399         val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
 400         if (sector_size == 1024)
 401                 val |= PMERRLOC_ELCFG_SECTOR_1024;
 402
 403         writel(val, &host->pmerrloc->elcfg);
 404         writel(sector_size * 8 + host->pmecc_degree * cap,
 405                         &host->pmerrloc->elen);
 406
 407         while (--timeout) {
 408                 if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
 409                         break;
 410                 WATCHDOG_RESET();
 411                 udelay(1);
 412         }
 413
 414         if (!timeout) {
 415                 printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
 416                 return -1;
 417         }
 418
 419         roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
 420                         >> 8;
 421         /* Number of roots == degree of smu hence <= cap */
 422         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 423                 return err_nbr - 1;
 424
 425         /* Number of roots does not match the degree of smu
 426          * unable to correct error */
 427         return -1;
 428 }
 429
 430 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 431                 int sector_num, int extra_bytes, int err_nbr)
 432 {
 433         struct nand_chip *nand_chip = mtd->priv;
 434         struct atmel_nand_host *host = nand_chip->priv;
 435         int i = 0;
 436         int byte_pos, bit_pos, sector_size, pos;
 437         uint32_t tmp;
 438         uint8_t err_byte;
 439
 440         sector_size = host->pmecc_sector_size;
 441
 442         while (err_nbr) {
 443                 tmp = readl(&host->pmerrloc->el[i]) - 1;
 444                 byte_pos = tmp / 8;
 445                 bit_pos  = tmp % 8;
 446
 447                 if (byte_pos >= (sector_size + extra_bytes))
 448                         BUG();  /* should never happen */
 449
 450                 if (byte_pos < sector_size) {
 451                         err_byte = *(buf + byte_pos);
 452                         *(buf + byte_pos) ^= (1 << bit_pos);
 453
 454                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 455                         printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 456                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 457                 } else {
 458                         /* Bit flip in OOB area */
 459                         tmp = sector_num * host->pmecc_bytes_per_sector
 460                                         + (byte_pos - sector_size);
 461                         err_byte = ecc[tmp];
 462                         ecc[tmp] ^= (1 << bit_pos);
 463
 464                         pos = tmp + nand_chip->ecc.layout->eccpos[0];
 465                         printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 466                                 pos, bit_pos, err_byte, ecc[tmp]);
 467                 }
 468
 469                 i++;
 470                 err_nbr--;
 471         }
 472
 473         return;
 474 }
 475
 476 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 477         u8 *ecc)
 478 {
 479         struct nand_chip *nand_chip = mtd->priv;
 480         struct atmel_nand_host *host = nand_chip->priv;
 481         int i, err_nbr, eccbytes;
 482         uint8_t *buf_pos;
 483
 484         eccbytes = nand_chip->ecc.bytes;
 485         for (i = 0; i < eccbytes; i++)
 486                 if (ecc[i] != 0xff)
 487                         goto normal_check;
 488         /* Erased page, return OK */
 489         return 0;
 490
 491 normal_check:
 492         for (i = 0; i < host->pmecc_sector_number; i++) {
 493                 err_nbr = 0;
 494                 if (pmecc_stat & 0x1) {
 495                         buf_pos = buf + i * host->pmecc_sector_size;
 496
 497                         pmecc_gen_syndrome(mtd, i);
 498                         pmecc_substitute(mtd);
 499                         pmecc_get_sigma(mtd);
 500
 501                         err_nbr = pmecc_err_location(mtd);
 502                         if (err_nbr == -1) {
 503                                 printk(KERN_ERR "PMECC: Too many errors\n");
 504                                 mtd->ecc_stats.failed++;
 505                                 return -EIO;
 506                         } else {
 507                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 508                                         host->pmecc_bytes_per_sector, err_nbr);
 509                                 mtd->ecc_stats.corrected += err_nbr;
 510                         }
 511                 }
 512                 pmecc_stat >>= 1;
 513         }
 514
 515         return 0;
 516 }
 517
 518 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 519         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 520 {
 521         struct atmel_nand_host *host = chip->priv;
 522         int eccsize = chip->ecc.size;
 523         uint8_t *oob = chip->oob_poi;
 524         uint32_t *eccpos = chip->ecc.layout->eccpos;
 525         uint32_t stat;
 526         int timeout = PMECC_MAX_TIMEOUT_US;
 527
 528         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 529         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 530         pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
 531                 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
 532
 533         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 534         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 535
 536         chip->read_buf(mtd, buf, eccsize);
 537         chip->read_buf(mtd, oob, mtd->oobsize);
 538
 539         while (--timeout) {
 540                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 541                         break;
 542                 WATCHDOG_RESET();
 543                 udelay(1);
 544         }
 545
 546         if (!timeout) {
 547                 printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
 548                 return -1;
 549         }
 550
 551         stat = pmecc_readl(host->pmecc, isr);
 552         if (stat != 0)
 553                 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
 554                         return -EIO;
 555
 556         return 0;
 557 }
 558
 559 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 560                 struct nand_chip *chip, const uint8_t *buf,
 561                 int oob_required)
 562 {
 563         struct atmel_nand_host *host = chip->priv;
 564         uint32_t *eccpos = chip->ecc.layout->eccpos;
 565         int i, j;
 566         int timeout = PMECC_MAX_TIMEOUT_US;
 567
 568         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 569         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 570
 571         pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
 572                 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
 573
 574         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 575         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
 576
 577         chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 578
 579         while (--timeout) {
 580                 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
 581                         break;
 582                 WATCHDOG_RESET();
 583                 udelay(1);
 584         }
 585
 586         if (!timeout) {
 587                 printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
 588                 goto out;
 589         }
 590
 591         for (i = 0; i < host->pmecc_sector_number; i++) {
 592                 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
 593                         int pos;
 594
 595                         pos = i * host->pmecc_bytes_per_sector + j;
 596                         chip->oob_poi[eccpos[pos]] =
 597                                 readb(&host->pmecc->ecc_port[i].ecc[j]);
 598                 }
 599         }
 600         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 601 out:
 602         return 0;
 603 }
 604
 605 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 606 {
 607         struct nand_chip *nand_chip = mtd->priv;
 608         struct atmel_nand_host *host = nand_chip->priv;
 609         uint32_t val = 0;
 610         struct nand_ecclayout *ecc_layout;
 611
 612         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
 613         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
 614
 615         switch (host->pmecc_corr_cap) {
 616         case 2:
 617                 val = PMECC_CFG_BCH_ERR2;
 618                 break;
 619         case 4:
 620                 val = PMECC_CFG_BCH_ERR4;
 621                 break;
 622         case 8:
 623                 val = PMECC_CFG_BCH_ERR8;
 624                 break;
 625         case 12:
 626                 val = PMECC_CFG_BCH_ERR12;
 627                 break;
 628         case 24:
 629                 val = PMECC_CFG_BCH_ERR24;
 630                 break;
 631         }
 632
 633         if (host->pmecc_sector_size == 512)
 634                 val |= PMECC_CFG_SECTOR512;
 635         else if (host->pmecc_sector_size == 1024)
 636                 val |= PMECC_CFG_SECTOR1024;
 637
 638         switch (host->pmecc_sector_number) {
 639         case 1:
 640                 val |= PMECC_CFG_PAGE_1SECTOR;
 641                 break;
 642         case 2:
 643                 val |= PMECC_CFG_PAGE_2SECTORS;
 644                 break;
 645         case 4:
 646                 val |= PMECC_CFG_PAGE_4SECTORS;
 647                 break;
 648         case 8:
 649                 val |= PMECC_CFG_PAGE_8SECTORS;
 650                 break;
 651         }
 652
 653         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
 654                 | PMECC_CFG_AUTO_DISABLE);
 655         pmecc_writel(host->pmecc, cfg, val);
 656
 657         ecc_layout = nand_chip->ecc.layout;
 658         pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
 659         pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
 660         pmecc_writel(host->pmecc, eaddr,
 661                         ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
 662         /* See datasheet about PMECC Clock Control Register */
 663         pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
 664         pmecc_writel(host->pmecc, idr, 0xff);
 665         pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
 666 }
 667
 668 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 669                 struct mtd_info *mtd)
 670 {
 671         struct atmel_nand_host *host;
 672         int cap, sector_size;
 673
 674         host = nand->priv = &pmecc_host;
 675
 676         nand->ecc.mode = NAND_ECC_HW;
 677         nand->ecc.calculate = NULL;
 678         nand->ecc.correct = NULL;
 679         nand->ecc.hwctl = NULL;
 680
 681         cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP;
 682         sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
 683         if (host->pmecc_sector_size == 512)
 684                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 685         else
 686                 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
 687
 688         MTDDEBUG(MTD_DEBUG_LEVEL1,
 689                 "Initialize PMECC params, cap: %d, sector: %d\n",
 690                 cap, sector_size);
 691
 692         host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 693         host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 694                         ATMEL_BASE_PMERRLOC;
 695         host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
 696
 697         /* ECC is calculated for the whole page (1 step) */
 698         nand->ecc.size = mtd->writesize;
 699
 700         /* set ECC page size and oob layout */
 701         switch (mtd->writesize) {
 702         case 2048:
 703         case 4096:
 704                 host->pmecc_degree = PMECC_GF_DIMENSION_13;
 705                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
 706                 host->pmecc_sector_number = mtd->writesize / sector_size;
 707                 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
 708                         cap, sector_size);
 709                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
 710                 host->pmecc_index_of = host->pmecc_rom_base +
 711                         host->pmecc_index_table_offset;
 712
 713                 nand->ecc.steps = 1;
 714                 nand->ecc.bytes = host->pmecc_bytes_per_sector *
 715                                        host->pmecc_sector_number;
 716                 if (nand->ecc.bytes > mtd->oobsize - 2) {
 717                         printk(KERN_ERR "No room for ECC bytes\n");
 718                         return -EINVAL;
 719                 }
 720                 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
 721                                         mtd->oobsize,
 722                                         nand->ecc.bytes);
 723                 nand->ecc.layout = &atmel_pmecc_oobinfo;
 724                 break;
 725         case 512:
 726         case 1024:
 727                 /* TODO */
 728                 printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
 729         default:
 730                 /* page size not handled by HW ECC */
 731                 /* switching back to soft ECC */
 732                 nand->ecc.mode = NAND_ECC_SOFT;
 733                 nand->ecc.read_page = NULL;
 734                 nand->ecc.postpad = 0;
 735                 nand->ecc.prepad = 0;
 736                 nand->ecc.bytes = 0;
 737                 return 0;
 738         }
 739
 740         /* Allocate data for PMECC computation */
 741         if (pmecc_data_alloc(host)) {
 742                 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
 743                 return -ENOMEM;
 744         }
 745
 746         nand->ecc.read_page = atmel_nand_pmecc_read_page;
 747         nand->ecc.write_page = atmel_nand_pmecc_write_page;
 748         nand->ecc.strength = cap;
 749
 750         atmel_pmecc_core_init(mtd);
 751
 752         return 0;
 753 }
 754
 755 #else
 756
 757 /* oob layout for large page size
 758  * bad block info is on bytes 0 and 1
 759  * the bytes have to be consecutives to avoid
 760  * several NAND_CMD_RNDOUT during read
 761  */
 762 static struct nand_ecclayout atmel_oobinfo_large = {
 763         .eccbytes = 4,
 764         .eccpos = {60, 61, 62, 63},
 765         .oobfree = {
 766                 {2, 58}
 767         },
 768 };
 769
 770 /* oob layout for small page size
 771  * bad block info is on bytes 4 and 5
 772  * the bytes have to be consecutives to avoid
 773  * several NAND_CMD_RNDOUT during read
 774  */
 775 static struct nand_ecclayout atmel_oobinfo_small = {
 776         .eccbytes = 4,
 777         .eccpos = {0, 1, 2, 3},
 778         .oobfree = {
 779                 {6, 10}
 780         },
 781 };
 782
 783 /*
 784  * Calculate HW ECC
 785  *
 786  * function called after a write
 787  *
 788  * mtd:        MTD block structure
 789  * dat:        raw data (unused)
 790  * ecc_code:   buffer for ECC
 791  */
 792 static int atmel_nand_calculate(struct mtd_info *mtd,
 793                 const u_char *dat, unsigned char *ecc_code)
 794 {
 795         unsigned int ecc_value;
 796
 797         /* get the first 2 ECC bytes */
 798         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
 799
 800         ecc_code[0] = ecc_value & 0xFF;
 801         ecc_code[1] = (ecc_value >> 8) & 0xFF;
 802
 803         /* get the last 2 ECC bytes */
 804         ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
 805
 806         ecc_code[2] = ecc_value & 0xFF;
 807         ecc_code[3] = (ecc_value >> 8) & 0xFF;
 808
 809         return 0;
 810 }
 811
 812 /*
 813  * HW ECC read page function
 814  *
 815  * mtd:        mtd info structure
 816  * chip:       nand chip info structure
 817  * buf:        buffer to store read data
 818  * oob_required:    caller expects OOB data read to chip->oob_poi
 819  */
 820 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 821                                 uint8_t *buf, int oob_required, int page)
 822 {
 823         int eccsize = chip->ecc.size;
 824         int eccbytes = chip->ecc.bytes;
 825         uint32_t *eccpos = chip->ecc.layout->eccpos;
 826         uint8_t *p = buf;
 827         uint8_t *oob = chip->oob_poi;
 828         uint8_t *ecc_pos;
 829         int stat;
 830
 831         /* read the page */
 832         chip->read_buf(mtd, p, eccsize);
 833
 834         /* move to ECC position if needed */
 835         if (eccpos[0] != 0) {
 836                 /* This only works on large pages
 837                  * because the ECC controller waits for
 838                  * NAND_CMD_RNDOUTSTART after the
 839                  * NAND_CMD_RNDOUT.
 840                  * anyway, for small pages, the eccpos[0] == 0
 841                  */
 842                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
 843                                 mtd->writesize + eccpos[0], -1);
 844         }
 845
 846         /* the ECC controller needs to read the ECC just after the data */
 847         ecc_pos = oob + eccpos[0];
 848         chip->read_buf(mtd, ecc_pos, eccbytes);
 849
 850         /* check if there's an error */
 851         stat = chip->ecc.correct(mtd, p, oob, NULL);
 852
 853         if (stat < 0)
 854                 mtd->ecc_stats.failed++;
 855         else
 856                 mtd->ecc_stats.corrected += stat;
 857
 858         /* get back to oob start (end of page) */
 859         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 860
 861         /* read the oob */
 862         chip->read_buf(mtd, oob, mtd->oobsize);
 863
 864         return 0;
 865 }
 866
 867 /*
 868  * HW ECC Correction
 869  *
 870  * function called after a read
 871  *
 872  * mtd:        MTD block structure
 873  * dat:        raw data read from the chip
 874  * read_ecc:   ECC from the chip (unused)
 875  * isnull:     unused
 876  *
 877  * Detect and correct a 1 bit error for a page
 878  */
 879 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 880                 u_char *read_ecc, u_char *isnull)
 881 {
 882         struct nand_chip *nand_chip = mtd->priv;
 883         unsigned int ecc_status;
 884         unsigned int ecc_word, ecc_bit;
 885
 886         /* get the status from the Status Register */
 887         ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
 888
 889         /* if there's no error */
 890         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
 891                 return 0;
 892
 893         /* get error bit offset (4 bits) */
 894         ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
 895         /* get word address (12 bits) */
 896         ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
 897         ecc_word >>= 4;
 898
 899         /* if there are multiple errors */
 900         if (ecc_status & ATMEL_ECC_MULERR) {
 901                 /* check if it is a freshly erased block
 902                  * (filled with 0xff) */
 903                 if ((ecc_bit == ATMEL_ECC_BITADDR)
 904                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
 905                         /* the block has just been erased, return OK */
 906                         return 0;
 907                 }
 908                 /* it doesn't seems to be a freshly
 909                  * erased block.
 910                  * We can't correct so many errors */
 911                 printk(KERN_WARNING "atmel_nand : multiple errors detected."
 912                                 " Unable to correct.\n");
 913                 return -EIO;
 914         }
 915
 916         /* if there's a single bit error : we can correct it */
 917         if (ecc_status & ATMEL_ECC_ECCERR) {
 918                 /* there's nothing much to do here.
 919                  * the bit error is on the ECC itself.
 920                  */
 921                 printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
 922                                 " Nothing to correct\n");
 923                 return 0;
 924         }
 925
 926         printk(KERN_WARNING "atmel_nand : one bit error on data."
 927                         " (word offset in the page :"
 928                         " 0x%x bit offset : 0x%x)\n",
 929                         ecc_word, ecc_bit);
 930         /* correct the error */
 931         if (nand_chip->options & NAND_BUSWIDTH_16) {
 932                 /* 16 bits words */
 933                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
 934         } else {
 935                 /* 8 bits words */
 936                 dat[ecc_word] ^= (1 << ecc_bit);
 937         }
 938         printk(KERN_WARNING "atmel_nand : error corrected\n");
 939         return 1;
 940 }
 941
 942 /*
 943  * Enable HW ECC : unused on most chips
 944  */
 945 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
 946 {
 947 }
 948
 949 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
 950 {
 951         nand->ecc.mode = NAND_ECC_HW;
 952         nand->ecc.calculate = atmel_nand_calculate;
 953         nand->ecc.correct = atmel_nand_correct;
 954         nand->ecc.hwctl = atmel_nand_hwctl;
 955         nand->ecc.read_page = atmel_nand_read_page;
 956         nand->ecc.bytes = 4;
 957
 958         if (nand->ecc.mode == NAND_ECC_HW) {
 959                 /* ECC is calculated for the whole page (1 step) */
 960                 nand->ecc.size = mtd->writesize;
 961
 962                 /* set ECC page size and oob layout */
 963                 switch (mtd->writesize) {
 964                 case 512:
 965                         nand->ecc.layout = &atmel_oobinfo_small;
 966                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
 967                                         ATMEL_ECC_PAGESIZE_528);
 968                         break;
 969                 case 1024:
 970                         nand->ecc.layout = &atmel_oobinfo_large;
 971                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
 972                                         ATMEL_ECC_PAGESIZE_1056);
 973                         break;
 974                 case 2048:
 975                         nand->ecc.layout = &atmel_oobinfo_large;
 976                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
 977                                         ATMEL_ECC_PAGESIZE_2112);
 978                         break;
 979                 case 4096:
 980                         nand->ecc.layout = &atmel_oobinfo_large;
 981                         ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
 982                                         ATMEL_ECC_PAGESIZE_4224);
 983                         break;
 984                 default:
 985                         /* page size not handled by HW ECC */
 986                         /* switching back to soft ECC */
 987                         nand->ecc.mode = NAND_ECC_SOFT;
 988                         nand->ecc.calculate = NULL;
 989                         nand->ecc.correct = NULL;
 990                         nand->ecc.hwctl = NULL;
 991                         nand->ecc.read_page = NULL;
 992                         nand->ecc.postpad = 0;
 993                         nand->ecc.prepad = 0;
 994                         nand->ecc.bytes = 0;
 995                         break;
 996                 }
 997         }
 998
 999         return 0;
1000 }
1001
1002 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1003
1004 #endif /* CONFIG_ATMEL_NAND_HWECC */
1005
1006 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1007                                          int cmd, unsigned int ctrl)
1008 {
1009         struct nand_chip *this = mtd->priv;
1010
1011         if (ctrl & NAND_CTRL_CHANGE) {
1012                 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1013                 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1014                              | CONFIG_SYS_NAND_MASK_CLE);
1015
1016                 if (ctrl & NAND_CLE)
1017                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1018                 if (ctrl & NAND_ALE)
1019                         IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1020
1021 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1022                 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1023                                     !(ctrl & NAND_NCE));
1024 #endif
1025                 this->IO_ADDR_W = (void *) IO_ADDR_W;
1026         }
1027
1028         if (cmd != NAND_CMD_NONE)
1029                 writeb(cmd, this->IO_ADDR_W);
1030 }
1031
1032 #ifdef CONFIG_SYS_NAND_READY_PIN
1033 static int at91_nand_ready(struct mtd_info *mtd)
1034 {
1035         return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1036 }
1037 #endif
1038
1039 #ifndef CONFIG_SYS_NAND_BASE_LIST
1040 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1041 #endif
1042 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1043 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1044
1045 int atmel_nand_chip_init(int devnum, ulong base_addr)
1046 {
1047         int ret;
1048         struct mtd_info *mtd = &nand_info[devnum];
1049         struct nand_chip *nand = &nand_chip[devnum];
1050
1051         mtd->priv = nand;
1052         nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
1053
1054         nand->ecc.mode = NAND_ECC_SOFT;
1055 #ifdef CONFIG_SYS_NAND_DBW_16
1056         nand->options = NAND_BUSWIDTH_16;
1057 #endif
1058         nand->cmd_ctrl = at91_nand_hwcontrol;
1059 #ifdef CONFIG_SYS_NAND_READY_PIN
1060         nand->dev_ready = at91_nand_ready;
1061 #endif
1062         nand->chip_delay = 20;
1063
1064         ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1065         if (ret)
1066                 return ret;
1067
1068 #ifdef CONFIG_ATMEL_NAND_HWECC
1069 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1070         ret = atmel_pmecc_nand_init_params(nand, mtd);
1071 #else
1072         ret = atmel_hwecc_nand_init_param(nand, mtd);
1073 #endif
1074         if (ret)
1075                 return ret;
1076 #endif
1077
1078         ret = nand_scan_tail(mtd);
1079         if (!ret)
1080                 nand_register(devnum);
1081
1082         return ret;
1083 }
1084
1085 void board_nand_init(void)
1086 {
1087         int i;
1088         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1089                 if (atmel_nand_chip_init(i, base_addr[i]))
1090                         printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",
1091                                 i);
1092 }