Prepare v2013.07-rc2
[karo-tx-uboot.git] / drivers / mtd / nand / jz4740_nand.c
1 /*
2  * Platform independend driver for JZ4740.
3  *
4  * Copyright (c) 2007 Ingenic Semiconductor Inc.
5  * Author: <jlwei@ingenic.cn>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12 #include <common.h>
13
14 #include <nand.h>
15 #include <asm/io.h>
16 #include <asm/jz4740.h>
17
18 #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
19 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
20 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
21
22 #define BIT(x) (1 << (x))
23 #define JZ_NAND_ECC_CTRL_ENCODING       BIT(3)
24 #define JZ_NAND_ECC_CTRL_RS             BIT(2)
25 #define JZ_NAND_ECC_CTRL_RESET          BIT(1)
26 #define JZ_NAND_ECC_CTRL_ENABLE         BIT(0)
27
28 #define EMC_SMCR1_OPT_NAND      0x094c4400
29 /* Optimize the timing of nand */
30
31 static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
32
33 static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
34         .eccbytes = 72,
35         .eccpos = {
36                 12, 13, 14, 15, 16, 17, 18, 19,
37                 20, 21, 22, 23, 24, 25, 26, 27,
38                 28, 29, 30, 31, 32, 33, 34, 35,
39                 36, 37, 38, 39, 40, 41, 42, 43,
40                 44, 45, 46, 47, 48, 49, 50, 51,
41                 52, 53, 54, 55, 56, 57, 58, 59,
42                 60, 61, 62, 63, 64, 65, 66, 67,
43                 68, 69, 70, 71, 72, 73, 74, 75,
44                 76, 77, 78, 79, 80, 81, 82, 83 },
45         .oobfree = {
46                 {.offset = 2,
47                  .length = 10 },
48                 {.offset = 84,
49                  .length = 44 } }
50 };
51
52 static int is_reading;
53
54 static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
55 {
56         struct nand_chip *this = mtd->priv;
57         uint32_t reg;
58
59         if (ctrl & NAND_CTRL_CHANGE) {
60                 if (ctrl & NAND_ALE)
61                         this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
62                 else if (ctrl & NAND_CLE)
63                         this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
64                 else
65                         this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
66
67                 reg = readl(&emc->nfcsr);
68                 if (ctrl & NAND_NCE)
69                         reg |= EMC_NFCSR_NFCE1;
70                 else
71                         reg &= ~EMC_NFCSR_NFCE1;
72                 writel(reg, &emc->nfcsr);
73         }
74
75         if (cmd != NAND_CMD_NONE)
76                 writeb(cmd, this->IO_ADDR_W);
77 }
78
79 static int jz_nand_device_ready(struct mtd_info *mtd)
80 {
81         return (readl(GPIO_PXPIN(2)) & 0x40000000) ? 1 : 0;
82 }
83
84 void board_nand_select_device(struct nand_chip *nand, int chip)
85 {
86         /*
87          * Don't use "chip" to address the NAND device,
88          * generate the cs from the address where it is encoded.
89          */
90 }
91
92 static int jz_nand_rs_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
93                                 u_char *ecc_code)
94 {
95         uint32_t status;
96         int i;
97
98         if (is_reading)
99                 return 0;
100
101         do {
102                 status = readl(&emc->nfints);
103         } while (!(status & EMC_NFINTS_ENCF));
104
105         /* disable ecc */
106         writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
107
108         for (i = 0; i < 9; i++)
109                 ecc_code[i] = readb(&emc->nfpar[i]);
110
111         return 0;
112 }
113
114 static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
115 {
116         uint32_t reg;
117
118         writel(0, &emc->nfints);
119         reg = readl(&emc->nfecr);
120         reg |= JZ_NAND_ECC_CTRL_RESET;
121         reg |= JZ_NAND_ECC_CTRL_ENABLE;
122         reg |= JZ_NAND_ECC_CTRL_RS;
123
124         switch (mode) {
125         case NAND_ECC_READ:
126                 reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
127                 is_reading = 1;
128                 break;
129         case NAND_ECC_WRITE:
130                 reg |= JZ_NAND_ECC_CTRL_ENCODING;
131                 is_reading = 0;
132                 break;
133         default:
134                 break;
135         }
136
137         writel(reg, &emc->nfecr);
138 }
139
140 /* Correct 1~9-bit errors in 512-bytes data */
141 static void jz_rs_correct(unsigned char *dat, int idx, int mask)
142 {
143         int i;
144
145         idx--;
146
147         i = idx + (idx >> 3);
148         if (i >= 512)
149                 return;
150
151         mask <<= (idx & 0x7);
152
153         dat[i] ^= mask & 0xff;
154         if (i < 511)
155                 dat[i + 1] ^= (mask >> 8) & 0xff;
156 }
157
158 static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
159                                    u_char *read_ecc, u_char *calc_ecc)
160 {
161         int k;
162         uint32_t errcnt, index, mask, status;
163
164         /* Set PAR values */
165         const uint8_t all_ff_ecc[] = {
166                 0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f };
167
168         if (read_ecc[0] == 0xff && read_ecc[1] == 0xff &&
169             read_ecc[2] == 0xff && read_ecc[3] == 0xff &&
170             read_ecc[4] == 0xff && read_ecc[5] == 0xff &&
171             read_ecc[6] == 0xff && read_ecc[7] == 0xff &&
172             read_ecc[8] == 0xff) {
173                 for (k = 0; k < 9; k++)
174                         writeb(all_ff_ecc[k], &emc->nfpar[k]);
175         } else {
176                 for (k = 0; k < 9; k++)
177                         writeb(read_ecc[k], &emc->nfpar[k]);
178         }
179         /* Set PRDY */
180         writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
181
182         /* Wait for completion */
183         do {
184                 status = readl(&emc->nfints);
185         } while (!(status & EMC_NFINTS_DECF));
186
187         /* disable ecc */
188         writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
189
190         /* Check decoding */
191         if (!(status & EMC_NFINTS_ERR))
192                 return 0;
193
194         if (status & EMC_NFINTS_UNCOR) {
195                 printf("uncorrectable ecc\n");
196                 return -1;
197         }
198
199         errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
200
201         switch (errcnt) {
202         case 4:
203                 index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >>
204                         EMC_NFERR_INDEX_BIT;
205                 mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
206                         EMC_NFERR_MASK_BIT;
207                 jz_rs_correct(dat, index, mask);
208         case 3:
209                 index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >>
210                         EMC_NFERR_INDEX_BIT;
211                 mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
212                         EMC_NFERR_MASK_BIT;
213                 jz_rs_correct(dat, index, mask);
214         case 2:
215                 index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
216                         EMC_NFERR_INDEX_BIT;
217                 mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
218                         EMC_NFERR_MASK_BIT;
219                 jz_rs_correct(dat, index, mask);
220         case 1:
221                 index = (readl(&emc->nferr[0]) & EMC_NFERR_INDEX_MASK) >>
222                         EMC_NFERR_INDEX_BIT;
223                 mask = (readl(&emc->nferr[0]) & EMC_NFERR_MASK_MASK) >>
224                         EMC_NFERR_MASK_BIT;
225                 jz_rs_correct(dat, index, mask);
226         default:
227                 break;
228         }
229
230         return errcnt;
231 }
232
233 /*
234  * Main initialization routine
235  */
236 int board_nand_init(struct nand_chip *nand)
237 {
238         uint32_t reg;
239
240         reg = readl(&emc->nfcsr);
241         reg |= EMC_NFCSR_NFE1;  /* EMC setup, Set NFE bit */
242         writel(reg, &emc->nfcsr);
243
244         writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]);
245
246         nand->IO_ADDR_R         = JZ_NAND_DATA_ADDR;
247         nand->IO_ADDR_W         = JZ_NAND_DATA_ADDR;
248         nand->cmd_ctrl          = jz_nand_cmd_ctrl;
249         nand->dev_ready         = jz_nand_device_ready;
250         nand->ecc.hwctl         = jz_nand_hwctl;
251         nand->ecc.correct       = jz_nand_rs_correct_data;
252         nand->ecc.calculate     = jz_nand_rs_calculate_ecc;
253         nand->ecc.mode          = NAND_ECC_HW_OOB_FIRST;
254         nand->ecc.size          = CONFIG_SYS_NAND_ECCSIZE;
255         nand->ecc.bytes         = CONFIG_SYS_NAND_ECCBYTES;
256         nand->ecc.strength      = 4;
257         nand->ecc.layout        = &qi_lb60_ecclayout_2gb;
258         nand->chip_delay        = 50;
259         nand->options           = NAND_USE_FLASH_BBT;
260
261         return 0;
262 }