2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #include <linux/err.h>
28 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
29 defined(CONFIG_MX51) || defined(CONFIG_MX53)
30 #include <asm/arch/imx-regs.h>
34 #define pr_debug(fmt...) printk(fmt)
36 #define pr_debug(fmt...) do { } while (0)
39 typedef enum _bool { false, true } bool;
41 static struct mxc_nand_host mxc_host;
42 static struct mxc_nand_host *host = &mxc_host;
45 static int is_16bit_nand(void)
47 struct system_control_regs *sc_regs =
48 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
50 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
55 #elif defined(CONFIG_MX31)
56 static int is_16bit_nand(void)
58 struct clock_control_regs *sc_regs =
59 (struct clock_control_regs *)CCM_BASE;
61 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
66 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
67 static int is_16bit_nand(void)
69 struct ccm_regs *ccm =
70 (struct ccm_regs *)IMX_CCM_BASE;
72 if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
77 #elif defined(CONFIG_MX51)
78 static int is_16bit_nand(void)
80 struct src *src = (struct src *)SRC_BASE_ADDR;
82 if (readl(&src->sbmr) & (1 << 2))
87 #elif defined(CONFIG_MX53)
88 /* BOOT_CFG[1..3][0..7] */
89 #define SRC_BOOT_CFG(m, n) (1 << ((m) * 8 + (n)))
90 static int is_16bit_nand(void)
92 struct src *src = (struct src *)SRC_BASE_ADDR;
94 if (readl(&src->sbmr) & SRC_BOOT_CFG(2, 5))
100 #warning "8/16 bit NAND autodetection not supported"
101 static int is_16bit_nand(void)
107 #define MXC_NAND_TIMEOUT (1 * HZ)
109 #define DRIVER_NAME "mxc_nand"
111 #ifndef CONFIG_MXC_NAND_REGS_BASE
112 #error CONFIG_MXC_NAND_REGS_BASE not defined
115 #if defined(CONFIG_MX27) || defined(CONFIG_MX31)
116 #define nfc_is_v1() 1
117 #define nfc_is_v21() 0
118 #define nfc_is_v3_2() 0
119 #define nfc_is_v3() nfc_is_v3_2()
120 #define NFC_VERSION "V1"
121 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
122 #define nfc_is_v1() 0
123 #define nfc_is_v21() 1
124 #define nfc_is_v3_2() 0
125 #define nfc_is_v3() nfc_is_v3_2()
126 #define NFC_VERSION "V2"
127 #elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
128 #define nfc_is_v1() 0
129 #define nfc_is_v21() 0
130 #define nfc_is_v3_2() 1
131 #define nfc_is_v3() nfc_is_v3_2()
132 #define NFC_VERSION "V3"
133 #ifndef CONFIG_MXC_NAND_IP_BASE
134 #error CONFIG_MXC_NAND_IP_BASE not defined
137 #error mxc_nand driver not supported on this platform
138 #define NFC_VERSION "unknown"
141 #ifndef CONFIG_MXC_NAND_IP_BASE
142 #define CONFIG_MXC_NAND_IP_BASE 0
145 /* Addresses for NFC registers */
146 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
147 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
148 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
149 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
150 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
151 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
152 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
153 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
154 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
155 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
156 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
157 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
158 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
159 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
160 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
161 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
162 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
163 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
164 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
165 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
166 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
167 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
169 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
170 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
171 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
172 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
173 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
174 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
175 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
176 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
177 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
178 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
180 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
183 * Operation modes for the NFC. Valid for v1, v2 and v3
186 #define NFC_CMD (1 << 0)
187 #define NFC_ADDR (1 << 1)
188 #define NFC_INPUT (1 << 2)
189 #define NFC_OUTPUT (1 << 3)
190 #define NFC_ID (1 << 4)
191 #define NFC_STATUS (1 << 5)
193 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
194 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
196 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
197 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
198 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
200 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
202 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
204 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
205 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
206 #define NFC_V3_WRPROT_LOCK (1 << 1)
207 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
208 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
210 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
212 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
213 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
214 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
215 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
216 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
217 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
218 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
219 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
220 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
221 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
222 #define MX53_CONFIG2_PPB(x) (((x) & 0x3) << 8)
223 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
224 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
225 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
226 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
228 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
229 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
230 #define NFC_V3_CONFIG3_FW8 (1 << 3)
231 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
232 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
233 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
234 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
236 #define NFC_V3_IPC (host->regs_ip + 0x2C)
237 #define NFC_V3_IPC_CREQ (1 << 0)
238 #define NFC_V3_IPC_CACK (1 << 1)
239 #define NFC_V3_IPC_INT (1 << 31)
241 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
243 struct mxc_nand_host {
245 struct nand_chip nand;
252 void __iomem *regs_axi;
253 void __iomem *regs_ip;
259 unsigned int buf_start;
262 void (*preset)(struct mtd_info *);
263 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
264 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
265 void (*send_page)(struct mtd_info *, unsigned int);
266 void (*send_read_id)(struct mxc_nand_host *);
267 uint16_t (*get_dev_status)(struct mxc_nand_host *);
268 int (*check_int)(struct mxc_nand_host *);
271 /* OOB placement block for use with hardware ecc generation */
272 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
274 .eccpos = {6, 7, 8, 9, 10},
275 .oobfree = {{0, 5}, {12, 4}, }
278 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
280 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
281 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
282 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
285 /* OOB description for 512 byte pages with 16 byte OOB */
286 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
289 7, 8, 9, 10, 11, 12, 13, 14, 15
292 {.offset = 0, .length = 5}
296 /* OOB description for 2048 byte pages with 64 byte OOB */
297 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
300 7, 8, 9, 10, 11, 12, 13, 14, 15,
301 23, 24, 25, 26, 27, 28, 29, 30, 31,
302 39, 40, 41, 42, 43, 44, 45, 46, 47,
303 55, 56, 57, 58, 59, 60, 61, 62, 63
306 {.offset = 2, .length = 4},
307 {.offset = 16, .length = 7},
308 {.offset = 32, .length = 7},
309 {.offset = 48, .length = 7}
313 /* OOB description for 4096 byte pages with 128 byte OOB */
314 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
317 7, 8, 9, 10, 11, 12, 13, 14, 15,
318 23, 24, 25, 26, 27, 28, 29, 30, 31,
319 39, 40, 41, 42, 43, 44, 45, 46, 47,
320 55, 56, 57, 58, 59, 60, 61, 62, 63,
321 71, 72, 73, 74, 75, 76, 77, 78, 79,
322 87, 88, 89, 90, 91, 92, 93, 94, 95,
323 103, 104, 105, 106, 107, 108, 109, 110, 111,
324 119, 120, 121, 122, 123, 124, 125, 126, 127,
327 {.offset = 2, .length = 4},
328 {.offset = 16, .length = 7},
329 {.offset = 32, .length = 7},
330 {.offset = 48, .length = 7},
331 {.offset = 64, .length = 7},
332 {.offset = 80, .length = 7},
333 {.offset = 96, .length = 7},
334 {.offset = 112, .length = 7},
338 static int check_int_v3(struct mxc_nand_host *host)
342 tmp = readl(NFC_V3_IPC);
343 if (!(tmp & NFC_V3_IPC_INT))
346 tmp &= ~NFC_V3_IPC_INT;
347 writel(tmp, NFC_V3_IPC);
352 static int check_int_v1_v2(struct mxc_nand_host *host)
356 tmp = readw(NFC_V1_V2_CONFIG2);
357 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
360 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
365 /* This function polls the NANDFC to wait for the basic operation to
366 * complete by checking the INT bit of config2 register.
368 static void wait_op_done(struct mxc_nand_host *host, bool useirq)
370 int max_retries = 8000;
372 while (max_retries-- > 0) {
373 if (host->check_int(host))
379 pr_debug("%s: INT not set\n", __func__);
382 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
385 writel(cmd, NFC_V3_FLASH_CMD);
387 /* send out command */
388 writel(NFC_CMD, NFC_V3_LAUNCH);
390 /* Wait for operation to complete */
391 wait_op_done(host, useirq);
394 /* This function issues the specified command to the NAND device and
395 * waits for completion. */
396 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
398 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
400 writew(cmd, NFC_V1_V2_FLASH_CMD);
401 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
403 /* Wait for operation to complete */
404 wait_op_done(host, useirq);
407 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
410 writel(addr, NFC_V3_FLASH_ADDR0);
412 /* send out address */
413 writel(NFC_ADDR, NFC_V3_LAUNCH);
415 wait_op_done(host, islast);
418 /* This function sends an address (or partial address) to the
419 * NAND device. The address is used to select the source/destination for
421 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
423 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
425 writew(addr, NFC_V1_V2_FLASH_ADDR);
426 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
428 /* Wait for operation to complete */
429 wait_op_done(host, islast);
432 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
434 struct nand_chip *nand_chip = mtd->priv;
435 struct mxc_nand_host *host = nand_chip->priv;
438 tmp = readl(NFC_V3_CONFIG1);
440 writel(tmp, NFC_V3_CONFIG1);
442 /* transfer data from NFC ram to nand */
443 writel(ops, NFC_V3_LAUNCH);
445 wait_op_done(host, false);
448 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
450 struct nand_chip *nand_chip = mtd->priv;
451 struct mxc_nand_host *host = nand_chip->priv;
454 if (nfc_is_v1() && mtd->writesize > 512)
459 for (i = 0; i < bufs; i++) {
461 /* NANDFC buffer 0 is used for page read/write */
462 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
464 writew(ops, NFC_V1_V2_CONFIG2);
466 /* Wait for operation to complete */
467 wait_op_done(host, true);
471 static void send_read_id_v3(struct mxc_nand_host *host)
473 /* Read ID into main buffer */
474 writel(NFC_ID, NFC_V3_LAUNCH);
476 wait_op_done(host, true);
478 memcpy(host->data_buf, host->main_area0, 16);
480 pr_debug("read ID %02x %02x %02x %02x\n",
481 host->data_buf[0], host->data_buf[1],
482 host->data_buf[2], host->data_buf[3]);
485 /* Request the NANDFC to perform a read of the NAND device ID. */
486 static void send_read_id_v1_v2(struct mxc_nand_host *host)
488 struct nand_chip *this = &host->nand;
490 /* NANDFC buffer 0 is used for device ID output */
491 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
493 writew(NFC_ID, NFC_V1_V2_CONFIG2);
495 /* Wait for operation to complete */
496 wait_op_done(host, true);
498 memcpy(host->data_buf, host->main_area0, 16);
500 if (this->options & NAND_BUSWIDTH_16) {
501 /* compress the ID info */
502 host->data_buf[1] = host->data_buf[2];
503 host->data_buf[2] = host->data_buf[4];
504 host->data_buf[3] = host->data_buf[6];
505 host->data_buf[4] = host->data_buf[8];
506 host->data_buf[5] = host->data_buf[10];
510 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
512 writel(NFC_STATUS, NFC_V3_LAUNCH);
513 wait_op_done(host, true);
515 return readl(NFC_V3_CONFIG1) >> 16;
518 /* This function requests the NANDFC to perform a read of the
519 * NAND device status and returns the current status. */
520 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
522 void __iomem *main_buf = host->main_area0;
526 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
529 * The device status is stored in main_area0. To
530 * prevent corruption of the buffer save the value
531 * and restore it afterwards.
533 store = readl(main_buf);
535 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
536 wait_op_done(host, true);
538 ret = readw(main_buf);
540 writel(store, main_buf);
545 /* This functions is used by upper layer to checks if device is ready */
546 static int mxc_nand_dev_ready(struct mtd_info *mtd)
549 * NFC handles R/B internally. Therefore, this function
550 * always returns status as ready.
555 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
558 * If HW ECC is enabled, we turn it on during init. There is
559 * no need to enable again here.
563 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
564 u_char *read_ecc, u_char *calc_ecc)
566 struct nand_chip *nand_chip = mtd->priv;
567 struct mxc_nand_host *host = nand_chip->priv;
570 * 1-Bit errors are automatically corrected in HW. No need for
571 * additional correction. 2-Bit errors cannot be corrected by
572 * HW ECC, so we need to return failure
574 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
576 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
577 printk("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
584 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
585 u_char *read_ecc, u_char *calc_ecc)
587 struct nand_chip *nand_chip = mtd->priv;
588 struct mxc_nand_host *host = nand_chip->priv;
592 u8 ecc_bit_mask, err_limit;
594 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
595 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
597 no_subpages = mtd->writesize >> 9;
600 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
602 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
605 err = ecc_stat & ecc_bit_mask;
606 if (err > err_limit) {
607 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
613 } while (--no_subpages);
615 mtd->ecc_stats.corrected += ret;
617 pr_debug("%d Symbol Correctable RS-ECC Errors\n", ret);
622 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
628 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
630 struct nand_chip *nand_chip = mtd->priv;
631 struct mxc_nand_host *host = nand_chip->priv;
634 /* Check for status request */
635 if (host->status_request)
636 return host->get_dev_status(host) & 0xFF;
638 ret = *(uint8_t *)(host->data_buf + host->buf_start);
644 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
646 struct nand_chip *nand_chip = mtd->priv;
647 struct mxc_nand_host *host = nand_chip->priv;
650 ret = *(uint16_t *)(host->data_buf + host->buf_start);
651 host->buf_start += 2;
656 /* Write data of length len to buffer buf. The data to be
657 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
658 * Operation by the NFC, the data is written to NAND Flash */
659 static void mxc_nand_write_buf(struct mtd_info *mtd,
660 const u_char *buf, int len)
662 struct nand_chip *nand_chip = mtd->priv;
663 struct mxc_nand_host *host = nand_chip->priv;
664 u16 col = host->buf_start;
665 int n = mtd->oobsize + mtd->writesize - col;
669 memcpy(host->data_buf + col, buf, n);
671 host->buf_start += n;
674 /* Read the data buffer from the NAND Flash. To read the data from NAND
675 * Flash first the data output cycle is initiated by the NFC, which copies
676 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
678 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
680 struct nand_chip *nand_chip = mtd->priv;
681 struct mxc_nand_host *host = nand_chip->priv;
682 u16 col = host->buf_start;
683 int n = mtd->oobsize + mtd->writesize - col;
687 memcpy(buf, host->data_buf + col, n);
689 host->buf_start += n;
692 /* Used by the upper layer to verify the data in NAND Flash
693 * with the data in the buf. */
694 static int mxc_nand_verify_buf(struct mtd_info *mtd,
695 const u_char *buf, int len)
700 /* This function is used by upper layer for select and
701 * deselect of the NAND chip */
702 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
704 struct nand_chip *nand_chip = mtd->priv;
705 struct mxc_nand_host *host = nand_chip->priv;
708 host->active_cs = chip;
709 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
714 * Function to transfer data to/from spare area.
716 static void copy_spare(struct mtd_info *mtd, bool bfrom)
718 struct nand_chip *this = mtd->priv;
719 struct mxc_nand_host *host = this->priv;
721 u16 n = mtd->writesize >> 9;
722 u8 *d = host->data_buf + mtd->writesize;
723 u8 *s = host->spare0;
724 u16 t = host->spare_len;
726 j = (mtd->oobsize / n >> 1) << 1;
729 for (i = 0; i < n - 1; i++)
730 memcpy(d + i * j, s + i * t, j);
732 /* the last section */
733 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
735 for (i = 0; i < n - 1; i++)
736 memcpy(&s[i * t], &d[i * j], j);
738 /* the last section */
739 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
743 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
745 struct nand_chip *nand_chip = mtd->priv;
746 struct mxc_nand_host *host = nand_chip->priv;
748 /* Write out column address, if necessary */
751 * MXC NANDFC can only perform full page+spare or
752 * spare-only read/write. When the upper layers
753 * perform a read/write buf operation, the saved column
754 * address is used to index into the full page.
756 host->send_addr(host, 0, page_addr == -1);
757 if (mtd->writesize > 512)
758 /* another col addr cycle for 2k page */
759 host->send_addr(host, 0, false);
762 /* Write out page address, if necessary */
763 if (page_addr != -1) {
764 /* paddr_0 - p_addr_7 */
765 host->send_addr(host, (page_addr & 0xff), false);
767 if (mtd->writesize > 512) {
768 if (mtd->size >= 0x10000000) {
769 /* paddr_8 - paddr_15 */
770 host->send_addr(host, (page_addr >> 8) & 0xff, false);
771 host->send_addr(host, (page_addr >> 16) & 0xff, true);
773 /* paddr_8 - paddr_15 */
774 host->send_addr(host, (page_addr >> 8) & 0xff, true);
776 /* One more address cycle for higher density devices */
777 if (mtd->size >= 0x4000000) {
778 /* paddr_8 - paddr_15 */
779 host->send_addr(host, (page_addr >> 8) & 0xff, false);
780 host->send_addr(host, (page_addr >> 16) & 0xff, true);
782 /* paddr_8 - paddr_15 */
783 host->send_addr(host, (page_addr >> 8) & 0xff, true);
789 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
790 * on how much oob the nand chip has. For 8bit ecc we need at least
791 * 26 bytes of oob data per 512 byte block.
793 static int get_eccsize(struct mtd_info *mtd)
795 int oobbytes_per_512 = 0;
797 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
799 if (oobbytes_per_512 < 26)
805 static void preset_v1_v2(struct mtd_info *mtd)
807 struct nand_chip *nand_chip = mtd->priv;
808 struct mxc_nand_host *host = nand_chip->priv;
809 uint16_t config1 = 0;
811 if (nand_chip->ecc.mode == NAND_ECC_HW)
812 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
815 config1 |= NFC_V2_CONFIG1_FP_INT;
817 if (nfc_is_v21() && mtd->writesize) {
818 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
820 host->eccsize = get_eccsize(mtd);
821 if (host->eccsize == 4)
822 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
824 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
829 writew(config1, NFC_V1_V2_CONFIG1);
830 /* preset operation */
832 /* Unlock the internal RAM Buffer */
833 writew(0x2, NFC_V1_V2_CONFIG);
835 /* Blocks to be unlocked */
837 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
838 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
839 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
840 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
841 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
842 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
843 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
844 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
845 } else if (nfc_is_v1()) {
846 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
847 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
851 /* Unlock Block Command for given address range */
852 writew(0x4, NFC_V1_V2_WRPROT);
855 static void preset_v3(struct mtd_info *mtd)
857 struct nand_chip *chip = mtd->priv;
858 struct mxc_nand_host *host = chip->priv;
859 uint32_t config2, config3;
862 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
863 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
864 WARN_ON(!(readl(NFC_V3_IPC) & NFC_V3_IPC_CACK));
866 /* Unlock the internal RAM Buffer */
867 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
870 /* Blocks to be unlocked */
871 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++)
872 writel(0x0 | (0xffff << 16),
873 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
875 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
876 NFC_V3_CONFIG2_2CMD_PHASES |
877 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
878 NFC_V3_CONFIG2_ST_CMD(0x70) |
879 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
881 if (chip->ecc.mode == NAND_ECC_HW)
882 config2 |= NFC_V3_CONFIG2_ECC_EN;
884 addr_phases = fls(chip->pagemask) >> 3;
886 if (mtd->writesize == 2048) {
887 config2 |= NFC_V3_CONFIG2_PS_2048;
888 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
889 } else if (mtd->writesize == 4096) {
890 config2 |= NFC_V3_CONFIG2_PS_4096;
891 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
893 config2 |= NFC_V3_CONFIG2_PS_512;
894 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
897 if (mtd->writesize) {
898 #if defined CONFIG_MX53
899 config2 |= MX53_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
901 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
903 host->eccsize = get_eccsize(mtd);
904 if (host->eccsize == 8)
905 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
908 writel(config2, NFC_V3_CONFIG2);
910 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
911 NFC_V3_CONFIG3_NO_SDMA |
912 NFC_V3_CONFIG3_RBB_MODE |
913 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
914 NFC_V3_CONFIG3_ADD_OP(0);
916 if (!(chip->options & NAND_BUSWIDTH_16))
917 config3 |= NFC_V3_CONFIG3_FW8;
919 writel(config3, NFC_V3_CONFIG3);
921 writel(0, NFC_V3_DELAY_LINE);
922 writel(0, NFC_V3_IPC);
925 /* Used by the upper layer to write command to NAND Flash for
926 * different operations to be carried out on NAND Flash */
927 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
928 int column, int page_addr)
930 struct nand_chip *nand_chip = mtd->priv;
931 struct mxc_nand_host *host = nand_chip->priv;
933 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
934 command, column, page_addr);
936 /* Reset command state information */
937 host->status_request = false;
939 /* Command pre-processing step */
943 host->send_cmd(host, command, false);
946 case NAND_CMD_STATUS:
948 host->status_request = true;
950 host->send_cmd(host, command, true);
951 mxc_do_addr_cycle(mtd, column, page_addr);
955 case NAND_CMD_READOOB:
956 if (command == NAND_CMD_READ0)
957 host->buf_start = column;
959 host->buf_start = column + mtd->writesize;
961 command = NAND_CMD_READ0; /* only READ0 is valid */
963 host->send_cmd(host, command, false);
964 mxc_do_addr_cycle(mtd, column, page_addr);
966 if (mtd->writesize > 512)
967 host->send_cmd(host, NAND_CMD_READSTART, true);
969 host->send_page(mtd, NFC_OUTPUT);
971 memcpy(host->data_buf, host->main_area0, mtd->writesize);
972 copy_spare(mtd, true);
976 if (column >= mtd->writesize)
977 /* call ourself to read a page */
978 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
980 host->buf_start = column;
982 host->send_cmd(host, command, false);
983 mxc_do_addr_cycle(mtd, column, page_addr);
986 case NAND_CMD_PAGEPROG:
987 memcpy(host->main_area0, host->data_buf, mtd->writesize);
988 copy_spare(mtd, false);
989 host->send_page(mtd, NFC_INPUT);
990 host->send_cmd(host, command, true);
991 mxc_do_addr_cycle(mtd, column, page_addr);
994 case NAND_CMD_READID:
995 host->send_cmd(host, command, true);
996 mxc_do_addr_cycle(mtd, column, page_addr);
997 host->send_read_id(host);
998 host->buf_start = column;
1001 case NAND_CMD_ERASE1:
1002 case NAND_CMD_ERASE2:
1003 host->send_cmd(host, command, false);
1004 mxc_do_addr_cycle(mtd, column, page_addr);
1011 * The generic flash bbt decriptors overlap with our ecc
1012 * hardware, so define some i.MX specific ones.
1014 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1015 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1017 static struct nand_bbt_descr bbt_main_descr = {
1018 .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
1019 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1024 .pattern = bbt_pattern,
1027 static struct nand_bbt_descr bbt_mirror_descr = {
1028 .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
1029 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1034 .pattern = mirror_pattern,
1037 static void mxc_nand_chip_init(int devno)
1040 struct nand_chip *this;
1041 struct mtd_info *mtd = &nand_info[devno];
1042 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1044 /* allocate a minimal buffer for the read_id command */
1045 host->data_buf = malloc(16);
1046 if (!host->data_buf) {
1047 printk("Failed to allocate ID buffer\n");
1051 /* structures must be linked */
1055 mtd->name = DRIVER_NAME;
1057 /* 50 us command delay time */
1058 this->chip_delay = 5;
1061 this->dev_ready = mxc_nand_dev_ready;
1062 this->cmdfunc = mxc_nand_command;
1063 this->select_chip = mxc_nand_select_chip;
1064 this->read_byte = mxc_nand_read_byte;
1065 this->read_word = mxc_nand_read_word;
1066 this->write_buf = mxc_nand_write_buf;
1067 this->read_buf = mxc_nand_read_buf;
1068 this->verify_buf = mxc_nand_verify_buf;
1070 host->base = (void __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1075 host->main_area0 = host->base;
1077 if (nfc_is_v1() || nfc_is_v21()) {
1078 host->preset = preset_v1_v2;
1079 host->send_cmd = send_cmd_v1_v2;
1080 host->send_addr = send_addr_v1_v2;
1081 host->send_page = send_page_v1_v2;
1082 host->send_read_id = send_read_id_v1_v2;
1083 host->get_dev_status = get_dev_status_v1_v2;
1084 host->check_int = check_int_v1_v2;
1088 host->regs = host->base + 0x1e00;
1089 host->spare0 = host->base + 0x1000;
1090 host->spare_len = 64;
1091 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1092 oob_largepage = &nandv2_hw_eccoob_largepage;
1093 this->ecc.bytes = 9;
1094 } else if (nfc_is_v1()) {
1095 host->regs = host->base + 0xe00;
1096 host->spare0 = host->base + 0x800;
1097 host->spare_len = 16;
1098 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1099 oob_largepage = &nandv1_hw_eccoob_largepage;
1100 this->ecc.bytes = 3;
1102 } else if (nfc_is_v3_2()) {
1103 host->regs_ip = (void __iomem *)CONFIG_MXC_NAND_IP_BASE;
1104 host->regs_axi = host->base + 0x1e00;
1105 host->spare0 = host->base + 0x1000;
1106 host->spare_len = 64;
1107 host->preset = preset_v3;
1108 host->send_cmd = send_cmd_v3;
1109 host->send_addr = send_addr_v3;
1110 host->send_page = send_page_v3;
1111 host->send_read_id = send_read_id_v3;
1112 host->check_int = check_int_v3;
1113 host->get_dev_status = get_dev_status_v3;
1114 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1115 oob_largepage = &nandv2_hw_eccoob_largepage;
1119 this->ecc.size = 512;
1120 this->ecc.layout = oob_smallpage;
1122 #ifdef CONFIG_MXC_NAND_HWECC
1123 this->ecc.calculate = mxc_nand_calculate_ecc;
1124 this->ecc.hwctl = mxc_nand_enable_hwecc;
1126 this->ecc.correct = mxc_nand_correct_data_v1;
1128 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1129 this->ecc.mode = NAND_ECC_HW;
1131 this->ecc.mode = NAND_ECC_SOFT;
1133 /* NAND bus width determines access funtions used by upper layer */
1134 if (is_16bit_nand())
1135 this->options |= NAND_BUSWIDTH_16;
1137 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1138 this->options |= NAND_USE_FLASH_BBT;
1139 this->bbt_td = &bbt_main_descr;
1140 this->bbt_md = &bbt_mirror_descr;
1141 this->bbt_td->options |= NAND_BBT_CREATE;
1142 this->bbt_md->options |= NAND_BBT_CREATE;
1145 /* first scan to find the device and get the page size */
1146 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1150 host->data_buf = realloc(host->data_buf,
1151 mtd->writesize + mtd->oobsize);
1152 if (!host->data_buf) {
1153 printk("Failed to allocate data buffer of %u byte\n",
1154 mtd->writesize + mtd->oobsize);
1157 pr_debug("Allocated %u byte data buffer\n",
1158 mtd->writesize + mtd->oobsize);
1160 /* Call preset again, with correct writesize this time */
1163 if (mtd->writesize == 2048)
1164 this->ecc.layout = oob_largepage;
1165 if (nfc_is_v21() && mtd->writesize == 4096)
1166 this->ecc.layout = &nandv2_hw_eccoob_4k;
1168 /* second phase scan */
1169 err = nand_scan_tail(mtd);
1171 printk("Nand scan failed: %d\n", err);
1175 err = nand_register(devno);
1180 void board_nand_init(void)
1184 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1185 mxc_nand_chip_init(i);