2 * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
17 #include <asm/errno.h>
18 #include <linux/mtd/nand.h>
19 #include <asm-arm/arch/mxc_nand.h>
20 #include "nand_device_info.h"
35 * Define delays in microsec for NAND device operations
37 #define TROP_US_DELAY 2000
40 * OOB placement block for use with hardware ecc generation
42 static struct nand_ecclayout nand_hw_eccoob_512 = {
44 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
48 static struct nand_ecclayout nand_hw_eccoob_2k = {
50 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
54 static struct nand_ecclayout nand_hw_eccoob_4k = {
56 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
61 static void mxc_nand_bi_swap(struct mtd_info *mtd)
63 struct nand_chip *this = mtd->priv;
64 struct nand_info *info = this->priv;
67 if (!IS_LARGE_PAGE_NAND)
70 ma = __raw_readw(BAD_BLK_MARKER_MAIN);
71 sa = __raw_readw(BAD_BLK_MARKER_SP);
73 nma = (ma & 0xFF00) | (sa >> 8);
74 nsa = (sa & 0x00FF) | (ma << 8);
76 __raw_writew(nma, BAD_BLK_MARKER_MAIN);
77 __raw_writew(nsa, BAD_BLK_MARKER_SP);
82 * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors
88 * @brief This file contains the hardware specific layer for NAND Flash on
95 * Half word access.Added for U-boot.
97 static void *nfc_memcpy(void *dest, const void *src, size_t n)
99 u16 *dst_16 = (u16 *) dest;
100 const u16 *src_16 = (u16 *) src;
103 *dst_16++ = *src_16++;
111 * Functions to transfer data to/from spare erea.
114 copy_spare(struct mtd_info *mtd, void *pbuf, void *pspare, int len, int bfrom)
117 u16 m = mtd->oobsize;
118 u16 n = mtd->writesize >> 9;
120 u8 *s = (u8 *) pspare;
122 struct nand_chip *this = mtd->priv;
123 struct nand_info *info = this->priv;
125 m /= info->num_of_intlv;
126 n /= info->num_of_intlv;
128 j = (m / n >> 1) << 1;
131 for (i = 0; i < n - 1; i++)
132 nfc_memcpy(&d[i * j], &s[i * t], j);
134 /* the last section */
135 nfc_memcpy(&d[i * j], &s[i * t], len - i * j);
137 for (i = 0; i < n - 1; i++)
138 nfc_memcpy(&s[i * t], &d[i * j], j);
140 /* the last section */
141 nfc_memcpy(&s[i * t], &d[i * j], len - i * j);
146 * This function polls the NFC to wait for the basic operation to complete by
147 * checking the INT bit of config2 register.
149 * @param maxRetries number of retry attempts (separated by 1 us)
150 * @param useirq True if IRQ should be used rather than polling
152 static void wait_op_done(int max_retries)
155 while (max_retries-- > 0) {
156 if (raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT) {
157 WRITE_NFC_IP_REG((raw_read(REG_NFC_OPS_STAT) &
164 if (max_retries <= 0)
165 MTDDEBUG(MTD_DEBUG_LEVEL0, "wait: INT not set\n");
169 * This function sends an address (or partial address) to the
170 * NAND device. The address is used to select the source/destination for
173 * @param addr address to be written to NFC.
174 * @param useirq True if IRQ should be used rather than polling
176 static void send_addr(u16 addr)
178 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x)\n", addr);
181 raw_write((addr << NFC_FLASH_ADDR_SHIFT), REG_NFC_FLASH_ADDR);
186 /* send out address */
187 raw_write(NFC_ADDR, REG_NFC_OPS);
189 /* Wait for operation to complete */
190 wait_op_done(TROP_US_DELAY);
193 static void mxc_do_addr_cycle_auto(struct mtd_info *mtd, int column,
196 #ifdef CONFIG_MXC_NFC_SP_AUTO
197 if (page_addr != -1 && column != -1) {
199 /* the column address */
200 raw_write(column & mask, NFC_FLASH_ADDR0);
201 raw_write((raw_read(NFC_FLASH_ADDR0) |
202 ((page_addr & mask) << 16)), NFC_FLASH_ADDR0);
203 /* the row address */
204 raw_write(((raw_read(NFC_FLASH_ADDR8) & (mask << 16)) |
205 ((page_addr & (mask << 16)) >> 16)),
207 } else if (page_addr != -1) {
208 raw_write(page_addr, NFC_FLASH_ADDR0);
211 MTDDEBUG(MTD_DEBUG_LEVEL3,
212 "AutoMode:the ADDR REGS value is (0x%x, 0x%x)\n",
213 raw_read(NFC_FLASH_ADDR0), raw_read(NFC_FLASH_ADDR8));
217 static void mxc_do_addr_cycle_atomic(struct mtd_info *mtd, int column,
220 struct nand_chip *this = mtd->priv;
221 struct nand_info *info = this->priv;
223 u32 page_mask = info->page_mask;
226 send_addr(column & 0xFF);
227 if (IS_2K_PAGE_NAND) {
228 /* another col addr cycle for 2k page */
229 send_addr((column >> 8) & 0xF);
230 } else if (IS_4K_PAGE_NAND) {
231 /* another col addr cycle for 4k page */
232 send_addr((column >> 8) & 0x1F);
235 if (page_addr != -1) {
237 send_addr(page_addr & 0xff);
240 } while (page_mask != 0);
245 * Function to perform the address cycles.
247 static void mxc_nand_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
249 struct nand_chip *this = mtd->priv;
250 struct nand_info *info = this->priv;
253 mxc_do_addr_cycle_auto(mtd, column, page_addr);
255 mxc_do_addr_cycle_atomic(mtd, column, page_addr);
258 static void send_cmd_atomic(struct mtd_info *mtd, u16 cmd)
261 raw_write(cmd, REG_NFC_FLASH_CMD);
266 /* send out command */
267 raw_write(NFC_CMD, REG_NFC_OPS);
269 /* Wait for operation to complete */
270 wait_op_done(TROP_US_DELAY);
274 * Function to record the ECC corrected/uncorrected errors resulted
275 * after a page read. This NFC detects and corrects upto to 4 symbols
278 static int mxc_nand_ecc_status(struct mtd_info *mtd)
283 u8 ecc_bit_mask, err_limit;
284 struct nand_chip *this = mtd->priv;
285 struct nand_info *info = this->priv;
287 ecc_bit_mask = (IS_4BIT_ECC ? 0x7 : 0xf);
288 err_limit = (IS_4BIT_ECC ? 0x4 : 0x8);
290 no_subpages = mtd->writesize >> 9;
292 no_subpages /= info->num_of_intlv;
294 ecc_stat = GET_NFC_ECC_STATUS();
296 err = ecc_stat & ecc_bit_mask;
297 if (err > err_limit) {
298 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
304 } while (--no_subpages);
306 MTDDEBUG(MTD_DEBUG_LEVEL3, "%d Symbol Correctable RS-ECC Error\n", ret);
312 * This function handle the interleave related work
313 * @param mtd mtd info
316 static void send_cmd_interleave(struct mtd_info *mtd, u16 cmd)
318 #ifdef CONFIG_MXC_NFC_SP_AUTO
320 struct nand_chip *this = mtd->priv;
321 struct nand_info *info = this->priv;
322 u32 addr_low = raw_read(NFC_FLASH_ADDR0);
323 u32 addr_high = raw_read(NFC_FLASH_ADDR8);
324 u32 page_addr = addr_low >> 16 | addr_high << 16;
325 u32 i, j = info->num_of_intlv;
326 u8 *dbuf = info->data_buf;
327 u8 *obuf = info->oob_buf;
328 u32 dlen = mtd->writesize / j;
329 u32 olen = mtd->oobsize / j;
331 /* adjust the addr value
332 * since ADD_OP mode is 01
337 page_addr *= this->numchips;
340 case NAND_CMD_PAGEPROG:
341 for (i = 0; i < j; i++) {
342 /* reset addr cycle */
344 mxc_nand_addr_cycle(mtd, 0, page_addr++);
347 nfc_memcpy(MAIN_AREA0, dbuf, dlen);
348 copy_spare(mtd, obuf, SPARE_AREA0, olen, 0);
349 mxc_nand_bi_swap(mtd);
351 /* update the value */
356 raw_write(0, REG_NFC_OPS_STAT);
357 raw_write(NFC_AUTO_PROG, REG_NFC_OPS);
359 /* wait auto_prog_done bit set */
360 while (!(raw_read(REG_NFC_OPS_STAT) & NFC_OP_DONE))
364 wait_op_done(TROP_US_DELAY);
365 while (!(raw_read(REG_NFC_OPS_STAT) & NFC_RB));
368 case NAND_CMD_READSTART:
369 for (i = 0; i < j; i++) {
370 /* reset addr cycle */
372 mxc_nand_addr_cycle(mtd, 0, page_addr++);
375 raw_write(0, REG_NFC_OPS_STAT);
376 raw_write(NFC_AUTO_READ, REG_NFC_OPS);
377 wait_op_done(TROP_US_DELAY);
379 /* check ecc error */
380 mxc_nand_ecc_status(mtd);
383 mxc_nand_bi_swap(mtd);
384 nfc_memcpy(dbuf, MAIN_AREA0, dlen);
385 copy_spare(mtd, obuf, SPARE_AREA0, olen, 1);
387 /* update the value */
392 case NAND_CMD_ERASE2:
393 for (i = 0; i < j; i++) {
395 page_addr = addr_low;
396 page_addr *= (j > 1 ? j : this->numchips);
398 mxc_nand_addr_cycle(mtd, -1, page_addr++);
399 raw_write(0, REG_NFC_OPS_STAT);
400 raw_write(NFC_AUTO_ERASE, REG_NFC_OPS);
401 wait_op_done(TROP_US_DELAY);
405 for (i = 0; i < j; i++) {
407 NFC_SET_NFC_ACTIVE_CS(i);
408 send_cmd_atomic(mtd, cmd);
417 static void send_cmd_auto(struct mtd_info *mtd, u16 cmd)
419 #ifdef CONFIG_MXC_NFC_SP_AUTO
422 case NAND_CMD_READOOB:
423 raw_write(NAND_CMD_READ0, REG_NFC_FLASH_CMD);
426 case NAND_CMD_ERASE1:
427 raw_write(cmd, REG_NFC_FLASH_CMD);
429 case NAND_CMD_PAGEPROG:
430 case NAND_CMD_ERASE2:
431 case NAND_CMD_READSTART:
432 raw_write(raw_read(REG_NFC_FLASH_CMD) | cmd << NFC_CMD_1_SHIFT,
434 send_cmd_interleave(mtd, cmd);
436 case NAND_CMD_READID:
437 send_cmd_atomic(mtd, cmd);
441 send_cmd_interleave(mtd, cmd);
443 case NAND_CMD_STATUS:
444 send_cmd_atomic(mtd, cmd);
453 * This function issues the specified command to the NAND device and
454 * waits for completion.
456 * @param cmd command for NAND Flash
457 * @param useirq True if IRQ should be used rather than polling
459 static void send_cmd(struct mtd_info *mtd, u16 cmd)
462 struct nand_chip *this = mtd->priv;
463 struct nand_info *info = this->priv;
466 send_cmd_auto(mtd, cmd);
468 send_cmd_atomic(mtd, cmd);
470 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x)\n", cmd);
474 * This function requests the NFC to initate the transfer
475 * of data currently in the NFC RAM buffer to the NAND device.
477 * @param buf_id Specify Internal RAM Buffer number
479 static void send_prog_page(struct mtd_info *mtd, u8 buf_id)
481 struct nand_chip *this = mtd->priv;
482 struct nand_info *info = this->priv;
484 if (!info->auto_mode) {
485 /* set ram buffer id */
491 /* transfer data from NFC ram to nand */
492 raw_write(NFC_INPUT, REG_NFC_OPS);
494 /* Wait for operation to complete */
495 wait_op_done(TROP_US_DELAY);
497 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __func__);
502 * This function requests the NFC to initated the transfer
503 * of data from the NAND device into in the NFC ram buffer.
505 * @param buf_id Specify Internal RAM Buffer number
507 static void send_read_page(struct mtd_info *mtd, u8 buf_id)
509 struct nand_chip *this = mtd->priv;
510 struct nand_info *info = this->priv;
512 if (!info->auto_mode) {
514 /* set ram buffer id */
520 /* transfer data from nand to NFC ram */
521 raw_write(NFC_OUTPUT, REG_NFC_OPS);
523 /* Wait for operation to complete */
524 wait_op_done(TROP_US_DELAY);
526 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s(%d)\n", __func__, buf_id);
533 * This function requests the NFC to perform a read of the
536 static void send_read_id(void)
538 /* Set RBA bits for BUFFER0 */
544 /* Read ID into main buffer */
545 raw_write(NFC_ID, REG_NFC_OPS);
547 /* Wait for operation to complete */
548 wait_op_done(TROP_US_DELAY);
552 static u16 mxc_do_status_auto(struct mtd_info *mtd)
555 #ifdef CONFIG_MXC_NFC_SP_AUTO
557 u32 mask = 0xFF << 16;
558 struct nand_chip *this = mtd->priv;
559 struct nand_info *info = this->priv;
561 for (; i < info->num_of_intlv; i++) {
564 NFC_SET_NFC_ACTIVE_CS(i);
569 /* use atomic mode to read status instead
570 * of using auto mode,auto-mode has issues
571 * and the status is not correct.
573 raw_write(NFC_STATUS, REG_NFC_OPS);
575 wait_op_done(TROP_US_DELAY);
577 status = (raw_read(NFC_CONFIG1) & mask) >> 16;
579 if (status & NAND_STATUS_FAIL)
586 static u16 mxc_do_status_atomic(struct mtd_info *mtd)
588 volatile u16 *mainBuf = MAIN_AREA1;
592 /* Set ram buffer id */
598 /* Read status into main buffer */
599 raw_write(NFC_STATUS, REG_NFC_OPS);
601 /* Wait for operation to complete */
602 wait_op_done(TROP_US_DELAY);
604 /* Status is placed in first word of main buffer */
605 /* get status, then recovery area 1 data */
612 * This function requests the NFC to perform a read of the
613 * NAND device status and returns the current status.
615 * @return device status
617 static u16 mxc_nand_get_status(struct mtd_info *mtd)
619 struct nand_chip *this = mtd->priv;
620 struct nand_info *info = this->priv;
624 status = mxc_do_status_auto(mtd);
626 status = mxc_do_status_atomic(mtd);
632 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
634 raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), REG_NFC_ECC_EN);
639 * Function to correct the detected errors. This NFC corrects all the errors
640 * detected. So this function just return 0.
642 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
643 u_char *read_ecc, u_char *calc_ecc)
649 * Function to calculate the ECC for the data to be stored in the Nand device.
650 * This NFC has a hardware RS(511,503) ECC engine together with the RS ECC
651 * CONTROL blocks are responsible for detection and correction of up to
652 * 8 symbols of 9 bits each in 528 byte page.
653 * So this function is just return 0.
656 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
663 * This function id is used to read the data buffer from the NAND Flash. To
664 * read the data from NAND Flash first the data output cycle is initiated by
665 * the NFC, which copies the data to RAMbuffer. This data of length \b len is
666 * then copied to buffer \b buf.
668 * @param mtd MTD structure for the NAND Flash
669 * @param buf data to be read from NAND Flash
670 * @param len number of bytes to be read
672 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
674 struct nand_chip *this = mtd->priv;
675 struct nand_info *info = this->priv;
676 u16 col = info->col_addr;
677 u8 *data_buf = info->data_buf;
678 u8 *oob_buf = info->oob_buf;
680 if (mtd->writesize) {
682 int j = mtd->writesize - col;
683 int n = mtd->oobsize + j;
689 memcpy(buf, &data_buf[col], j);
690 memcpy(buf + j, &oob_buf[0], n - j);
692 memcpy(buf, &data_buf[col], n);
695 col -= mtd->writesize;
696 memcpy(buf, &oob_buf[col], len);
703 /* At flash identify phase,
704 * mtd->writesize has not been
705 * set correctly, it should
706 * be zero.And len will less 2
708 memcpy(buf, &data_buf[col], len);
711 info->col_addr += len;
717 * This function reads byte from the NAND Flash
719 * @param mtd MTD structure for the NAND Flash
721 * @return data read from the NAND Flash
723 static uint8_t mxc_nand_read_byte(struct mtd_info *mtd)
725 struct nand_chip *this = mtd->priv;
726 struct nand_info *info = this->priv;
729 /* Check for status request */
730 if (info->status_req)
731 return mxc_nand_get_status(mtd) & 0xFF;
733 mxc_nand_read_buf(mtd, &ret, 1);
739 * This function reads word from the NAND Flash
741 * @param mtd MTD structure for the NAND Flash
743 * @return data read from the NAND Flash
745 static u16 mxc_nand_read_word(struct mtd_info *mtd)
749 mxc_nand_read_buf(mtd, (uint8_t *) &ret, sizeof(u16));
755 * This function reads byte from the NAND Flash
757 * @param mtd MTD structure for the NAND Flash
759 * @return data read from the NAND Flash
761 static u_char mxc_nand_read_byte16(struct mtd_info *mtd)
763 struct nand_chip *this = mtd->priv;
764 struct nand_info *info = this->priv;
766 /* Check for status request */
767 if (info->status_req)
768 return mxc_nand_get_status(mtd) & 0xFF;
770 return mxc_nand_read_word(mtd) & 0xFF;
775 * This function writes data of length \b len from buffer \b buf to the NAND
776 * internal RAM buffer's MAIN area 0.
778 * @param mtd MTD structure for the NAND Flash
779 * @param buf data to be written to NAND Flash
780 * @param len number of bytes to be written
782 static void mxc_nand_write_buf(struct mtd_info *mtd,
783 const u_char *buf, int len)
785 struct nand_chip *this = mtd->priv;
786 struct nand_info *info = this->priv;
787 u16 col = info->col_addr;
788 u8 *data_buf = info->data_buf;
789 u8 *oob_buf = info->oob_buf;
790 int j = mtd->writesize - col;
791 int n = mtd->oobsize + j;
797 memcpy(&data_buf[col], buf, j);
798 memcpy(&oob_buf[0], buf + j, n - j);
800 memcpy(&data_buf[col], buf, n);
803 col -= mtd->writesize;
804 memcpy(&oob_buf[col], buf, len);
812 * This function is used by the upper layer to verify the data in NAND Flash
813 * with the data in the \b buf.
815 * @param mtd MTD structure for the NAND Flash
816 * @param buf data to be verified
817 * @param len length of the data to be verified
819 * @return -EFAULT if error else 0
822 static int mxc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf,
825 struct nand_chip *this = mtd->priv;
826 struct nand_info *info = this->priv;
827 u_char *s = info->data_buf;
829 const u_char *p = buf;
831 for (; len > 0; len--) {
840 * This function is used by upper layer for select and deselect of the NAND
843 * @param mtd MTD structure for the NAND Flash
844 * @param chip val indicating select or deselect
846 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
854 NFC_SET_NFC_ACTIVE_CS(chip);
863 * This function is used by the upper layer to write command to NAND Flash for
864 * different operations to be carried out on NAND Flash
866 * @param mtd MTD structure for the NAND Flash
867 * @param command command for NAND Flash
868 * @param column column offset for the page read
869 * @param page_addr page to be read from NAND Flash
871 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
872 int column, int page_addr)
874 struct nand_chip *this = mtd->priv;
875 struct nand_info *info = this->priv;
877 MTDDEBUG(MTD_DEBUG_LEVEL3,
878 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
879 command, column, page_addr);
881 * Reset command state information
883 info->status_req = 0;
886 * Command pre-processing step
889 case NAND_CMD_STATUS:
891 info->status_req = 1;
895 info->col_addr = column;
898 case NAND_CMD_READOOB:
899 info->col_addr = column;
900 command = NAND_CMD_READ0;
906 /* FIXME: before send SEQIN command for
907 * partial write,We need read one page out.
908 * FSL NFC does not support partial write
909 * It alway send out 512+ecc+512+ecc ...
910 * for large page nand flash. But for small
911 * page nand flash, it did support SPARE
912 * ONLY operation. But to make driver
913 * simple. We take the same as large page,read
914 * whole page out and update. As for MLC nand
915 * NOP(num of operation) = 1. Partial written
916 * on one programed page is not allowed! We
917 * can't limit it on the driver, it need the
918 * upper layer applicaiton take care it
921 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
924 info->col_addr = column;
927 case NAND_CMD_PAGEPROG:
928 if (!info->auto_mode) {
929 nfc_memcpy(MAIN_AREA0, info->data_buf, mtd->writesize);
930 copy_spare(mtd, info->oob_buf, SPARE_AREA0,
932 mxc_nand_bi_swap(mtd);
935 send_prog_page(mtd, 0);
938 case NAND_CMD_ERASE1:
939 case NAND_CMD_ERASE2:
944 * Write out the command to the device.
946 send_cmd(mtd, command);
948 mxc_nand_addr_cycle(mtd, column, page_addr);
951 * Command post-processing step
955 case NAND_CMD_READOOB:
957 if (info->large_page)
958 /* send read confirm command */
959 send_cmd(mtd, NAND_CMD_READSTART);
961 send_read_page(mtd, 0);
963 if (!info->auto_mode) {
964 mxc_nand_ecc_status(mtd);
965 mxc_nand_bi_swap(mtd);
966 nfc_memcpy(info->data_buf, MAIN_AREA0, mtd->writesize);
967 copy_spare(mtd, info->oob_buf, SPARE_AREA0,
972 case NAND_CMD_READID:
974 info->col_addr = column;
975 nfc_memcpy(info->data_buf, MAIN_AREA0, 2048);
980 static int mxc_nand_read_oob(struct mtd_info *mtd,
981 struct nand_chip *chip, int page, int sndcmd)
983 struct nand_chip *this = mtd->priv;
984 struct nand_info *info = this->priv;
988 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
992 memcpy(chip->oob_poi, info->oob_buf, mtd->oobsize);
997 static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1000 struct nand_chip *this = mtd->priv;
1001 struct nand_info *info = this->priv;
1003 #ifndef CONFIG_MXC_NFC_SP_AUTO
1004 mxc_nand_ecc_status(mtd);
1007 memcpy(buf, info->data_buf, mtd->writesize);
1008 memcpy(chip->oob_poi, info->oob_buf, mtd->oobsize);
1013 static void mxc_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1016 struct nand_chip *this = mtd->priv;
1017 struct nand_info *info = this->priv;
1019 memcpy(info->data_buf, buf, mtd->writesize);
1020 memcpy(info->oob_buf, chip->oob_poi, mtd->oobsize);
1025 * mxc_nand_prog_page - [REPLACEABLE] write one page
1026 * @mtd: MTD device structure
1027 * @chip: NAND chip descriptor
1028 * @buf: the data to write
1029 * @page: page number to write
1030 * @cached: cached programming
1031 * @raw: use _raw version of write_page
1033 static int mxc_nand_prog_page(struct mtd_info *mtd, struct nand_chip *chip,
1034 const uint8_t *buf, int page, int cached, int raw)
1039 for (i = 0; i < mtd->writesize; i += 4) {
1040 if (*(u32 *)(buf + i) != (u32)-1)
1044 if (i == mtd->writesize)
1047 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1050 chip->ecc.write_page_raw(mtd, chip, buf);
1052 chip->ecc.write_page(mtd, chip, buf);
1055 * Cached progamming disabled for now, Not sure if its worth the
1056 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1060 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1062 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1063 status = chip->waitfunc(mtd, chip);
1065 * See if operation failed and additional status checks are
1068 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1069 status = chip->errstat(mtd, chip, FL_WRITING, status,
1072 if (status & NAND_STATUS_FAIL)
1075 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1076 status = chip->waitfunc(mtd, chip);
1080 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1081 /* Send command to read back the data */
1082 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1084 if (chip->verify_buf(mtd, buf, mtd->writesize))
1090 /* Define some generic bad / good block scan pattern which are used
1091 * while scanning a device for factory marked good / bad blocks. */
1092 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
1094 static struct nand_bbt_descr smallpage_memorybased = {
1095 .options = NAND_BBT_SCAN2NDPAGE,
1098 .pattern = scan_ff_pattern
1101 static struct nand_bbt_descr largepage_memorybased = {
1105 .pattern = scan_ff_pattern
1108 /* Generic flash bbt decriptors
1110 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1111 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1113 static struct nand_bbt_descr bbt_main_descr = {
1114 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1115 | NAND_BBT_2BIT | NAND_BBT_VERSION,
1120 .pattern = bbt_pattern
1123 static struct nand_bbt_descr bbt_mirror_descr = {
1124 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1125 | NAND_BBT_2BIT | NAND_BBT_VERSION,
1130 .pattern = mirror_pattern
1133 static int mxc_nand_scan_bbt(struct mtd_info *mtd)
1136 uint8_t id_bytes[NAND_DEVICE_ID_BYTE_COUNT];
1137 struct nand_chip *this = mtd->priv;
1138 struct nand_info *info = this->priv;
1139 struct nand_device_info *dev_info;
1141 info->page_mask = this->pagemask;
1143 if (!IS_LARGE_PAGE_NAND)
1146 /* Read ID bytes from the first NAND Flash chip. */
1147 this->select_chip(mtd, 0);
1149 this->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1151 for (i = 0; i < NAND_DEVICE_ID_BYTE_COUNT; i++)
1152 id_bytes[i] = this->read_byte(mtd);
1154 /* Get information about this device, based on the ID bytes. */
1155 dev_info = nand_device_get_info(id_bytes);
1157 /* Check if we understand this device. */
1159 printk(KERN_ERR "Unrecognized NAND Flash device.\n");
1163 nand_device_print_info(dev_info);
1165 /* Correct mtd setting */
1166 this->chipsize = dev_info->chip_size_in_bytes;
1167 mtd->size = dev_info->chip_size_in_bytes * this->numchips;
1168 mtd->writesize = dev_info->page_total_size_in_bytes & ~0x3ff;
1169 mtd->oobsize = dev_info->page_total_size_in_bytes & 0x3ff;;
1170 mtd->erasesize = dev_info->block_size_in_pages * mtd->writesize;
1172 /* limit to 2G size due to Kernel
1173 * larger 4G space support,need fix
1176 if ((u32)mtd->size == 0) {
1177 mtd->size = (u32)(1 << 31);
1179 this->chipsize = mtd->size;
1182 /* Calculate the address shift from the page size */
1183 this->page_shift = ffs(mtd->writesize) - 1;
1184 /* Convert chipsize to number of pages per chip -1. */
1185 this->pagemask = (this->chipsize >> this->page_shift) - 1;
1187 this->bbt_erase_shift = this->phys_erase_shift =
1188 ffs(mtd->erasesize) - 1;
1189 this->chip_shift = ffs(this->chipsize) - 1;
1190 this->oob_poi = this->buffers->databuf + mtd->writesize;
1193 if (IS_2K_PAGE_NAND) {
1194 NFC_SET_NFMS(1 << NFMS_NF_PG_SZ);
1195 this->ecc.layout = &nand_hw_eccoob_2k;
1196 info->large_page = 1;
1197 } else if (IS_4K_PAGE_NAND) {
1198 NFC_SET_NFMS(1 << NFMS_NF_PG_SZ);
1199 this->ecc.layout = &nand_hw_eccoob_4k;
1200 info->large_page = 1;
1202 this->ecc.layout = &nand_hw_eccoob_512;
1203 info->large_page = 0;
1206 /* propagate ecc.layout to mtd_info */
1207 mtd->ecclayout = this->ecc.layout;
1209 /* jffs2 not write oob */
1210 /*mtd->flags &= ~MTD_OOB_WRITEABLE;*/
1212 /* fix up the offset */
1213 largepage_memorybased.offs = BAD_BLK_MARKER_OOB_OFFS;
1215 /* use flash based bbt */
1216 this->bbt_td = &bbt_main_descr;
1217 this->bbt_md = &bbt_mirror_descr;
1219 /* update flash based bbt */
1220 this->options |= NAND_USE_FLASH_BBT;
1222 if (!this->badblock_pattern) {
1223 this->badblock_pattern = (mtd->writesize > 512) ?
1224 &largepage_memorybased : &smallpage_memorybased;
1227 /* Build bad block table */
1228 return nand_scan_bbt(mtd, this->badblock_pattern);
1231 static void mxc_nfc_init(void)
1233 /* Disable interrupt */
1234 raw_write((raw_read(REG_NFC_INTRRUPT) | NFC_INT_MSK), REG_NFC_INTRRUPT);
1236 /* disable spare enable */
1237 raw_write(raw_read(REG_NFC_SP_EN) & ~NFC_SP_EN, REG_NFC_SP_EN);
1239 /* Unlock the internal RAM Buffer */
1240 raw_write(NFC_SET_BLS(NFC_BLS_UNLCOKED), REG_NFC_BLS);
1242 /* Blocks to be unlocked */
1243 UNLOCK_ADDR(0x0, 0xFFFF);
1245 /* Unlock Block Command for given address range */
1246 raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC);
1249 raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), REG_NFC_ECC_EN);
1252 static int mxc_alloc_buf(struct nand_info *info)
1256 info->data_buf = kmalloc(NAND_MAX_PAGESIZE, GFP_KERNEL);
1257 if (!info->data_buf) {
1258 printk(KERN_ERR "%s: failed to allocate data_buf\n", __func__);
1262 memset(info->data_buf, 0, NAND_MAX_PAGESIZE);
1264 info->oob_buf = kmalloc(NAND_MAX_OOBSIZE, GFP_KERNEL);
1265 if (!info->oob_buf) {
1266 printk(KERN_ERR "%s: failed to allocate oob_buf\n", __func__);
1270 memset(info->oob_buf, 0, NAND_MAX_OOBSIZE);
1276 * This function is called during the driver binding process.
1278 * @param pdev the device structure used to store device specific
1279 * information that is used by the suspend, resume and
1282 * @return The function always returns 0.
1284 int board_nand_init(struct nand_chip *nand)
1286 struct nand_info *info;
1287 struct nand_chip *this = nand;
1288 struct mtd_info *mtd; /* dummy for compile */
1291 info = kmalloc(sizeof(struct nand_info), GFP_KERNEL);
1293 printk(KERN_ERR "%s: failed to allocate nand_info\n",
1298 memset(info, 0, sizeof(struct nand_info));
1300 if (mxc_alloc_buf(info)) {
1305 info->num_of_intlv = 1;
1307 #ifdef CONFIG_MXC_NFC_SP_AUTO
1308 info->auto_mode = 1;
1315 this->cmdfunc = mxc_nand_command;
1316 this->select_chip = mxc_nand_select_chip;
1317 this->read_byte = mxc_nand_read_byte;
1318 this->read_word = mxc_nand_read_word;
1319 this->write_buf = mxc_nand_write_buf;
1320 this->read_buf = mxc_nand_read_buf;
1321 this->verify_buf = mxc_nand_verify_buf;
1322 this->scan_bbt = mxc_nand_scan_bbt;
1323 this->write_page = mxc_nand_prog_page;
1324 this->ecc.read_page = mxc_nand_read_page;
1325 this->ecc.write_page = mxc_nand_write_page;
1326 this->ecc.read_oob = mxc_nand_read_oob;
1327 this->ecc.calculate = mxc_nand_calculate_ecc;
1328 this->ecc.correct = mxc_nand_correct_data;
1329 this->ecc.hwctl = mxc_nand_enable_hwecc;
1330 this->ecc.layout = &nand_hw_eccoob_512;
1331 this->ecc.mode = NAND_ECC_HW;
1332 this->ecc.bytes = 9;
1333 this->ecc.size = 512;
1335 #ifdef CONFIG_NAND_FW_16BIT
1336 if (CONFIG_NAND_FW_16BIT == 1) {
1337 this->read_byte = mxc_nand_read_byte16;
1338 this->options |= NAND_BUSWIDTH_16;
1339 NFC_SET_NFMS(1 << NFMS_NF_DWIDTH);