2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #include <linux/err.h>
28 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
29 defined(CONFIG_MX51) || defined(CONFIG_MX53)
30 #include <asm/arch/imx-regs.h>
33 static struct mxc_nand_host mxc_host;
34 static struct mxc_nand_host *host = &mxc_host;
37 static int is_16bit_nand(void)
39 struct system_control_regs *sc_regs =
40 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
42 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
47 #elif defined(CONFIG_MX31)
48 static int is_16bit_nand(void)
50 struct clock_control_regs *sc_regs =
51 (struct clock_control_regs *)CCM_BASE;
53 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
58 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
59 static int is_16bit_nand(void)
61 struct ccm_regs *ccm =
62 (struct ccm_regs *)IMX_CCM_BASE;
64 if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
69 #elif defined(CONFIG_MX51)
70 static int is_16bit_nand(void)
72 struct src *src = (struct src *)SRC_BASE_ADDR;
74 if (readl(&src->sbmr) & (1 << 2))
79 #elif defined(CONFIG_MX53)
80 /* BOOT_CFG[1..3][0..7] */
81 #define SRC_BOOT_CFG(m, n) (1 << ((m) * 8 + (n)))
82 static int is_16bit_nand(void)
84 struct src *src = (struct src *)SRC_BASE_ADDR;
86 if (readl(&src->sbmr) & SRC_BOOT_CFG(2, 5))
92 #warning "8/16 bit NAND autodetection not supported"
93 static int is_16bit_nand(void)
99 #define MXC_NAND_TIMEOUT (1 * HZ)
101 #define DRIVER_NAME "mxc_nand"
103 #ifndef CONFIG_MXC_NAND_REGS_BASE
104 #error CONFIG_MXC_NAND_REGS_BASE not defined
107 #if defined(CONFIG_MX27) || defined(CONFIG_MX31)
108 #define nfc_is_v1() 1
109 #define nfc_is_v21() 0
110 #define nfc_is_v3_2() 0
111 #define nfc_is_v3() nfc_is_v3_2()
112 #define NFC_VERSION "V1"
113 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
114 #define nfc_is_v1() 0
115 #define nfc_is_v21() 1
116 #define nfc_is_v3_2() 0
117 #define nfc_is_v3() nfc_is_v3_2()
118 #define NFC_VERSION "V2"
119 #elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
120 #define nfc_is_v1() 0
121 #define nfc_is_v21() 0
122 #define nfc_is_v3_2() 1
123 #define nfc_is_v3() nfc_is_v3_2()
124 #define NFC_VERSION "V3"
125 #ifndef CONFIG_MXC_NAND_IP_REGS_BASE
126 #error CONFIG_MXC_NAND_IP_REGS_BASE not defined
129 #error mxc_nand driver not supported on this platform
130 #define NFC_VERSION "unknown"
133 /* Addresses for NFC registers */
134 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
135 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
136 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
137 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
138 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
139 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
140 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
141 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
142 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
143 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
144 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
145 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
146 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
147 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
148 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
149 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
150 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
151 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
152 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
153 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
154 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
155 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
157 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
158 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
159 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
160 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
161 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
162 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
163 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
164 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
165 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
166 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
168 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
171 * Operation modes for the NFC. Valid for v1, v2 and v3
174 #define NFC_CMD (1 << 0)
175 #define NFC_ADDR (1 << 1)
176 #define NFC_INPUT (1 << 2)
177 #define NFC_OUTPUT (1 << 3)
178 #define NFC_ID (1 << 4)
179 #define NFC_STATUS (1 << 5)
181 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
182 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
184 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
185 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
186 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
188 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
190 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
192 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
193 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
194 #define NFC_V3_WRPROT_LOCK (1 << 1)
195 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
196 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
198 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
200 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
201 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
202 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
203 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
204 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
205 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
206 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
207 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
208 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
209 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
210 #define MX53_CONFIG2_PPB(x) (((x) & 0x3) << 8)
211 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
212 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
213 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
214 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
216 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
217 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
218 #define NFC_V3_CONFIG3_FW8 (1 << 3)
219 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
220 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
221 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
222 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
224 #define NFC_V3_IPC (host->regs_ip + 0x2C)
225 #define NFC_V3_IPC_CREQ (1 << 0)
226 #define NFC_V3_IPC_CACK (1 << 1)
227 #define NFC_V3_IPC_INT (1 << 31)
229 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
231 struct mxc_nand_host {
233 struct nand_chip nand;
240 void __iomem *regs_axi;
241 void __iomem *regs_ip;
247 unsigned int buf_start;
250 void (*preset)(struct mtd_info *);
251 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
252 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
253 void (*send_page)(struct mtd_info *, unsigned int);
254 void (*send_read_id)(struct mxc_nand_host *);
255 uint16_t (*get_dev_status)(struct mxc_nand_host *);
256 int (*check_int)(struct mxc_nand_host *);
259 /* OOB placement block for use with hardware ecc generation */
260 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
262 .eccpos = {6, 7, 8, 9, 10},
263 .oobfree = {{0, 5}, {12, 4}, }
266 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
268 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
269 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
270 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
273 /* OOB description for 512 byte pages with 16 byte OOB */
274 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
277 7, 8, 9, 10, 11, 12, 13, 14, 15
280 {.offset = 0, .length = 5}
284 /* OOB description for 2048 byte pages with 64 byte OOB */
285 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
288 7, 8, 9, 10, 11, 12, 13, 14, 15,
289 23, 24, 25, 26, 27, 28, 29, 30, 31,
290 39, 40, 41, 42, 43, 44, 45, 46, 47,
291 55, 56, 57, 58, 59, 60, 61, 62, 63
294 {.offset = 2, .length = 4},
295 {.offset = 16, .length = 7},
296 {.offset = 32, .length = 7},
297 {.offset = 48, .length = 7}
301 /* OOB description for 4096 byte pages with 128 byte OOB */
302 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
305 7, 8, 9, 10, 11, 12, 13, 14, 15,
306 23, 24, 25, 26, 27, 28, 29, 30, 31,
307 39, 40, 41, 42, 43, 44, 45, 46, 47,
308 55, 56, 57, 58, 59, 60, 61, 62, 63,
309 71, 72, 73, 74, 75, 76, 77, 78, 79,
310 87, 88, 89, 90, 91, 92, 93, 94, 95,
311 103, 104, 105, 106, 107, 108, 109, 110, 111,
312 119, 120, 121, 122, 123, 124, 125, 126, 127,
315 {.offset = 2, .length = 4},
316 {.offset = 16, .length = 7},
317 {.offset = 32, .length = 7},
318 {.offset = 48, .length = 7},
319 {.offset = 64, .length = 7},
320 {.offset = 80, .length = 7},
321 {.offset = 96, .length = 7},
322 {.offset = 112, .length = 7},
326 static int check_int_v3(struct mxc_nand_host *host)
330 tmp = readl(NFC_V3_IPC);
331 if (!(tmp & NFC_V3_IPC_INT))
334 tmp &= ~NFC_V3_IPC_INT;
335 writel(tmp, NFC_V3_IPC);
340 static int check_int_v1_v2(struct mxc_nand_host *host)
344 tmp = readw(NFC_V1_V2_CONFIG2);
345 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
348 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
353 /* This function polls the NANDFC to wait for the basic operation to
354 * complete by checking the INT bit of config2 register.
356 static void wait_op_done(struct mxc_nand_host *host, bool useirq)
358 int max_retries = 8000;
360 while (max_retries-- > 0) {
361 if (host->check_int(host))
367 pr_debug("%s: INT not set\n", __func__);
370 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
373 writel(cmd, NFC_V3_FLASH_CMD);
375 /* send out command */
376 writel(NFC_CMD, NFC_V3_LAUNCH);
378 /* Wait for operation to complete */
379 wait_op_done(host, useirq);
382 /* This function issues the specified command to the NAND device and
383 * waits for completion. */
384 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
386 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
388 writew(cmd, NFC_V1_V2_FLASH_CMD);
389 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
391 /* Wait for operation to complete */
392 wait_op_done(host, useirq);
395 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
398 writel(addr, NFC_V3_FLASH_ADDR0);
400 /* send out address */
401 writel(NFC_ADDR, NFC_V3_LAUNCH);
403 wait_op_done(host, islast);
406 /* This function sends an address (or partial address) to the
407 * NAND device. The address is used to select the source/destination for
409 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
411 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
413 writew(addr, NFC_V1_V2_FLASH_ADDR);
414 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
416 /* Wait for operation to complete */
417 wait_op_done(host, islast);
420 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
422 struct nand_chip *nand_chip = mtd->priv;
423 struct mxc_nand_host *host = nand_chip->priv;
426 tmp = readl(NFC_V3_CONFIG1);
428 writel(tmp, NFC_V3_CONFIG1);
430 /* transfer data from NFC ram to nand */
431 writel(ops, NFC_V3_LAUNCH);
433 wait_op_done(host, false);
436 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
438 struct nand_chip *nand_chip = mtd->priv;
439 struct mxc_nand_host *host = nand_chip->priv;
442 if (nfc_is_v1() && mtd->writesize > 512)
447 for (i = 0; i < bufs; i++) {
449 /* NANDFC buffer 0 is used for page read/write */
450 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
452 writew(ops, NFC_V1_V2_CONFIG2);
454 /* Wait for operation to complete */
455 wait_op_done(host, true);
459 static void send_read_id_v3(struct mxc_nand_host *host)
461 /* Read ID into main buffer */
462 writel(NFC_ID, NFC_V3_LAUNCH);
464 wait_op_done(host, true);
466 memcpy(host->data_buf, host->main_area0, 16);
468 pr_debug("read ID %02x %02x %02x %02x\n",
469 host->data_buf[0], host->data_buf[1],
470 host->data_buf[2], host->data_buf[3]);
473 /* Request the NANDFC to perform a read of the NAND device ID. */
474 static void send_read_id_v1_v2(struct mxc_nand_host *host)
476 struct nand_chip *this = &host->nand;
478 /* NANDFC buffer 0 is used for device ID output */
479 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
481 writew(NFC_ID, NFC_V1_V2_CONFIG2);
483 /* Wait for operation to complete */
484 wait_op_done(host, true);
486 memcpy(host->data_buf, host->main_area0, 16);
488 if (this->options & NAND_BUSWIDTH_16) {
489 /* compress the ID info */
490 host->data_buf[1] = host->data_buf[2];
491 host->data_buf[2] = host->data_buf[4];
492 host->data_buf[3] = host->data_buf[6];
493 host->data_buf[4] = host->data_buf[8];
494 host->data_buf[5] = host->data_buf[10];
498 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
500 writel(NFC_STATUS, NFC_V3_LAUNCH);
501 wait_op_done(host, true);
503 return readl(NFC_V3_CONFIG1) >> 16;
506 /* This function requests the NANDFC to perform a read of the
507 * NAND device status and returns the current status. */
508 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
510 void __iomem *main_buf = host->main_area0;
514 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
517 * The device status is stored in main_area0. To
518 * prevent corruption of the buffer save the value
519 * and restore it afterwards.
521 store = readl(main_buf);
523 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
524 wait_op_done(host, true);
526 ret = readw(main_buf);
528 writel(store, main_buf);
533 /* This functions is used by upper layer to checks if device is ready */
534 static int mxc_nand_dev_ready(struct mtd_info *mtd)
537 * NFC handles R/B internally. Therefore, this function
538 * always returns status as ready.
543 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
546 * If HW ECC is enabled, we turn it on during init. There is
547 * no need to enable again here.
551 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
552 u_char *read_ecc, u_char *calc_ecc)
554 struct nand_chip *nand_chip = mtd->priv;
555 struct mxc_nand_host *host = nand_chip->priv;
558 * 1-Bit errors are automatically corrected in HW. No need for
559 * additional correction. 2-Bit errors cannot be corrected by
560 * HW ECC, so we need to return failure
562 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
564 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
565 printk("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
572 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
573 u_char *read_ecc, u_char *calc_ecc)
575 struct nand_chip *nand_chip = mtd->priv;
576 struct mxc_nand_host *host = nand_chip->priv;
580 u8 ecc_bit_mask, err_limit;
582 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
583 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
585 no_subpages = mtd->writesize >> 9;
588 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
590 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
593 err = ecc_stat & ecc_bit_mask;
594 if (err > err_limit) {
595 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
601 } while (--no_subpages);
603 mtd->ecc_stats.corrected += ret;
605 pr_debug("%d Symbol Correctable RS-ECC Errors\n", ret);
610 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
616 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
618 struct nand_chip *nand_chip = mtd->priv;
619 struct mxc_nand_host *host = nand_chip->priv;
622 /* Check for status request */
623 if (host->status_request)
624 return host->get_dev_status(host) & 0xFF;
626 ret = *(uint8_t *)(host->data_buf + host->buf_start);
632 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
634 struct nand_chip *nand_chip = mtd->priv;
635 struct mxc_nand_host *host = nand_chip->priv;
638 ret = *(uint16_t *)(host->data_buf + host->buf_start);
639 host->buf_start += 2;
644 /* Write data of length len to buffer buf. The data to be
645 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
646 * Operation by the NFC, the data is written to NAND Flash */
647 static void mxc_nand_write_buf(struct mtd_info *mtd,
648 const u_char *buf, int len)
650 struct nand_chip *nand_chip = mtd->priv;
651 struct mxc_nand_host *host = nand_chip->priv;
652 u16 col = host->buf_start;
653 int n = mtd->oobsize + mtd->writesize - col;
657 memcpy(host->data_buf + col, buf, n);
659 host->buf_start += n;
662 /* Read the data buffer from the NAND Flash. To read the data from NAND
663 * Flash first the data output cycle is initiated by the NFC, which copies
664 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
666 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
668 struct nand_chip *nand_chip = mtd->priv;
669 struct mxc_nand_host *host = nand_chip->priv;
670 u16 col = host->buf_start;
671 int n = mtd->oobsize + mtd->writesize - col;
675 memcpy(buf, host->data_buf + col, n);
677 host->buf_start += n;
680 /* Used by the upper layer to verify the data in NAND Flash
681 * with the data in the buf. */
682 static int mxc_nand_verify_buf(struct mtd_info *mtd,
683 const u_char *buf, int len)
688 /* This function is used by upper layer for select and
689 * deselect of the NAND chip */
690 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
692 struct nand_chip *nand_chip = mtd->priv;
693 struct mxc_nand_host *host = nand_chip->priv;
696 host->active_cs = chip;
697 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
702 * Function to transfer data to/from spare area.
704 static void copy_spare(struct mtd_info *mtd, bool bfrom)
706 struct nand_chip *this = mtd->priv;
707 struct mxc_nand_host *host = this->priv;
709 u16 n = mtd->writesize >> 9;
710 u8 *d = host->data_buf + mtd->writesize;
711 u8 *s = host->spare0;
712 u16 t = host->spare_len;
714 j = (mtd->oobsize / n >> 1) << 1;
717 for (i = 0; i < n - 1; i++)
718 memcpy(d + i * j, s + i * t, j);
720 /* the last section */
721 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
723 for (i = 0; i < n - 1; i++)
724 memcpy(&s[i * t], &d[i * j], j);
726 /* the last section */
727 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
731 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
733 struct nand_chip *nand_chip = mtd->priv;
734 struct mxc_nand_host *host = nand_chip->priv;
736 /* Write out column address, if necessary */
739 * MXC NANDFC can only perform full page+spare or
740 * spare-only read/write. When the upper layers
741 * perform a read/write buf operation, the saved column
742 * address is used to index into the full page.
744 host->send_addr(host, 0, page_addr == -1);
745 if (mtd->writesize > 512)
746 /* another col addr cycle for 2k page */
747 host->send_addr(host, 0, false);
750 /* Write out page address, if necessary */
751 if (page_addr != -1) {
752 /* paddr_0 - p_addr_7 */
753 host->send_addr(host, (page_addr & 0xff), false);
755 if (mtd->writesize > 512) {
756 if (mtd->size >= 0x10000000) {
757 /* paddr_8 - paddr_15 */
758 host->send_addr(host, (page_addr >> 8) & 0xff, false);
759 host->send_addr(host, (page_addr >> 16) & 0xff, true);
761 /* paddr_8 - paddr_15 */
762 host->send_addr(host, (page_addr >> 8) & 0xff, true);
764 /* One more address cycle for higher density devices */
765 if (mtd->size >= 0x4000000) {
766 /* paddr_8 - paddr_15 */
767 host->send_addr(host, (page_addr >> 8) & 0xff, false);
768 host->send_addr(host, (page_addr >> 16) & 0xff, true);
770 /* paddr_8 - paddr_15 */
771 host->send_addr(host, (page_addr >> 8) & 0xff, true);
777 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
778 * on how much oob the nand chip has. For 8bit ecc we need at least
779 * 26 bytes of oob data per 512 byte block.
781 static int get_eccsize(struct mtd_info *mtd)
783 int oobbytes_per_512 = 0;
785 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
787 if (oobbytes_per_512 < 26)
793 static void preset_v1_v2(struct mtd_info *mtd)
795 struct nand_chip *nand_chip = mtd->priv;
796 struct mxc_nand_host *host = nand_chip->priv;
797 uint16_t config1 = 0;
799 if (nand_chip->ecc.mode == NAND_ECC_HW)
800 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
803 config1 |= NFC_V2_CONFIG1_FP_INT;
805 if (nfc_is_v21() && mtd->writesize) {
806 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
808 host->eccsize = get_eccsize(mtd);
809 if (host->eccsize == 4)
810 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
812 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
817 writew(config1, NFC_V1_V2_CONFIG1);
818 /* preset operation */
820 /* Unlock the internal RAM Buffer */
821 writew(0x2, NFC_V1_V2_CONFIG);
823 /* Blocks to be unlocked */
825 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
826 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
827 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
828 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
829 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
830 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
831 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
832 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
833 } else if (nfc_is_v1()) {
834 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
835 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
839 /* Unlock Block Command for given address range */
840 writew(0x4, NFC_V1_V2_WRPROT);
843 static void preset_v3(struct mtd_info *mtd)
845 struct nand_chip *chip = mtd->priv;
846 struct mxc_nand_host *host = chip->priv;
847 uint32_t config2, config3;
850 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
851 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
852 WARN_ON(!(readl(NFC_V3_IPC) & NFC_V3_IPC_CACK));
854 /* Unlock the internal RAM Buffer */
855 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
858 /* Blocks to be unlocked */
859 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++)
860 writel(0x0 | (0xffff << 16),
861 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
863 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
864 NFC_V3_CONFIG2_2CMD_PHASES |
865 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
866 NFC_V3_CONFIG2_ST_CMD(0x70) |
867 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
869 if (chip->ecc.mode == NAND_ECC_HW)
870 config2 |= NFC_V3_CONFIG2_ECC_EN;
872 addr_phases = fls(chip->pagemask) >> 3;
874 if (mtd->writesize == 2048) {
875 config2 |= NFC_V3_CONFIG2_PS_2048;
876 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
877 } else if (mtd->writesize == 4096) {
878 config2 |= NFC_V3_CONFIG2_PS_4096;
879 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
881 config2 |= NFC_V3_CONFIG2_PS_512;
882 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
885 if (mtd->writesize) {
886 #if defined CONFIG_MX53
887 config2 |= MX53_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
889 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
891 host->eccsize = get_eccsize(mtd);
892 if (host->eccsize == 8)
893 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
896 writel(config2, NFC_V3_CONFIG2);
898 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
899 NFC_V3_CONFIG3_NO_SDMA |
900 NFC_V3_CONFIG3_RBB_MODE |
901 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
902 NFC_V3_CONFIG3_ADD_OP(0);
904 if (!(chip->options & NAND_BUSWIDTH_16))
905 config3 |= NFC_V3_CONFIG3_FW8;
907 writel(config3, NFC_V3_CONFIG3);
909 writel(0, NFC_V3_DELAY_LINE);
910 writel(0, NFC_V3_IPC);
913 /* Used by the upper layer to write command to NAND Flash for
914 * different operations to be carried out on NAND Flash */
915 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
916 int column, int page_addr)
918 struct nand_chip *nand_chip = mtd->priv;
919 struct mxc_nand_host *host = nand_chip->priv;
921 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
922 command, column, page_addr);
924 /* Reset command state information */
925 host->status_request = false;
927 /* Command pre-processing step */
931 host->send_cmd(host, command, false);
934 case NAND_CMD_STATUS:
936 host->status_request = true;
938 host->send_cmd(host, command, true);
939 mxc_do_addr_cycle(mtd, column, page_addr);
943 case NAND_CMD_READOOB:
944 if (command == NAND_CMD_READ0)
945 host->buf_start = column;
947 host->buf_start = column + mtd->writesize;
949 command = NAND_CMD_READ0; /* only READ0 is valid */
951 host->send_cmd(host, command, false);
952 mxc_do_addr_cycle(mtd, column, page_addr);
954 if (mtd->writesize > 512)
955 host->send_cmd(host, NAND_CMD_READSTART, true);
957 host->send_page(mtd, NFC_OUTPUT);
959 memcpy(host->data_buf, host->main_area0, mtd->writesize);
960 copy_spare(mtd, true);
964 if (column >= mtd->writesize)
965 /* call ourself to read a page */
966 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
968 host->buf_start = column;
970 host->send_cmd(host, command, false);
971 mxc_do_addr_cycle(mtd, column, page_addr);
974 case NAND_CMD_PAGEPROG:
975 memcpy(host->main_area0, host->data_buf, mtd->writesize);
976 copy_spare(mtd, false);
977 host->send_page(mtd, NFC_INPUT);
978 host->send_cmd(host, command, true);
979 mxc_do_addr_cycle(mtd, column, page_addr);
982 case NAND_CMD_READID:
983 host->send_cmd(host, command, true);
984 mxc_do_addr_cycle(mtd, column, page_addr);
985 host->send_read_id(host);
986 host->buf_start = column;
989 case NAND_CMD_ERASE1:
990 case NAND_CMD_ERASE2:
991 host->send_cmd(host, command, false);
992 mxc_do_addr_cycle(mtd, column, page_addr);
999 * The generic flash bbt decriptors overlap with our ecc
1000 * hardware, so define some i.MX specific ones.
1002 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1003 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1005 static struct nand_bbt_descr bbt_main_descr = {
1006 .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
1007 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1012 .pattern = bbt_pattern,
1015 static struct nand_bbt_descr bbt_mirror_descr = {
1016 .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
1017 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1022 .pattern = mirror_pattern,
1025 static void mxc_nand_chip_init(int devno)
1028 struct nand_chip *this;
1029 struct mtd_info *mtd = &nand_info[devno];
1030 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1032 /* allocate a minimal buffer for the read_id command */
1033 host->data_buf = malloc(16);
1034 if (!host->data_buf) {
1035 printk("Failed to allocate ID buffer\n");
1039 /* structures must be linked */
1043 mtd->name = DRIVER_NAME;
1045 /* 50 us command delay time */
1046 this->chip_delay = 5;
1049 this->dev_ready = mxc_nand_dev_ready;
1050 this->cmdfunc = mxc_nand_command;
1051 this->select_chip = mxc_nand_select_chip;
1052 this->read_byte = mxc_nand_read_byte;
1053 this->read_word = mxc_nand_read_word;
1054 this->write_buf = mxc_nand_write_buf;
1055 this->read_buf = mxc_nand_read_buf;
1056 this->verify_buf = mxc_nand_verify_buf;
1058 host->base = (void __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1063 host->main_area0 = host->base;
1065 if (nfc_is_v1() || nfc_is_v21()) {
1066 host->preset = preset_v1_v2;
1067 host->send_cmd = send_cmd_v1_v2;
1068 host->send_addr = send_addr_v1_v2;
1069 host->send_page = send_page_v1_v2;
1070 host->send_read_id = send_read_id_v1_v2;
1071 host->get_dev_status = get_dev_status_v1_v2;
1072 host->check_int = check_int_v1_v2;
1076 host->regs = host->base + 0x1e00;
1077 host->spare0 = host->base + 0x1000;
1078 host->spare_len = 64;
1079 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1080 oob_largepage = &nandv2_hw_eccoob_largepage;
1081 this->ecc.bytes = 9;
1082 } else if (nfc_is_v1()) {
1083 host->regs = host->base + 0xe00;
1084 host->spare0 = host->base + 0x800;
1085 host->spare_len = 16;
1086 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1087 oob_largepage = &nandv1_hw_eccoob_largepage;
1088 this->ecc.bytes = 3;
1090 } else if (nfc_is_v3_2()) {
1091 host->regs_ip = (void __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1092 host->regs_axi = host->base + 0x1e00;
1093 host->spare0 = host->base + 0x1000;
1094 host->spare_len = 64;
1095 host->preset = preset_v3;
1096 host->send_cmd = send_cmd_v3;
1097 host->send_addr = send_addr_v3;
1098 host->send_page = send_page_v3;
1099 host->send_read_id = send_read_id_v3;
1100 host->check_int = check_int_v3;
1101 host->get_dev_status = get_dev_status_v3;
1102 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1103 oob_largepage = &nandv2_hw_eccoob_largepage;
1104 this->ecc.strength = 4;
1108 this->ecc.size = 512;
1109 this->ecc.layout = oob_smallpage;
1111 #ifdef CONFIG_MXC_NAND_HWECC
1112 this->ecc.calculate = mxc_nand_calculate_ecc;
1113 this->ecc.hwctl = mxc_nand_enable_hwecc;
1115 this->ecc.correct = mxc_nand_correct_data_v1;
1117 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1118 this->ecc.mode = NAND_ECC_HW;
1120 this->ecc.mode = NAND_ECC_SOFT;
1122 /* NAND bus width determines access funtions used by upper layer */
1123 if (is_16bit_nand())
1124 this->options |= NAND_BUSWIDTH_16;
1126 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1127 this->bbt_options |= NAND_BBT_USE_FLASH;
1128 this->bbt_td = &bbt_main_descr;
1129 this->bbt_md = &bbt_mirror_descr;
1130 this->bbt_td->options |= NAND_BBT_CREATE;
1131 this->bbt_md->options |= NAND_BBT_CREATE;
1134 /* first scan to find the device and get the page size */
1135 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1139 host->data_buf = realloc(host->data_buf,
1140 mtd->writesize + mtd->oobsize);
1141 if (!host->data_buf) {
1142 printk("Failed to allocate data buffer of %u byte\n",
1143 mtd->writesize + mtd->oobsize);
1146 pr_debug("Allocated %u byte data buffer\n",
1147 mtd->writesize + mtd->oobsize);
1149 /* Call preset again, with correct writesize this time */
1152 if (mtd->writesize == 2048)
1153 this->ecc.layout = oob_largepage;
1154 if (nfc_is_v21() && mtd->writesize == 4096)
1155 this->ecc.layout = &nandv2_hw_eccoob_4k;
1157 /* second phase scan */
1158 err = nand_scan_tail(mtd);
1160 printk("Nand scan failed: %d\n", err);
1164 err = nand_register(devno);
1169 void board_nand_init(void)
1173 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1174 mxc_nand_chip_init(i);