drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *
   8  *      Additional technical information is available on
   9  *      http://www.linux-mtd.infradead.org/doc/nand.html
  10  *
  11  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  12  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  13  *
  14  *  Credits:
  15  *      David Woodhouse for adding multichip support
  16  *
  17  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  18  *      rework for 2K page size chips
  19  *
  20  *  TODO:
  21  *      Enable cached programming for 2k page size chips
  22  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  23  *      if we have HW ECC support.
  24  *      BBT table is not serialized, has to be fixed
  25  *
  26  * This program is free software; you can redistribute it and/or modify
  27  * it under the terms of the GNU General Public License version 2 as
  28  * published by the Free Software Foundation.
  29  *
  30  */
  31
  32 #ifndef __UBOOT__
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51 #else
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53 #include <common.h>
  54 #include <malloc.h>
  55 #include <watchdog.h>
  56 #include <linux/err.h>
  57 #include <linux/compat.h>
  58 #include <linux/mtd/mtd.h>
  59 #include <linux/mtd/nand.h>
  60 #include <linux/mtd/nand_ecc.h>
  61 #include <linux/mtd/nand_bch.h>
  62 #ifdef CONFIG_MTD_PARTITIONS
  63 #include <linux/mtd/partitions.h>
  64 #endif
  65 #include <asm/io.h>
  66 #include <asm/errno.h>
  67
  68 /*
  69  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  70  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  71  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  72  * which is greater than (max NAND reset time / NAND status read time).
  73  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  74  */
  75 #ifndef CONFIG_SYS_NAND_RESET_CNT
  76 #define CONFIG_SYS_NAND_RESET_CNT 200000
  77 #endif
  78
  79 static bool is_module_text_address(unsigned long addr) {return 0;}
  80 #endif
  81
  82 /* Define default oob placement schemes for large and small page devices */
  83 static struct nand_ecclayout nand_oob_8 = {
  84         .eccbytes = 3,
  85         .eccpos = {0, 1, 2},
  86         .oobfree = {
  87                 {.offset = 3,
  88                  .length = 2},
  89                 {.offset = 6,
  90                  .length = 2} }
  91 };
  92
  93 static struct nand_ecclayout nand_oob_16 = {
  94         .eccbytes = 6,
  95         .eccpos = {0, 1, 2, 3, 6, 7},
  96         .oobfree = {
  97                 {.offset = 8,
  98                  . length = 8} }
  99 };
 100
 101 static struct nand_ecclayout nand_oob_64 = {
 102         .eccbytes = 24,
 103         .eccpos = {
 104                    40, 41, 42, 43, 44, 45, 46, 47,
 105                    48, 49, 50, 51, 52, 53, 54, 55,
 106                    56, 57, 58, 59, 60, 61, 62, 63},
 107         .oobfree = {
 108                 {.offset = 2,
 109                  .length = 38} }
 110 };
 111
 112 static struct nand_ecclayout nand_oob_128 = {
 113         .eccbytes = 48,
 114         .eccpos = {
 115                    80, 81, 82, 83, 84, 85, 86, 87,
 116                    88, 89, 90, 91, 92, 93, 94, 95,
 117                    96, 97, 98, 99, 100, 101, 102, 103,
 118                    104, 105, 106, 107, 108, 109, 110, 111,
 119                    112, 113, 114, 115, 116, 117, 118, 119,
 120                    120, 121, 122, 123, 124, 125, 126, 127},
 121         .oobfree = {
 122                 {.offset = 2,
 123                  .length = 78} }
 124 };
 125
 126 static int nand_get_device(struct mtd_info *mtd, int new_state);
 127
 128 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 129                              struct mtd_oob_ops *ops);
 130
 131 /*
 132  * For devices which display every fart in the system on a separate LED. Is
 133  * compiled away when LED support is disabled.
 134  */
 135 DEFINE_LED_TRIGGER(nand_led_trigger);
 136
 137 static int check_offs_len(struct mtd_info *mtd,
 138                                         loff_t ofs, uint64_t len)
 139 {
 140         struct nand_chip *chip = mtd->priv;
 141         int ret = 0;
 142
 143         /* Start address must align on block boundary */
 144         if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
 145                 pr_debug("%s: unaligned address\n", __func__);
 146                 ret = -EINVAL;
 147         }
 148
 149         /* Length must align on block boundary */
 150         if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
 151                 pr_debug("%s: length not block aligned\n", __func__);
 152                 ret = -EINVAL;
 153         }
 154
 155         return ret;
 156 }
 157
 158 /**
 159  * nand_release_device - [GENERIC] release chip
 160  * @mtd: MTD device structure
 161  *
 162  * Release chip lock and wake up anyone waiting on the device.
 163  */
 164 static void nand_release_device(struct mtd_info *mtd)
 165 {
 166         struct nand_chip *chip = mtd->priv;
 167
 168 #ifndef __UBOOT__
 169         /* Release the controller and the chip */
 170         spin_lock(&chip->controller->lock);
 171         chip->controller->active = NULL;
 172         chip->state = FL_READY;
 173         wake_up(&chip->controller->wq);
 174         spin_unlock(&chip->controller->lock);
 175 #else
 176         /* De-select the NAND device */
 177         chip->select_chip(mtd, -1);
 178 #endif
 179 }
 180
 181 /**
 182  * nand_read_byte - [DEFAULT] read one byte from the chip
 183  * @mtd: MTD device structure
 184  *
 185  * Default read function for 8bit buswidth
 186  */
 187 #ifndef __UBOOT__
 188 static uint8_t nand_read_byte(struct mtd_info *mtd)
 189 #else
 190 uint8_t nand_read_byte(struct mtd_info *mtd)
 191 #endif
 192 {
 193         struct nand_chip *chip = mtd->priv;
 194         return readb(chip->IO_ADDR_R);
 195 }
 196
 197 /**
 198  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 199  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 200  * @mtd: MTD device structure
 201  *
 202  * Default read function for 16bit buswidth with endianness conversion.
 203  *
 204  */
 205 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 206 {
 207         struct nand_chip *chip = mtd->priv;
 208         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 209 }
 210
 211 /**
 212  * nand_read_word - [DEFAULT] read one word from the chip
 213  * @mtd: MTD device structure
 214  *
 215  * Default read function for 16bit buswidth without endianness conversion.
 216  */
 217 static u16 nand_read_word(struct mtd_info *mtd)
 218 {
 219         struct nand_chip *chip = mtd->priv;
 220         return readw(chip->IO_ADDR_R);
 221 }
 222
 223 /**
 224  * nand_select_chip - [DEFAULT] control CE line
 225  * @mtd: MTD device structure
 226  * @chipnr: chipnumber to select, -1 for deselect
 227  *
 228  * Default select function for 1 chip devices.
 229  */
 230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 231 {
 232         struct nand_chip *chip = mtd->priv;
 233
 234         switch (chipnr) {
 235         case -1:
 236                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 237                 break;
 238         case 0:
 239                 break;
 240
 241         default:
 242                 BUG();
 243         }
 244 }
 245
 246 /**
 247  * nand_write_byte - [DEFAULT] write single byte to chip
 248  * @mtd: MTD device structure
 249  * @byte: value to write
 250  *
 251  * Default function to write a byte to I/O[7:0]
 252  */
 253 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
 254 {
 255         struct nand_chip *chip = mtd->priv;
 256
 257         chip->write_buf(mtd, &byte, 1);
 258 }
 259
 260 /**
 261  * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
 262  * @mtd: MTD device structure
 263  * @byte: value to write
 264  *
 265  * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
 266  */
 267 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
 268 {
 269         struct nand_chip *chip = mtd->priv;
 270         uint16_t word = byte;
 271
 272         /*
 273          * It's not entirely clear what should happen to I/O[15:8] when writing
 274          * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
 275          *
 276          *    When the host supports a 16-bit bus width, only data is
 277          *    transferred at the 16-bit width. All address and command line
 278          *    transfers shall use only the lower 8-bits of the data bus. During
 279          *    command transfers, the host may place any value on the upper
 280          *    8-bits of the data bus. During address transfers, the host shall
 281          *    set the upper 8-bits of the data bus to 00h.
 282          *
 283          * One user of the write_byte callback is nand_onfi_set_features. The
 284          * four parameters are specified to be written to I/O[7:0], but this is
 285          * neither an address nor a command transfer. Let's assume a 0 on the
 286          * upper I/O lines is OK.
 287          */
 288         chip->write_buf(mtd, (uint8_t *)&word, 2);
 289 }
 290
 291 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
 292 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
 293 {
 294         int i;
 295
 296         for (i = 0; i < len; i++)
 297                 writeb(buf[i], addr);
 298 }
 299 static void ioread8_rep(void *addr, uint8_t *buf, int len)
 300 {
 301         int i;
 302
 303         for (i = 0; i < len; i++)
 304                 buf[i] = readb(addr);
 305 }
 306
 307 static void ioread16_rep(void *addr, void *buf, int len)
 308 {
 309         int i;
 310         u16 *p = (u16 *) buf;
 311
 312         for (i = 0; i < len; i++)
 313                 p[i] = readw(addr);
 314 }
 315
 316 static void iowrite16_rep(void *addr, void *buf, int len)
 317 {
 318         int i;
 319         u16 *p = (u16 *) buf;
 320
 321         for (i = 0; i < len; i++)
 322                 writew(p[i], addr);
 323 }
 324 #endif
 325
 326 /**
 327  * nand_write_buf - [DEFAULT] write buffer to chip
 328  * @mtd: MTD device structure
 329  * @buf: data buffer
 330  * @len: number of bytes to write
 331  *
 332  * Default write function for 8bit buswidth.
 333  */
 334 #ifndef __UBOOT__
 335 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 336 #else
 337 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 338 #endif
 339 {
 340         struct nand_chip *chip = mtd->priv;
 341
 342         iowrite8_rep(chip->IO_ADDR_W, buf, len);
 343 }
 344
 345 /**
 346  * nand_read_buf - [DEFAULT] read chip data into buffer
 347  * @mtd: MTD device structure
 348  * @buf: buffer to store date
 349  * @len: number of bytes to read
 350  *
 351  * Default read function for 8bit buswidth.
 352  */
 353 #ifndef __UBOOT__
 354 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 355 #else
 356 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 357 #endif
 358 {
 359         struct nand_chip *chip = mtd->priv;
 360
 361         ioread8_rep(chip->IO_ADDR_R, buf, len);
 362 }
 363
 364 #ifdef __UBOOT__
 365 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 366 /**
 367  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 368  * @mtd: MTD device structure
 369  * @buf: buffer containing the data to compare
 370  * @len: number of bytes to compare
 371  *
 372  * Default verify function for 8bit buswidth.
 373  */
 374 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 375 {
 376         int i;
 377         struct nand_chip *chip = mtd->priv;
 378
 379         for (i = 0; i < len; i++)
 380                 if (buf[i] != readb(chip->IO_ADDR_R))
 381                         return -EFAULT;
 382         return 0;
 383 }
 384
 385 /**
 386  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 387  * @mtd: MTD device structure
 388  * @buf: buffer containing the data to compare
 389  * @len: number of bytes to compare
 390  *
 391  * Default verify function for 16bit buswidth.
 392  */
 393 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 394 {
 395         int i;
 396         struct nand_chip *chip = mtd->priv;
 397         u16 *p = (u16 *) buf;
 398         len >>= 1;
 399
 400         for (i = 0; i < len; i++)
 401                 if (p[i] != readw(chip->IO_ADDR_R))
 402                         return -EFAULT;
 403
 404         return 0;
 405 }
 406 #endif
 407 #endif
 408
 409 /**
 410  * nand_write_buf16 - [DEFAULT] write buffer to chip
 411  * @mtd: MTD device structure
 412  * @buf: data buffer
 413  * @len: number of bytes to write
 414  *
 415  * Default write function for 16bit buswidth.
 416  */
 417 #ifndef __UBOOT__
 418 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 419 #else
 420 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 421 #endif
 422 {
 423         struct nand_chip *chip = mtd->priv;
 424         u16 *p = (u16 *) buf;
 425
 426         iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
 427 }
 428
 429 /**
 430  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 431  * @mtd: MTD device structure
 432  * @buf: buffer to store date
 433  * @len: number of bytes to read
 434  *
 435  * Default read function for 16bit buswidth.
 436  */
 437 #ifndef __UBOOT__
 438 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 439 #else
 440 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 441 #endif
 442 {
 443         struct nand_chip *chip = mtd->priv;
 444         u16 *p = (u16 *) buf;
 445
 446         ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
 447 }
 448
 449 /**
 450  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 451  * @mtd: MTD device structure
 452  * @ofs: offset from device start
 453  * @getchip: 0, if the chip is already selected
 454  *
 455  * Check, if the block is bad.
 456  */
 457 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 458 {
 459         int page, chipnr, res = 0, i = 0;
 460         struct nand_chip *chip = mtd->priv;
 461         u16 bad;
 462
 463         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 464                 ofs += mtd->erasesize - mtd->writesize;
 465
 466         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 467
 468         if (getchip) {
 469                 chipnr = (int)(ofs >> chip->chip_shift);
 470
 471                 nand_get_device(mtd, FL_READING);
 472
 473                 /* Select the NAND device */
 474                 chip->select_chip(mtd, chipnr);
 475         }
 476
 477         do {
 478                 if (chip->options & NAND_BUSWIDTH_16) {
 479                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 480                                         chip->badblockpos & 0xFE, page);
 481                         bad = cpu_to_le16(chip->read_word(mtd));
 482                         if (chip->badblockpos & 0x1)
 483                                 bad >>= 8;
 484                         else
 485                                 bad &= 0xFF;
 486                 } else {
 487                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 488                                         page);
 489                         bad = chip->read_byte(mtd);
 490                 }
 491
 492                 if (likely(chip->badblockbits == 8))
 493                         res = bad != 0xFF;
 494                 else
 495                         res = hweight8(bad) < chip->badblockbits;
 496                 ofs += mtd->writesize;
 497                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 498                 i++;
 499         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 500
 501         if (getchip) {
 502                 chip->select_chip(mtd, -1);
 503                 nand_release_device(mtd);
 504         }
 505
 506         return res;
 507 }
 508
 509 /**
 510  * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
 511  * @mtd: MTD device structure
 512  * @ofs: offset from device start
 513  *
 514  * This is the default implementation, which can be overridden by a hardware
 515  * specific driver. It provides the details for writing a bad block marker to a
 516  * block.
 517  */
 518 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 519 {
 520         struct nand_chip *chip = mtd->priv;
 521         struct mtd_oob_ops ops;
 522         uint8_t buf[2] = { 0, 0 };
 523         int ret = 0, res, i = 0;
 524
 525         ops.datbuf = NULL;
 526         ops.oobbuf = buf;
 527         ops.ooboffs = chip->badblockpos;
 528         if (chip->options & NAND_BUSWIDTH_16) {
 529                 ops.ooboffs &= ~0x01;
 530                 ops.len = ops.ooblen = 2;
 531         } else {
 532                 ops.len = ops.ooblen = 1;
 533         }
 534         ops.mode = MTD_OPS_PLACE_OOB;
 535
 536         /* Write to first/last page(s) if necessary */
 537         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 538                 ofs += mtd->erasesize - mtd->writesize;
 539         do {
 540                 res = nand_do_write_oob(mtd, ofs, &ops);
 541                 if (!ret)
 542                         ret = res;
 543
 544                 i++;
 545                 ofs += mtd->writesize;
 546         } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 547
 548         return ret;
 549 }
 550
 551 /**
 552  * nand_block_markbad_lowlevel - mark a block bad
 553  * @mtd: MTD device structure
 554  * @ofs: offset from device start
 555  *
 556  * This function performs the generic NAND bad block marking steps (i.e., bad
 557  * block table(s) and/or marker(s)). We only allow the hardware driver to
 558  * specify how to write bad block markers to OOB (chip->block_markbad).
 559  *
 560  * We try operations in the following order:
 561  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 562  *  (2) write bad block marker to OOB area of affected block (unless flag
 563  *      NAND_BBT_NO_OOB_BBM is present)
 564  *  (3) update the BBT
 565  * Note that we retain the first error encountered in (2) or (3), finish the
 566  * procedures, and dump the error in the end.
 567 */
 568 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 569 {
 570         struct nand_chip *chip = mtd->priv;
 571         int res, ret = 0;
 572
 573         if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
 574                 struct erase_info einfo;
 575
 576                 /* Attempt erase before marking OOB */
 577                 memset(&einfo, 0, sizeof(einfo));
 578                 einfo.mtd = mtd;
 579                 einfo.addr = ofs;
 580                 einfo.len = 1ULL << chip->phys_erase_shift;
 581                 nand_erase_nand(mtd, &einfo, 0);
 582
 583                 /* Write bad block marker to OOB */
 584                 nand_get_device(mtd, FL_WRITING);
 585                 ret = chip->block_markbad(mtd, ofs);
 586                 nand_release_device(mtd);
 587         }
 588
 589         /* Mark block bad in BBT */
 590         if (chip->bbt) {
 591                 res = nand_markbad_bbt(mtd, ofs);
 592                 if (!ret)
 593                         ret = res;
 594         }
 595
 596         if (!ret)
 597                 mtd->ecc_stats.badblocks++;
 598
 599         return ret;
 600 }
 601
 602 /**
 603  * nand_check_wp - [GENERIC] check if the chip is write protected
 604  * @mtd: MTD device structure
 605  *
 606  * Check, if the device is write protected. The function expects, that the
 607  * device is already selected.
 608  */
 609 static int nand_check_wp(struct mtd_info *mtd)
 610 {
 611         struct nand_chip *chip = mtd->priv;
 612
 613         /* Broken xD cards report WP despite being writable */
 614         if (chip->options & NAND_BROKEN_XD)
 615                 return 0;
 616
 617         /* Check the WP bit */
 618         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 619         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 620 }
 621
 622 /**
 623  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 624  * @mtd: MTD device structure
 625  * @ofs: offset from device start
 626  * @getchip: 0, if the chip is already selected
 627  * @allowbbt: 1, if its allowed to access the bbt area
 628  *
 629  * Check, if the block is bad. Either by reading the bad block table or
 630  * calling of the scan function.
 631  */
 632 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 633                                int allowbbt)
 634 {
 635         struct nand_chip *chip = mtd->priv;
 636
 637         if (!(chip->options & NAND_SKIP_BBTSCAN) &&
 638             !(chip->options & NAND_BBT_SCANNED)) {
 639                 chip->options |= NAND_BBT_SCANNED;
 640                 chip->scan_bbt(mtd);
 641         }
 642
 643         if (!chip->bbt)
 644                 return chip->block_bad(mtd, ofs, getchip);
 645
 646         /* Return info from the table */
 647         return nand_isbad_bbt(mtd, ofs, allowbbt);
 648 }
 649
 650 #ifndef __UBOOT__
 651 /**
 652  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 653  * @mtd: MTD device structure
 654  * @timeo: Timeout
 655  *
 656  * Helper function for nand_wait_ready used when needing to wait in interrupt
 657  * context.
 658  */
 659 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 660 {
 661         struct nand_chip *chip = mtd->priv;
 662         int i;
 663
 664         /* Wait for the device to get ready */
 665         for (i = 0; i < timeo; i++) {
 666                 if (chip->dev_ready(mtd))
 667                         break;
 668                 touch_softlockup_watchdog();
 669                 mdelay(1);
 670         }
 671 }
 672 #endif
 673
 674 /* Wait for the ready pin, after a command. The timeout is caught later. */
 675 void nand_wait_ready(struct mtd_info *mtd)
 676 {
 677         struct nand_chip *chip = mtd->priv;
 678 #ifndef __UBOOT__
 679         unsigned long timeo = jiffies + msecs_to_jiffies(20);
 680
 681         /* 400ms timeout */
 682         if (in_interrupt() || oops_in_progress)
 683                 return panic_nand_wait_ready(mtd, 400);
 684
 685         led_trigger_event(nand_led_trigger, LED_FULL);
 686         /* Wait until command is processed or timeout occurs */
 687         do {
 688                 if (chip->dev_ready(mtd))
 689                         break;
 690                 touch_softlockup_watchdog();
 691         } while (time_before(jiffies, timeo));
 692         led_trigger_event(nand_led_trigger, LED_OFF);
 693 #else
 694         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 695         u32 time_start;
 696
 697         time_start = get_timer(0);
 698         /* Wait until command is processed or timeout occurs */
 699         while (get_timer(time_start) < timeo) {
 700                 if (chip->dev_ready)
 701                         if (chip->dev_ready(mtd))
 702                                 break;
 703         }
 704 #endif
 705 }
 706 EXPORT_SYMBOL_GPL(nand_wait_ready);
 707
 708 /**
 709  * nand_command - [DEFAULT] Send command to NAND device
 710  * @mtd: MTD device structure
 711  * @command: the command to be sent
 712  * @column: the column address for this command, -1 if none
 713  * @page_addr: the page address for this command, -1 if none
 714  *
 715  * Send command to NAND device. This function is used for small page devices
 716  * (512 Bytes per page).
 717  */
 718 static void nand_command(struct mtd_info *mtd, unsigned int command,
 719                          int column, int page_addr)
 720 {
 721         register struct nand_chip *chip = mtd->priv;
 722         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 723         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 724
 725         /* Write out the command to the device */
 726         if (command == NAND_CMD_SEQIN) {
 727                 int readcmd;
 728
 729                 if (column >= mtd->writesize) {
 730                         /* OOB area */
 731                         column -= mtd->writesize;
 732                         readcmd = NAND_CMD_READOOB;
 733                 } else if (column < 256) {
 734                         /* First 256 bytes --> READ0 */
 735                         readcmd = NAND_CMD_READ0;
 736                 } else {
 737                         column -= 256;
 738                         readcmd = NAND_CMD_READ1;
 739                 }
 740                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 741                 ctrl &= ~NAND_CTRL_CHANGE;
 742         }
 743         chip->cmd_ctrl(mtd, command, ctrl);
 744
 745         /* Address cycle, when necessary */
 746         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 747         /* Serially input address */
 748         if (column != -1) {
 749                 /* Adjust columns for 16 bit buswidth */
 750                 if (chip->options & NAND_BUSWIDTH_16 &&
 751                                 !nand_opcode_8bits(command))
 752                         column >>= 1;
 753                 chip->cmd_ctrl(mtd, column, ctrl);
 754                 ctrl &= ~NAND_CTRL_CHANGE;
 755         }
 756         if (page_addr != -1) {
 757                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 758                 ctrl &= ~NAND_CTRL_CHANGE;
 759                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 760                 /* One more address cycle for devices > 32MiB */
 761                 if (chip->chipsize > (32 << 20))
 762                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 763         }
 764         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 765
 766         /*
 767          * Program and erase have their own busy handlers status and sequential
 768          * in needs no delay
 769          */
 770         switch (command) {
 771
 772         case NAND_CMD_PAGEPROG:
 773         case NAND_CMD_ERASE1:
 774         case NAND_CMD_ERASE2:
 775         case NAND_CMD_SEQIN:
 776         case NAND_CMD_STATUS:
 777                 return;
 778
 779         case NAND_CMD_RESET:
 780                 if (chip->dev_ready)
 781                         break;
 782                 udelay(chip->chip_delay);
 783                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 784                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 785                 chip->cmd_ctrl(mtd,
 786                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 787                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 788                         (rst_sts_cnt--));
 789                 return;
 790
 791                 /* This applies to read commands */
 792         default:
 793                 /*
 794                  * If we don't have access to the busy pin, we apply the given
 795                  * command delay
 796                  */
 797                 if (!chip->dev_ready) {
 798                         udelay(chip->chip_delay);
 799                         return;
 800                 }
 801         }
 802         /*
 803          * Apply this short delay always to ensure that we do wait tWB in
 804          * any case on any machine.
 805          */
 806         ndelay(100);
 807
 808         nand_wait_ready(mtd);
 809 }
 810
 811 /**
 812  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 813  * @mtd: MTD device structure
 814  * @command: the command to be sent
 815  * @column: the column address for this command, -1 if none
 816  * @page_addr: the page address for this command, -1 if none
 817  *
 818  * Send command to NAND device. This is the version for the new large page
 819  * devices. We don't have the separate regions as we have in the small page
 820  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 821  */
 822 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 823                             int column, int page_addr)
 824 {
 825         register struct nand_chip *chip = mtd->priv;
 826         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 827
 828         /* Emulate NAND_CMD_READOOB */
 829         if (command == NAND_CMD_READOOB) {
 830                 column += mtd->writesize;
 831                 command = NAND_CMD_READ0;
 832         }
 833
 834         /* Command latch cycle */
 835         chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 836
 837         if (column != -1 || page_addr != -1) {
 838                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 839
 840                 /* Serially input address */
 841                 if (column != -1) {
 842                         /* Adjust columns for 16 bit buswidth */
 843                         if (chip->options & NAND_BUSWIDTH_16 &&
 844                                         !nand_opcode_8bits(command))
 845                                 column >>= 1;
 846                         chip->cmd_ctrl(mtd, column, ctrl);
 847                         ctrl &= ~NAND_CTRL_CHANGE;
 848                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 849                 }
 850                 if (page_addr != -1) {
 851                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 852                         chip->cmd_ctrl(mtd, page_addr >> 8,
 853                                        NAND_NCE | NAND_ALE);
 854                         /* One more address cycle for devices > 128MiB */
 855                         if (chip->chipsize > (128 << 20))
 856                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 857                                                NAND_NCE | NAND_ALE);
 858                 }
 859         }
 860         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 861
 862         /*
 863          * Program and erase have their own busy handlers status, sequential
 864          * in, and deplete1 need no delay.
 865          */
 866         switch (command) {
 867
 868         case NAND_CMD_CACHEDPROG:
 869         case NAND_CMD_PAGEPROG:
 870         case NAND_CMD_ERASE1:
 871         case NAND_CMD_ERASE2:
 872         case NAND_CMD_SEQIN:
 873         case NAND_CMD_RNDIN:
 874         case NAND_CMD_STATUS:
 875                 return;
 876
 877         case NAND_CMD_RESET:
 878                 if (chip->dev_ready)
 879                         break;
 880                 udelay(chip->chip_delay);
 881                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 882                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 883                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 884                                NAND_NCE | NAND_CTRL_CHANGE);
 885                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 886                         (rst_sts_cnt--));
 887                 return;
 888
 889         case NAND_CMD_RNDOUT:
 890                 /* No ready / busy check necessary */
 891                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 892                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 893                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 894                                NAND_NCE | NAND_CTRL_CHANGE);
 895                 return;
 896
 897         case NAND_CMD_READ0:
 898                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 899                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 900                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 901                                NAND_NCE | NAND_CTRL_CHANGE);
 902
 903                 /* This applies to read commands */
 904         default:
 905                 /*
 906                  * If we don't have access to the busy pin, we apply the given
 907                  * command delay.
 908                  */
 909                 if (!chip->dev_ready) {
 910                         udelay(chip->chip_delay);
 911                         return;
 912                 }
 913         }
 914
 915         /*
 916          * Apply this short delay always to ensure that we do wait tWB in
 917          * any case on any machine.
 918          */
 919         ndelay(100);
 920
 921         nand_wait_ready(mtd);
 922 }
 923
 924 /**
 925  * panic_nand_get_device - [GENERIC] Get chip for selected access
 926  * @chip: the nand chip descriptor
 927  * @mtd: MTD device structure
 928  * @new_state: the state which is requested
 929  *
 930  * Used when in panic, no locks are taken.
 931  */
 932 static void panic_nand_get_device(struct nand_chip *chip,
 933                       struct mtd_info *mtd, int new_state)
 934 {
 935         /* Hardware controller shared among independent devices */
 936         chip->controller->active = chip;
 937         chip->state = new_state;
 938 }
 939
 940 /**
 941  * nand_get_device - [GENERIC] Get chip for selected access
 942  * @mtd: MTD device structure
 943  * @new_state: the state which is requested
 944  *
 945  * Get the device and lock it for exclusive access
 946  */
 947 static int
 948 nand_get_device(struct mtd_info *mtd, int new_state)
 949 {
 950         struct nand_chip *chip = mtd->priv;
 951 #ifndef __UBOOT__
 952         spinlock_t *lock = &chip->controller->lock;
 953         wait_queue_head_t *wq = &chip->controller->wq;
 954         DECLARE_WAITQUEUE(wait, current);
 955 retry:
 956         spin_lock(lock);
 957
 958         /* Hardware controller shared among independent devices */
 959         if (!chip->controller->active)
 960                 chip->controller->active = chip;
 961
 962         if (chip->controller->active == chip && chip->state == FL_READY) {
 963                 chip->state = new_state;
 964                 spin_unlock(lock);
 965                 return 0;
 966         }
 967         if (new_state == FL_PM_SUSPENDED) {
 968                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 969                         chip->state = FL_PM_SUSPENDED;
 970                         spin_unlock(lock);
 971                         return 0;
 972                 }
 973         }
 974         set_current_state(TASK_UNINTERRUPTIBLE);
 975         add_wait_queue(wq, &wait);
 976         spin_unlock(lock);
 977         schedule();
 978         remove_wait_queue(wq, &wait);
 979         goto retry;
 980 #else
 981         chip->state = new_state;
 982         return 0;
 983 #endif
 984 }
 985
 986 /**
 987  * panic_nand_wait - [GENERIC] wait until the command is done
 988  * @mtd: MTD device structure
 989  * @chip: NAND chip structure
 990  * @timeo: timeout
 991  *
 992  * Wait for command done. This is a helper function for nand_wait used when
 993  * we are in interrupt context. May happen when in panic and trying to write
 994  * an oops through mtdoops.
 995  */
 996 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 997                             unsigned long timeo)
 998 {
 999         int i;
1000         for (i = 0; i < timeo; i++) {
1001                 if (chip->dev_ready) {
1002                         if (chip->dev_ready(mtd))
1003                                 break;
1004                 } else {
1005                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
1006                                 break;
1007                 }
1008                 mdelay(1);
1009         }
1010 }
1011
1012 /**
1013  * nand_wait - [DEFAULT] wait until the command is done
1014  * @mtd: MTD device structure
1015  * @chip: NAND chip structure
1016  *
1017  * Wait for command done. This applies to erase and program only. Erase can
1018  * take up to 400ms and program up to 20ms according to general NAND and
1019  * SmartMedia specs.
1020  */
1021 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1022 {
1023
1024         int status, state = chip->state;
1025         unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1026
1027         led_trigger_event(nand_led_trigger, LED_FULL);
1028
1029         /*
1030          * Apply this short delay always to ensure that we do wait tWB in any
1031          * case on any machine.
1032          */
1033         ndelay(100);
1034
1035         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1036
1037 #ifndef __UBOOT__
1038         if (in_interrupt() || oops_in_progress)
1039                 panic_nand_wait(mtd, chip, timeo);
1040         else {
1041                 timeo = jiffies + msecs_to_jiffies(timeo);
1042                 while (time_before(jiffies, timeo)) {
1043                         if (chip->dev_ready) {
1044                                 if (chip->dev_ready(mtd))
1045                                         break;
1046                         } else {
1047                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1048                                         break;
1049                         }
1050                         cond_resched();
1051                 }
1052         }
1053 #else
1054         u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1055         u32 time_start;
1056
1057         time_start = get_timer(0);
1058         while (get_timer(time_start) < timer) {
1059                 if (chip->dev_ready) {
1060                         if (chip->dev_ready(mtd))
1061                                 break;
1062                 } else {
1063                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
1064                                 break;
1065                 }
1066         }
1067 #endif
1068 #ifdef PPCHAMELON_NAND_TIMER_HACK
1069         time_start = get_timer(0);
1070         while (get_timer(time_start) < 10)
1071                 ;
1072 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
1073         led_trigger_event(nand_led_trigger, LED_OFF);
1074
1075         status = (int)chip->read_byte(mtd);
1076         /* This can happen if in case of timeout or buggy dev_ready */
1077         WARN_ON(!(status & NAND_STATUS_READY));
1078         return status;
1079 }
1080
1081 #ifndef __UBOOT__
1082 /**
1083  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1084  * @mtd: mtd info
1085  * @ofs: offset to start unlock from
1086  * @len: length to unlock
1087  * @invert: when = 0, unlock the range of blocks within the lower and
1088  *                    upper boundary address
1089  *          when = 1, unlock the range of blocks outside the boundaries
1090  *                    of the lower and upper boundary address
1091  *
1092  * Returs unlock status.
1093  */
1094 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1095                                         uint64_t len, int invert)
1096 {
1097         int ret = 0;
1098         int status, page;
1099         struct nand_chip *chip = mtd->priv;
1100
1101         /* Submit address of first page to unlock */
1102         page = ofs >> chip->page_shift;
1103         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1104
1105         /* Submit address of last page to unlock */
1106         page = (ofs + len) >> chip->page_shift;
1107         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1108                                 (page | invert) & chip->pagemask);
1109
1110         /* Call wait ready function */
1111         status = chip->waitfunc(mtd, chip);
1112         /* See if device thinks it succeeded */
1113         if (status & NAND_STATUS_FAIL) {
1114                 pr_debug("%s: error status = 0x%08x\n",
1115                                         __func__, status);
1116                 ret = -EIO;
1117         }
1118
1119         return ret;
1120 }
1121
1122 /**
1123  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1124  * @mtd: mtd info
1125  * @ofs: offset to start unlock from
1126  * @len: length to unlock
1127  *
1128  * Returns unlock status.
1129  */
1130 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1131 {
1132         int ret = 0;
1133         int chipnr;
1134         struct nand_chip *chip = mtd->priv;
1135
1136         pr_debug("%s: start = 0x%012llx, len = %llu\n",
1137                         __func__, (unsigned long long)ofs, len);
1138
1139         if (check_offs_len(mtd, ofs, len))
1140                 ret = -EINVAL;
1141
1142         /* Align to last block address if size addresses end of the device */
1143         if (ofs + len == mtd->size)
1144                 len -= mtd->erasesize;
1145
1146         nand_get_device(mtd, FL_UNLOCKING);
1147
1148         /* Shift to get chip number */
1149         chipnr = ofs >> chip->chip_shift;
1150
1151         chip->select_chip(mtd, chipnr);
1152
1153         /* Check, if it is write protected */
1154         if (nand_check_wp(mtd)) {
1155                 pr_debug("%s: device is write protected!\n",
1156                                         __func__);
1157                 ret = -EIO;
1158                 goto out;
1159         }
1160
1161         ret = __nand_unlock(mtd, ofs, len, 0);
1162
1163 out:
1164         chip->select_chip(mtd, -1);
1165         nand_release_device(mtd);
1166
1167         return ret;
1168 }
1169 EXPORT_SYMBOL(nand_unlock);
1170
1171 /**
1172  * nand_lock - [REPLACEABLE] locks all blocks present in the device
1173  * @mtd: mtd info
1174  * @ofs: offset to start unlock from
1175  * @len: length to unlock
1176  *
1177  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1178  * have this feature, but it allows only to lock all blocks, not for specified
1179  * range for block. Implementing 'lock' feature by making use of 'unlock', for
1180  * now.
1181  *
1182  * Returns lock status.
1183  */
1184 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1185 {
1186         int ret = 0;
1187         int chipnr, status, page;
1188         struct nand_chip *chip = mtd->priv;
1189
1190         pr_debug("%s: start = 0x%012llx, len = %llu\n",
1191                         __func__, (unsigned long long)ofs, len);
1192
1193         if (check_offs_len(mtd, ofs, len))
1194                 ret = -EINVAL;
1195
1196         nand_get_device(mtd, FL_LOCKING);
1197
1198         /* Shift to get chip number */
1199         chipnr = ofs >> chip->chip_shift;
1200
1201         chip->select_chip(mtd, chipnr);
1202
1203         /* Check, if it is write protected */
1204         if (nand_check_wp(mtd)) {
1205                 pr_debug("%s: device is write protected!\n",
1206                                         __func__);
1207                 status = MTD_ERASE_FAILED;
1208                 ret = -EIO;
1209                 goto out;
1210         }
1211
1212         /* Submit address of first page to lock */
1213         page = ofs >> chip->page_shift;
1214         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1215
1216         /* Call wait ready function */
1217         status = chip->waitfunc(mtd, chip);
1218         /* See if device thinks it succeeded */
1219         if (status & NAND_STATUS_FAIL) {
1220                 pr_debug("%s: error status = 0x%08x\n",
1221                                         __func__, status);
1222                 ret = -EIO;
1223                 goto out;
1224         }
1225
1226         ret = __nand_unlock(mtd, ofs, len, 0x1);
1227
1228 out:
1229         chip->select_chip(mtd, -1);
1230         nand_release_device(mtd);
1231
1232         return ret;
1233 }
1234 EXPORT_SYMBOL(nand_lock);
1235 #endif
1236
1237 /**
1238  * nand_read_page_raw - [INTERN] read raw page data without ecc
1239  * @mtd: mtd info structure
1240  * @chip: nand chip info structure
1241  * @buf: buffer to store read data
1242  * @oob_required: caller requires OOB data read to chip->oob_poi
1243  * @page: page number to read
1244  *
1245  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1246  */
1247 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1248                               uint8_t *buf, int oob_required, int page)
1249 {
1250         chip->read_buf(mtd, buf, mtd->writesize);
1251         if (oob_required)
1252                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1253         return 0;
1254 }
1255
1256 /**
1257  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1258  * @mtd: mtd info structure
1259  * @chip: nand chip info structure
1260  * @buf: buffer to store read data
1261  * @oob_required: caller requires OOB data read to chip->oob_poi
1262  * @page: page number to read
1263  *
1264  * We need a special oob layout and handling even when OOB isn't used.
1265  */
1266 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1267                                        struct nand_chip *chip, uint8_t *buf,
1268                                        int oob_required, int page)
1269 {
1270         int eccsize = chip->ecc.size;
1271         int eccbytes = chip->ecc.bytes;
1272         uint8_t *oob = chip->oob_poi;
1273         int steps, size;
1274
1275         for (steps = chip->ecc.steps; steps > 0; steps--) {
1276                 chip->read_buf(mtd, buf, eccsize);
1277                 buf += eccsize;
1278
1279                 if (chip->ecc.prepad) {
1280                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1281                         oob += chip->ecc.prepad;
1282                 }
1283
1284                 chip->read_buf(mtd, oob, eccbytes);
1285                 oob += eccbytes;
1286
1287                 if (chip->ecc.postpad) {
1288                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1289                         oob += chip->ecc.postpad;
1290                 }
1291         }
1292
1293         size = mtd->oobsize - (oob - chip->oob_poi);
1294         if (size)
1295                 chip->read_buf(mtd, oob, size);
1296
1297         return 0;
1298 }
1299
1300 /**
1301  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1302  * @mtd: mtd info structure
1303  * @chip: nand chip info structure
1304  * @buf: buffer to store read data
1305  * @oob_required: caller requires OOB data read to chip->oob_poi
1306  * @page: page number to read
1307  */
1308 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1309                                 uint8_t *buf, int oob_required, int page)
1310 {
1311         int i, eccsize = chip->ecc.size;
1312         int eccbytes = chip->ecc.bytes;
1313         int eccsteps = chip->ecc.steps;
1314         uint8_t *p = buf;
1315         uint8_t *ecc_calc = chip->buffers->ecccalc;
1316         uint8_t *ecc_code = chip->buffers->ecccode;
1317         uint32_t *eccpos = chip->ecc.layout->eccpos;
1318         unsigned int max_bitflips = 0;
1319
1320         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1321
1322         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1323                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1324
1325         for (i = 0; i < chip->ecc.total; i++)
1326                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1327
1328         eccsteps = chip->ecc.steps;
1329         p = buf;
1330
1331         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1332                 int stat;
1333
1334                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1335                 if (stat < 0) {
1336                         mtd->ecc_stats.failed++;
1337                 } else {
1338                         mtd->ecc_stats.corrected += stat;
1339                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1340                 }
1341         }
1342         return max_bitflips;
1343 }
1344
1345 /**
1346  * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1347  * @mtd: mtd info structure
1348  * @chip: nand chip info structure
1349  * @data_offs: offset of requested data within the page
1350  * @readlen: data length
1351  * @bufpoi: buffer to store read data
1352  * @page: page number to read
1353  */
1354 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1355                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1356                         int page)
1357 {
1358         int start_step, end_step, num_steps;
1359         uint32_t *eccpos = chip->ecc.layout->eccpos;
1360         uint8_t *p;
1361         int data_col_addr, i, gaps = 0;
1362         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1363         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1364         int index;
1365         unsigned int max_bitflips = 0;
1366
1367         /* Column address within the page aligned to ECC size (256bytes) */
1368         start_step = data_offs / chip->ecc.size;
1369         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1370         num_steps = end_step - start_step + 1;
1371         index = start_step * chip->ecc.bytes;
1372
1373         /* Data size aligned to ECC ecc.size */
1374         datafrag_len = num_steps * chip->ecc.size;
1375         eccfrag_len = num_steps * chip->ecc.bytes;
1376
1377         data_col_addr = start_step * chip->ecc.size;
1378         /* If we read not a page aligned data */
1379         if (data_col_addr != 0)
1380                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1381
1382         p = bufpoi + data_col_addr;
1383         chip->read_buf(mtd, p, datafrag_len);
1384
1385         /* Calculate ECC */
1386         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1387                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1388
1389         /*
1390          * The performance is faster if we position offsets according to
1391          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1392          */
1393         for (i = 0; i < eccfrag_len - 1; i++) {
1394                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1395                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1396                         gaps = 1;
1397                         break;
1398                 }
1399         }
1400         if (gaps) {
1401                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1402                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1403         } else {
1404                 /*
1405                  * Send the command to read the particular ECC bytes take care
1406                  * about buswidth alignment in read_buf.
1407                  */
1408                 aligned_pos = eccpos[index] & ~(busw - 1);
1409                 aligned_len = eccfrag_len;
1410                 if (eccpos[index] & (busw - 1))
1411                         aligned_len++;
1412                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1413                         aligned_len++;
1414
1415                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1416                                         mtd->writesize + aligned_pos, -1);
1417                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1418         }
1419
1420         for (i = 0; i < eccfrag_len; i++)
1421                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1422
1423         p = bufpoi + data_col_addr;
1424         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1425                 int stat;
1426
1427                 stat = chip->ecc.correct(mtd, p,
1428                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1429                 if (stat < 0) {
1430                         mtd->ecc_stats.failed++;
1431                 } else {
1432                         mtd->ecc_stats.corrected += stat;
1433                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1434                 }
1435         }
1436         return max_bitflips;
1437 }
1438
1439 /**
1440  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1441  * @mtd: mtd info structure
1442  * @chip: nand chip info structure
1443  * @buf: buffer to store read data
1444  * @oob_required: caller requires OOB data read to chip->oob_poi
1445  * @page: page number to read
1446  *
1447  * Not for syndrome calculating ECC controllers which need a special oob layout.
1448  */
1449 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1450                                 uint8_t *buf, int oob_required, int page)
1451 {
1452         int i, eccsize = chip->ecc.size;
1453         int eccbytes = chip->ecc.bytes;
1454         int eccsteps = chip->ecc.steps;
1455         uint8_t *p = buf;
1456         uint8_t *ecc_calc = chip->buffers->ecccalc;
1457         uint8_t *ecc_code = chip->buffers->ecccode;
1458         uint32_t *eccpos = chip->ecc.layout->eccpos;
1459         unsigned int max_bitflips = 0;
1460
1461         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1462                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1463                 chip->read_buf(mtd, p, eccsize);
1464                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1465         }
1466         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1467
1468         for (i = 0; i < chip->ecc.total; i++)
1469                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1470
1471         eccsteps = chip->ecc.steps;
1472         p = buf;
1473
1474         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1475                 int stat;
1476
1477                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1478                 if (stat < 0) {
1479                         mtd->ecc_stats.failed++;
1480                 } else {
1481                         mtd->ecc_stats.corrected += stat;
1482                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1483                 }
1484         }
1485         return max_bitflips;
1486 }
1487
1488 /**
1489  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1490  * @mtd: mtd info structure
1491  * @chip: nand chip info structure
1492  * @buf: buffer to store read data
1493  * @oob_required: caller requires OOB data read to chip->oob_poi
1494  * @page: page number to read
1495  *
1496  * Hardware ECC for large page chips, require OOB to be read first. For this
1497  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1498  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1499  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1500  * the data area, by overwriting the NAND manufacturer bad block markings.
1501  */
1502 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1503         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1504 {
1505         int i, eccsize = chip->ecc.size;
1506         int eccbytes = chip->ecc.bytes;
1507         int eccsteps = chip->ecc.steps;
1508         uint8_t *p = buf;
1509         uint8_t *ecc_code = chip->buffers->ecccode;
1510         uint32_t *eccpos = chip->ecc.layout->eccpos;
1511         uint8_t *ecc_calc = chip->buffers->ecccalc;
1512         unsigned int max_bitflips = 0;
1513
1514         /* Read the OOB area first */
1515         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1516         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1517         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1518
1519         for (i = 0; i < chip->ecc.total; i++)
1520                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1521
1522         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1523                 int stat;
1524
1525                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1526                 chip->read_buf(mtd, p, eccsize);
1527                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1528
1529                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1530                 if (stat < 0) {
1531                         mtd->ecc_stats.failed++;
1532                 } else {
1533                         mtd->ecc_stats.corrected += stat;
1534                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1535                 }
1536         }
1537         return max_bitflips;
1538 }
1539
1540 /**
1541  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1542  * @mtd: mtd info structure
1543  * @chip: nand chip info structure
1544  * @buf: buffer to store read data
1545  * @oob_required: caller requires OOB data read to chip->oob_poi
1546  * @page: page number to read
1547  *
1548  * The hw generator calculates the error syndrome automatically. Therefore we
1549  * need a special oob layout and handling.
1550  */
1551 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1552                                    uint8_t *buf, int oob_required, int page)
1553 {
1554         int i, eccsize = chip->ecc.size;
1555         int eccbytes = chip->ecc.bytes;
1556         int eccsteps = chip->ecc.steps;
1557         uint8_t *p = buf;
1558         uint8_t *oob = chip->oob_poi;
1559         unsigned int max_bitflips = 0;
1560
1561         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1562                 int stat;
1563
1564                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1565                 chip->read_buf(mtd, p, eccsize);
1566
1567                 if (chip->ecc.prepad) {
1568                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1569                         oob += chip->ecc.prepad;
1570                 }
1571
1572                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1573                 chip->read_buf(mtd, oob, eccbytes);
1574                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1575
1576                 if (stat < 0) {
1577                         mtd->ecc_stats.failed++;
1578                 } else {
1579                         mtd->ecc_stats.corrected += stat;
1580                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1581                 }
1582
1583                 oob += eccbytes;
1584
1585                 if (chip->ecc.postpad) {
1586                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1587                         oob += chip->ecc.postpad;
1588                 }
1589         }
1590
1591         /* Calculate remaining oob bytes */
1592         i = mtd->oobsize - (oob - chip->oob_poi);
1593         if (i)
1594                 chip->read_buf(mtd, oob, i);
1595
1596         return max_bitflips;
1597 }
1598
1599 /**
1600  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1601  * @chip: nand chip structure
1602  * @oob: oob destination address
1603  * @ops: oob ops structure
1604  * @len: size of oob to transfer
1605  */
1606 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1607                                   struct mtd_oob_ops *ops, size_t len)
1608 {
1609         switch (ops->mode) {
1610
1611         case MTD_OPS_PLACE_OOB:
1612         case MTD_OPS_RAW:
1613                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1614                 return oob + len;
1615
1616         case MTD_OPS_AUTO_OOB: {
1617                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1618                 uint32_t boffs = 0, roffs = ops->ooboffs;
1619                 size_t bytes = 0;
1620
1621                 for (; free->length && len; free++, len -= bytes) {
1622                         /* Read request not from offset 0? */
1623                         if (unlikely(roffs)) {
1624                                 if (roffs >= free->length) {
1625                                         roffs -= free->length;
1626                                         continue;
1627                                 }
1628                                 boffs = free->offset + roffs;
1629                                 bytes = min_t(size_t, len,
1630                                               (free->length - roffs));
1631                                 roffs = 0;
1632                         } else {
1633                                 bytes = min_t(size_t, len, free->length);
1634                                 boffs = free->offset;
1635                         }
1636                         memcpy(oob, chip->oob_poi + boffs, bytes);
1637                         oob += bytes;
1638                 }
1639                 return oob;
1640         }
1641         default:
1642                 BUG();
1643         }
1644         return NULL;
1645 }
1646
1647 /**
1648  * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1649  * @mtd: MTD device structure
1650  * @retry_mode: the retry mode to use
1651  *
1652  * Some vendors supply a special command to shift the Vt threshold, to be used
1653  * when there are too many bitflips in a page (i.e., ECC error). After setting
1654  * a new threshold, the host should retry reading the page.
1655  */
1656 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1657 {
1658         struct nand_chip *chip = mtd->priv;
1659
1660         pr_debug("setting READ RETRY mode %d\n", retry_mode);
1661
1662         if (retry_mode >= chip->read_retries)
1663                 return -EINVAL;
1664
1665         if (!chip->setup_read_retry)
1666                 return -EOPNOTSUPP;
1667
1668         return chip->setup_read_retry(mtd, retry_mode);
1669 }
1670
1671 /**
1672  * nand_do_read_ops - [INTERN] Read data with ECC
1673  * @mtd: MTD device structure
1674  * @from: offset to read from
1675  * @ops: oob ops structure
1676  *
1677  * Internal function. Called with chip held.
1678  */
1679 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1680                             struct mtd_oob_ops *ops)
1681 {
1682         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1683         struct nand_chip *chip = mtd->priv;
1684         int ret = 0;
1685         uint32_t readlen = ops->len;
1686         uint32_t oobreadlen = ops->ooblen;
1687         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1688                 mtd->oobavail : mtd->oobsize;
1689
1690         uint8_t *bufpoi, *oob, *buf;
1691         unsigned int max_bitflips = 0;
1692         int retry_mode = 0;
1693         bool ecc_fail = false;
1694
1695         chipnr = (int)(from >> chip->chip_shift);
1696         chip->select_chip(mtd, chipnr);
1697
1698         realpage = (int)(from >> chip->page_shift);
1699         page = realpage & chip->pagemask;
1700
1701         col = (int)(from & (mtd->writesize - 1));
1702
1703         buf = ops->datbuf;
1704         oob = ops->oobbuf;
1705         oob_required = oob ? 1 : 0;
1706
1707         while (1) {
1708                 unsigned int ecc_failures = mtd->ecc_stats.failed;
1709
1710                 WATCHDOG_RESET();
1711                 bytes = min(mtd->writesize - col, readlen);
1712                 aligned = (bytes == mtd->writesize);
1713
1714                 /* Is the current page in the buffer? */
1715                 if (realpage != chip->pagebuf || oob) {
1716                         bufpoi = aligned ? buf : chip->buffers->databuf;
1717
1718 read_retry:
1719                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1720
1721                         /*
1722                          * Now read the page into the buffer.  Absent an error,
1723                          * the read methods return max bitflips per ecc step.
1724                          */
1725                         if (unlikely(ops->mode == MTD_OPS_RAW))
1726                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1727                                                               oob_required,
1728                                                               page);
1729                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1730                                  !oob)
1731                                 ret = chip->ecc.read_subpage(mtd, chip,
1732                                                         col, bytes, bufpoi,
1733                                                         page);
1734                         else
1735                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1736                                                           oob_required, page);
1737                         if (ret < 0) {
1738                                 if (!aligned)
1739                                         /* Invalidate page cache */
1740                                         chip->pagebuf = -1;
1741                                 break;
1742                         }
1743
1744                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1745
1746                         /* Transfer not aligned data */
1747                         if (!aligned) {
1748                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1749                                     !(mtd->ecc_stats.failed - ecc_failures) &&
1750                                     (ops->mode != MTD_OPS_RAW)) {
1751                                         chip->pagebuf = realpage;
1752                                         chip->pagebuf_bitflips = ret;
1753                                 } else {
1754                                         /* Invalidate page cache */
1755                                         chip->pagebuf = -1;
1756                                 }
1757                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1758                         }
1759
1760                         if (unlikely(oob)) {
1761                                 int toread = min(oobreadlen, max_oobsize);
1762
1763                                 if (toread) {
1764                                         oob = nand_transfer_oob(chip,
1765                                                 oob, ops, toread);
1766                                         oobreadlen -= toread;
1767                                 }
1768                         }
1769
1770                         if (chip->options & NAND_NEED_READRDY) {
1771                                 /* Apply delay or wait for ready/busy pin */
1772                                 if (!chip->dev_ready)
1773                                         udelay(chip->chip_delay);
1774                                 else
1775                                         nand_wait_ready(mtd);
1776                         }
1777
1778                         if (mtd->ecc_stats.failed - ecc_failures) {
1779                                 if (retry_mode + 1 < chip->read_retries) {
1780                                         retry_mode++;
1781                                         ret = nand_setup_read_retry(mtd,
1782                                                         retry_mode);
1783                                         if (ret < 0)
1784                                                 break;
1785
1786                                         /* Reset failures; retry */
1787                                         mtd->ecc_stats.failed = ecc_failures;
1788                                         goto read_retry;
1789                                 } else {
1790                                         /* No more retry modes; real failure */
1791                                         ecc_fail = true;
1792                                 }
1793                         }
1794
1795                         buf += bytes;
1796                 } else {
1797                         memcpy(buf, chip->buffers->databuf + col, bytes);
1798                         buf += bytes;
1799                         max_bitflips = max_t(unsigned int, max_bitflips,
1800                                              chip->pagebuf_bitflips);
1801                 }
1802
1803                 readlen -= bytes;
1804
1805                 /* Reset to retry mode 0 */
1806                 if (retry_mode) {
1807                         ret = nand_setup_read_retry(mtd, 0);
1808                         if (ret < 0)
1809                                 break;
1810                         retry_mode = 0;
1811                 }
1812
1813                 if (!readlen)
1814                         break;
1815
1816                 /* For subsequent reads align to page boundary */
1817                 col = 0;
1818                 /* Increment page address */
1819                 realpage++;
1820
1821                 page = realpage & chip->pagemask;
1822                 /* Check, if we cross a chip boundary */
1823                 if (!page) {
1824                         chipnr++;
1825                         chip->select_chip(mtd, -1);
1826                         chip->select_chip(mtd, chipnr);
1827                 }
1828         }
1829         chip->select_chip(mtd, -1);
1830
1831         ops->retlen = ops->len - (size_t) readlen;
1832         if (oob)
1833                 ops->oobretlen = ops->ooblen - oobreadlen;
1834
1835         if (ret < 0)
1836                 return ret;
1837
1838         if (ecc_fail)
1839                 return -EBADMSG;
1840
1841         return max_bitflips;
1842 }
1843
1844 /**
1845  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1846  * @mtd: MTD device structure
1847  * @from: offset to read from
1848  * @len: number of bytes to read
1849  * @retlen: pointer to variable to store the number of read bytes
1850  * @buf: the databuffer to put data
1851  *
1852  * Get hold of the chip and call nand_do_read.
1853  */
1854 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1855                      size_t *retlen, uint8_t *buf)
1856 {
1857         struct mtd_oob_ops ops;
1858         int ret;
1859
1860         nand_get_device(mtd, FL_READING);
1861         ops.len = len;
1862         ops.datbuf = buf;
1863         ops.oobbuf = NULL;
1864         ops.mode = MTD_OPS_PLACE_OOB;
1865         ret = nand_do_read_ops(mtd, from, &ops);
1866         *retlen = ops.retlen;
1867         nand_release_device(mtd);
1868         return ret;
1869 }
1870
1871 /**
1872  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1873  * @mtd: mtd info structure
1874  * @chip: nand chip info structure
1875  * @page: page number to read
1876  */
1877 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1878                              int page)
1879 {
1880         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1881         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1882         return 0;
1883 }
1884
1885 /**
1886  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1887  *                          with syndromes
1888  * @mtd: mtd info structure
1889  * @chip: nand chip info structure
1890  * @page: page number to read
1891  */
1892 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1893                                   int page)
1894 {
1895         uint8_t *buf = chip->oob_poi;
1896         int length = mtd->oobsize;
1897         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1898         int eccsize = chip->ecc.size;
1899         uint8_t *bufpoi = buf;
1900         int i, toread, sndrnd = 0, pos;
1901
1902         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1903         for (i = 0; i < chip->ecc.steps; i++) {
1904                 if (sndrnd) {
1905                         pos = eccsize + i * (eccsize + chunk);
1906                         if (mtd->writesize > 512)
1907                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1908                         else
1909                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1910                 } else
1911                         sndrnd = 1;
1912                 toread = min_t(int, length, chunk);
1913                 chip->read_buf(mtd, bufpoi, toread);
1914                 bufpoi += toread;
1915                 length -= toread;
1916         }
1917         if (length > 0)
1918                 chip->read_buf(mtd, bufpoi, length);
1919
1920         return 0;
1921 }
1922
1923 /**
1924  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1925  * @mtd: mtd info structure
1926  * @chip: nand chip info structure
1927  * @page: page number to write
1928  */
1929 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1930                               int page)
1931 {
1932         int status = 0;
1933         const uint8_t *buf = chip->oob_poi;
1934         int length = mtd->oobsize;
1935
1936         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1937         chip->write_buf(mtd, buf, length);
1938         /* Send command to program the OOB data */
1939         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1940
1941         status = chip->waitfunc(mtd, chip);
1942
1943         return status & NAND_STATUS_FAIL ? -EIO : 0;
1944 }
1945
1946 /**
1947  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1948  *                           with syndrome - only for large page flash
1949  * @mtd: mtd info structure
1950  * @chip: nand chip info structure
1951  * @page: page number to write
1952  */
1953 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1954                                    struct nand_chip *chip, int page)
1955 {
1956         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1957         int eccsize = chip->ecc.size, length = mtd->oobsize;
1958         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1959         const uint8_t *bufpoi = chip->oob_poi;
1960
1961         /*
1962          * data-ecc-data-ecc ... ecc-oob
1963          * or
1964          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1965          */
1966         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1967                 pos = steps * (eccsize + chunk);
1968                 steps = 0;
1969         } else
1970                 pos = eccsize;
1971
1972         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1973         for (i = 0; i < steps; i++) {
1974                 if (sndcmd) {
1975                         if (mtd->writesize <= 512) {
1976                                 uint32_t fill = 0xFFFFFFFF;
1977
1978                                 len = eccsize;
1979                                 while (len > 0) {
1980                                         int num = min_t(int, len, 4);
1981                                         chip->write_buf(mtd, (uint8_t *)&fill,
1982                                                         num);
1983                                         len -= num;
1984                                 }
1985                         } else {
1986                                 pos = eccsize + i * (eccsize + chunk);
1987                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1988                         }
1989                 } else
1990                         sndcmd = 1;
1991                 len = min_t(int, length, chunk);
1992                 chip->write_buf(mtd, bufpoi, len);
1993                 bufpoi += len;
1994                 length -= len;
1995         }
1996         if (length > 0)
1997                 chip->write_buf(mtd, bufpoi, length);
1998
1999         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2000         status = chip->waitfunc(mtd, chip);
2001
2002         return status & NAND_STATUS_FAIL ? -EIO : 0;
2003 }
2004
2005 /**
2006  * nand_do_read_oob - [INTERN] NAND read out-of-band
2007  * @mtd: MTD device structure
2008  * @from: offset to read from
2009  * @ops: oob operations description structure
2010  *
2011  * NAND read out-of-band data from the spare area.
2012  */
2013 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2014                             struct mtd_oob_ops *ops)
2015 {
2016         int page, realpage, chipnr;
2017         struct nand_chip *chip = mtd->priv;
2018         struct mtd_ecc_stats stats;
2019         int readlen = ops->ooblen;
2020         int len;
2021         uint8_t *buf = ops->oobbuf;
2022         int ret = 0;
2023
2024         pr_debug("%s: from = 0x%08Lx, len = %i\n",
2025                         __func__, (unsigned long long)from, readlen);
2026
2027         stats = mtd->ecc_stats;
2028
2029         if (ops->mode == MTD_OPS_AUTO_OOB)
2030                 len = chip->ecc.layout->oobavail;
2031         else
2032                 len = mtd->oobsize;
2033
2034         if (unlikely(ops->ooboffs >= len)) {
2035                 pr_debug("%s: attempt to start read outside oob\n",
2036                                 __func__);
2037                 return -EINVAL;
2038         }
2039
2040         /* Do not allow reads past end of device */
2041         if (unlikely(from >= mtd->size ||
2042                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2043                                         (from >> chip->page_shift)) * len)) {
2044                 pr_debug("%s: attempt to read beyond end of device\n",
2045                                 __func__);
2046                 return -EINVAL;
2047         }
2048
2049         chipnr = (int)(from >> chip->chip_shift);
2050         chip->select_chip(mtd, chipnr);
2051
2052         /* Shift to get page */
2053         realpage = (int)(from >> chip->page_shift);
2054         page = realpage & chip->pagemask;
2055
2056         while (1) {
2057                 WATCHDOG_RESET();
2058
2059                 if (ops->mode == MTD_OPS_RAW)
2060                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
2061                 else
2062                         ret = chip->ecc.read_oob(mtd, chip, page);
2063
2064                 if (ret < 0)
2065                         break;
2066
2067                 len = min(len, readlen);
2068                 buf = nand_transfer_oob(chip, buf, ops, len);
2069
2070                 if (chip->options & NAND_NEED_READRDY) {
2071                         /* Apply delay or wait for ready/busy pin */
2072                         if (!chip->dev_ready)
2073                                 udelay(chip->chip_delay);
2074                         else
2075                                 nand_wait_ready(mtd);
2076                 }
2077
2078                 readlen -= len;
2079                 if (!readlen)
2080                         break;
2081
2082                 /* Increment page address */
2083                 realpage++;
2084
2085                 page = realpage & chip->pagemask;
2086                 /* Check, if we cross a chip boundary */
2087                 if (!page) {
2088                         chipnr++;
2089                         chip->select_chip(mtd, -1);
2090                         chip->select_chip(mtd, chipnr);
2091                 }
2092         }
2093         chip->select_chip(mtd, -1);
2094
2095         ops->oobretlen = ops->ooblen - readlen;
2096
2097         if (ret < 0)
2098                 return ret;
2099
2100         if (mtd->ecc_stats.failed - stats.failed)
2101                 return -EBADMSG;
2102
2103         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2104 }
2105
2106 /**
2107  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2108  * @mtd: MTD device structure
2109  * @from: offset to read from
2110  * @ops: oob operation description structure
2111  *
2112  * NAND read data and/or out-of-band data.
2113  */
2114 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2115                          struct mtd_oob_ops *ops)
2116 {
2117         int ret = -ENOTSUPP;
2118
2119         ops->retlen = 0;
2120
2121         /* Do not allow reads past end of device */
2122         if (ops->datbuf && (from + ops->len) > mtd->size) {
2123                 pr_debug("%s: attempt to read beyond end of device\n",
2124                                 __func__);
2125                 return -EINVAL;
2126         }
2127
2128         nand_get_device(mtd, FL_READING);
2129
2130         switch (ops->mode) {
2131         case MTD_OPS_PLACE_OOB:
2132         case MTD_OPS_AUTO_OOB:
2133         case MTD_OPS_RAW:
2134                 break;
2135
2136         default:
2137                 goto out;
2138         }
2139
2140         if (!ops->datbuf)
2141                 ret = nand_do_read_oob(mtd, from, ops);
2142         else
2143                 ret = nand_do_read_ops(mtd, from, ops);
2144
2145 out:
2146         nand_release_device(mtd);
2147         return ret;
2148 }
2149
2150
2151 /**
2152  * nand_write_page_raw - [INTERN] raw page write function
2153  * @mtd: mtd info structure
2154  * @chip: nand chip info structure
2155  * @buf: data buffer
2156  * @oob_required: must write chip->oob_poi to OOB
2157  *
2158  * Not for syndrome calculating ECC controllers, which use a special oob layout.
2159  */
2160 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2161                                 const uint8_t *buf, int oob_required)
2162 {
2163         chip->write_buf(mtd, buf, mtd->writesize);
2164         if (oob_required)
2165                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2166
2167         return 0;
2168 }
2169
2170 /**
2171  * nand_write_page_raw_syndrome - [INTERN] raw page write function
2172  * @mtd: mtd info structure
2173  * @chip: nand chip info structure
2174  * @buf: data buffer
2175  * @oob_required: must write chip->oob_poi to OOB
2176  *
2177  * We need a special oob layout and handling even when ECC isn't checked.
2178  */
2179 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2180                                         struct nand_chip *chip,
2181                                         const uint8_t *buf, int oob_required)
2182 {
2183         int eccsize = chip->ecc.size;
2184         int eccbytes = chip->ecc.bytes;
2185         uint8_t *oob = chip->oob_poi;
2186         int steps, size;
2187
2188         for (steps = chip->ecc.steps; steps > 0; steps--) {
2189                 chip->write_buf(mtd, buf, eccsize);
2190                 buf += eccsize;
2191
2192                 if (chip->ecc.prepad) {
2193                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2194                         oob += chip->ecc.prepad;
2195                 }
2196
2197                 chip->write_buf(mtd, oob, eccbytes);
2198                 oob += eccbytes;
2199
2200                 if (chip->ecc.postpad) {
2201                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2202                         oob += chip->ecc.postpad;
2203                 }
2204         }
2205
2206         size = mtd->oobsize - (oob - chip->oob_poi);
2207         if (size)
2208                 chip->write_buf(mtd, oob, size);
2209
2210         return 0;
2211 }
2212 /**
2213  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2214  * @mtd: mtd info structure
2215  * @chip: nand chip info structure
2216  * @buf: data buffer
2217  * @oob_required: must write chip->oob_poi to OOB
2218  */
2219 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2220                                   const uint8_t *buf, int oob_required)
2221 {
2222         int i, eccsize = chip->ecc.size;
2223         int eccbytes = chip->ecc.bytes;
2224         int eccsteps = chip->ecc.steps;
2225         uint8_t *ecc_calc = chip->buffers->ecccalc;
2226         const uint8_t *p = buf;
2227         uint32_t *eccpos = chip->ecc.layout->eccpos;
2228
2229         /* Software ECC calculation */
2230         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2231                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2232
2233         for (i = 0; i < chip->ecc.total; i++)
2234                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2235
2236         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2237 }
2238
2239 /**
2240  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2241  * @mtd: mtd info structure
2242  * @chip: nand chip info structure
2243  * @buf: data buffer
2244  * @oob_required: must write chip->oob_poi to OOB
2245  */
2246 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2247                                   const uint8_t *buf, int oob_required)
2248 {
2249         int i, eccsize = chip->ecc.size;
2250         int eccbytes = chip->ecc.bytes;
2251         int eccsteps = chip->ecc.steps;
2252         uint8_t *ecc_calc = chip->buffers->ecccalc;
2253         const uint8_t *p = buf;
2254         uint32_t *eccpos = chip->ecc.layout->eccpos;
2255
2256         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2257                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2258                 chip->write_buf(mtd, p, eccsize);
2259                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2260         }
2261
2262         for (i = 0; i < chip->ecc.total; i++)
2263                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2264
2265         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2266
2267         return 0;
2268 }
2269
2270
2271 /**
2272  * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2273  * @mtd:        mtd info structure
2274  * @chip:       nand chip info structure
2275  * @offset:     column address of subpage within the page
2276  * @data_len:   data length
2277  * @buf:        data buffer
2278  * @oob_required: must write chip->oob_poi to OOB
2279  */
2280 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2281                                 struct nand_chip *chip, uint32_t offset,
2282                                 uint32_t data_len, const uint8_t *buf,
2283                                 int oob_required)
2284 {
2285         uint8_t *oob_buf  = chip->oob_poi;
2286         uint8_t *ecc_calc = chip->buffers->ecccalc;
2287         int ecc_size      = chip->ecc.size;
2288         int ecc_bytes     = chip->ecc.bytes;
2289         int ecc_steps     = chip->ecc.steps;
2290         uint32_t *eccpos  = chip->ecc.layout->eccpos;
2291         uint32_t start_step = offset / ecc_size;
2292         uint32_t end_step   = (offset + data_len - 1) / ecc_size;
2293         int oob_bytes       = mtd->oobsize / ecc_steps;
2294         int step, i;
2295
2296         for (step = 0; step < ecc_steps; step++) {
2297                 /* configure controller for WRITE access */
2298                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2299
2300                 /* write data (untouched subpages already masked by 0xFF) */
2301                 chip->write_buf(mtd, buf, ecc_size);
2302
2303                 /* mask ECC of un-touched subpages by padding 0xFF */
2304                 if ((step < start_step) || (step > end_step))
2305                         memset(ecc_calc, 0xff, ecc_bytes);
2306                 else
2307                         chip->ecc.calculate(mtd, buf, ecc_calc);
2308
2309                 /* mask OOB of un-touched subpages by padding 0xFF */
2310                 /* if oob_required, preserve OOB metadata of written subpage */
2311                 if (!oob_required || (step < start_step) || (step > end_step))
2312                         memset(oob_buf, 0xff, oob_bytes);
2313
2314                 buf += ecc_size;
2315                 ecc_calc += ecc_bytes;
2316                 oob_buf  += oob_bytes;
2317         }
2318
2319         /* copy calculated ECC for whole page to chip->buffer->oob */
2320         /* this include masked-value(0xFF) for unwritten subpages */
2321         ecc_calc = chip->buffers->ecccalc;
2322         for (i = 0; i < chip->ecc.total; i++)
2323                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2324
2325         /* write OOB buffer to NAND device */
2326         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2327
2328         return 0;
2329 }
2330
2331
2332 /**
2333  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2334  * @mtd: mtd info structure
2335  * @chip: nand chip info structure
2336  * @buf: data buffer
2337  * @oob_required: must write chip->oob_poi to OOB
2338  *
2339  * The hw generator calculates the error syndrome automatically. Therefore we
2340  * need a special oob layout and handling.
2341  */
2342 static int nand_write_page_syndrome(struct mtd_info *mtd,
2343                                     struct nand_chip *chip,
2344                                     const uint8_t *buf, int oob_required)
2345 {
2346         int i, eccsize = chip->ecc.size;
2347         int eccbytes = chip->ecc.bytes;
2348         int eccsteps = chip->ecc.steps;
2349         const uint8_t *p = buf;
2350         uint8_t *oob = chip->oob_poi;
2351
2352         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2353
2354                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2355                 chip->write_buf(mtd, p, eccsize);
2356
2357                 if (chip->ecc.prepad) {
2358                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2359                         oob += chip->ecc.prepad;
2360                 }
2361
2362                 chip->ecc.calculate(mtd, p, oob);
2363                 chip->write_buf(mtd, oob, eccbytes);
2364                 oob += eccbytes;
2365
2366                 if (chip->ecc.postpad) {
2367                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2368                         oob += chip->ecc.postpad;
2369                 }
2370         }
2371
2372         /* Calculate remaining oob bytes */
2373         i = mtd->oobsize - (oob - chip->oob_poi);
2374         if (i)
2375                 chip->write_buf(mtd, oob, i);
2376
2377         return 0;
2378 }
2379
2380 /**
2381  * nand_write_page - [REPLACEABLE] write one page
2382  * @mtd: MTD device structure
2383  * @chip: NAND chip descriptor
2384  * @offset: address offset within the page
2385  * @data_len: length of actual data to be written
2386  * @buf: the data to write
2387  * @oob_required: must write chip->oob_poi to OOB
2388  * @page: page number to write
2389  * @cached: cached programming
2390  * @raw: use _raw version of write_page
2391  */
2392 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2393                 uint32_t offset, int data_len, const uint8_t *buf,
2394                 int oob_required, int page, int cached, int raw)
2395 {
2396         int status, subpage;
2397
2398         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2399                 chip->ecc.write_subpage)
2400                 subpage = offset || (data_len < mtd->writesize);
2401         else
2402                 subpage = 0;
2403
2404         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2405
2406         if (unlikely(raw))
2407                 status = chip->ecc.write_page_raw(mtd, chip, buf,
2408                                                         oob_required);
2409         else if (subpage)
2410                 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2411                                                          buf, oob_required);
2412         else
2413                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2414
2415         if (status < 0)
2416                 return status;
2417
2418         /*
2419          * Cached progamming disabled for now. Not sure if it's worth the
2420          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2421          */
2422         cached = 0;
2423
2424         if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2425
2426                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2427                 status = chip->waitfunc(mtd, chip);
2428                 /*
2429                  * See if operation failed and additional status checks are
2430                  * available.
2431                  */
2432                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2433                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2434                                                page);
2435
2436                 if (status & NAND_STATUS_FAIL)
2437                         return -EIO;
2438         } else {
2439                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2440                 status = chip->waitfunc(mtd, chip);
2441         }
2442
2443
2444 #ifdef __UBOOT__
2445 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
2446         /* Send command to read back the data */
2447         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2448
2449         if (chip->verify_buf(mtd, buf, mtd->writesize))
2450                 return -EIO;
2451
2452         /* Make sure the next page prog is preceded by a status read */
2453         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2454 #endif
2455 #endif
2456
2457         return 0;
2458 }
2459
2460 /**
2461  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2462  * @mtd: MTD device structure
2463  * @oob: oob data buffer
2464  * @len: oob data write length
2465  * @ops: oob ops structure
2466  */
2467 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2468                               struct mtd_oob_ops *ops)
2469 {
2470         struct nand_chip *chip = mtd->priv;
2471
2472         /*
2473          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2474          * data from a previous OOB read.
2475          */
2476         memset(chip->oob_poi, 0xff, mtd->oobsize);
2477
2478         switch (ops->mode) {
2479
2480         case MTD_OPS_PLACE_OOB:
2481         case MTD_OPS_RAW:
2482                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2483                 return oob + len;
2484
2485         case MTD_OPS_AUTO_OOB: {
2486                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2487                 uint32_t boffs = 0, woffs = ops->ooboffs;
2488                 size_t bytes = 0;
2489
2490                 for (; free->length && len; free++, len -= bytes) {
2491                         /* Write request not from offset 0? */
2492                         if (unlikely(woffs)) {
2493                                 if (woffs >= free->length) {
2494                                         woffs -= free->length;
2495                                         continue;
2496                                 }
2497                                 boffs = free->offset + woffs;
2498                                 bytes = min_t(size_t, len,
2499                                               (free->length - woffs));
2500                                 woffs = 0;
2501                         } else {
2502                                 bytes = min_t(size_t, len, free->length);
2503                                 boffs = free->offset;
2504                         }
2505                         memcpy(chip->oob_poi + boffs, oob, bytes);
2506                         oob += bytes;
2507                 }
2508                 return oob;
2509         }
2510         default:
2511                 BUG();
2512         }
2513         return NULL;
2514 }
2515
2516 #define NOTALIGNED(x)   (((x) & (chip->subpagesize - 1)) != 0)
2517
2518 /**
2519  * nand_do_write_ops - [INTERN] NAND write with ECC
2520  * @mtd: MTD device structure
2521  * @to: offset to write to
2522  * @ops: oob operations description structure
2523  *
2524  * NAND write with ECC.
2525  */
2526 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2527                              struct mtd_oob_ops *ops)
2528 {
2529         int chipnr, realpage, page, blockmask, column;
2530         struct nand_chip *chip = mtd->priv;
2531         uint32_t writelen = ops->len;
2532
2533         uint32_t oobwritelen = ops->ooblen;
2534         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2535                                 mtd->oobavail : mtd->oobsize;
2536
2537         uint8_t *oob = ops->oobbuf;
2538         uint8_t *buf = ops->datbuf;
2539         int ret;
2540         int oob_required = oob ? 1 : 0;
2541
2542         ops->retlen = 0;
2543         if (!writelen)
2544                 return 0;
2545
2546 #ifndef __UBOOT__
2547         /* Reject writes, which are not page aligned */
2548         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2549 #else
2550         /* Reject writes, which are not page aligned */
2551         if (NOTALIGNED(to)) {
2552 #endif
2553                 pr_notice("%s: attempt to write non page aligned data\n",
2554                            __func__);
2555                 return -EINVAL;
2556         }
2557
2558         column = to & (mtd->writesize - 1);
2559
2560         chipnr = (int)(to >> chip->chip_shift);
2561         chip->select_chip(mtd, chipnr);
2562
2563         /* Check, if it is write protected */
2564         if (nand_check_wp(mtd)) {
2565                 ret = -EIO;
2566                 goto err_out;
2567         }
2568
2569         realpage = (int)(to >> chip->page_shift);
2570         page = realpage & chip->pagemask;
2571         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2572
2573         /* Invalidate the page cache, when we write to the cached page */
2574         if (to <= (chip->pagebuf << chip->page_shift) &&
2575             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2576                 chip->pagebuf = -1;
2577
2578         /* Don't allow multipage oob writes with offset */
2579         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2580                 ret = -EINVAL;
2581                 goto err_out;
2582         }
2583
2584         while (1) {
2585                 int bytes = mtd->writesize;
2586                 int cached = writelen > bytes && page != blockmask;
2587                 uint8_t *wbuf = buf;
2588
2589                 WATCHDOG_RESET();
2590                 /* Partial page write? */
2591                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2592                         cached = 0;
2593                         bytes = min_t(int, bytes - column, (int) writelen);
2594                         chip->pagebuf = -1;
2595                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2596                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2597                         wbuf = chip->buffers->databuf;
2598                 }
2599
2600                 if (unlikely(oob)) {
2601                         size_t len = min(oobwritelen, oobmaxlen);
2602                         oob = nand_fill_oob(mtd, oob, len, ops);
2603                         oobwritelen -= len;
2604                 } else {
2605                         /* We still need to erase leftover OOB data */
2606                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2607                 }
2608                 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2609                                         oob_required, page, cached,
2610                                         (ops->mode == MTD_OPS_RAW));
2611                 if (ret)
2612                         break;
2613
2614                 writelen -= bytes;
2615                 if (!writelen)
2616                         break;
2617
2618                 column = 0;
2619                 buf += bytes;
2620                 realpage++;
2621
2622                 page = realpage & chip->pagemask;
2623                 /* Check, if we cross a chip boundary */
2624                 if (!page) {
2625                         chipnr++;
2626                         chip->select_chip(mtd, -1);
2627                         chip->select_chip(mtd, chipnr);
2628                 }
2629         }
2630
2631         ops->retlen = ops->len - writelen;
2632         if (unlikely(oob))
2633                 ops->oobretlen = ops->ooblen;
2634
2635 err_out:
2636         chip->select_chip(mtd, -1);
2637         return ret;
2638 }
2639
2640 /**
2641  * panic_nand_write - [MTD Interface] NAND write with ECC
2642  * @mtd: MTD device structure
2643  * @to: offset to write to
2644  * @len: number of bytes to write
2645  * @retlen: pointer to variable to store the number of written bytes
2646  * @buf: the data to write
2647  *
2648  * NAND write with ECC. Used when performing writes in interrupt context, this
2649  * may for example be called by mtdoops when writing an oops while in panic.
2650  */
2651 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2652                             size_t *retlen, const uint8_t *buf)
2653 {
2654         struct nand_chip *chip = mtd->priv;
2655         struct mtd_oob_ops ops;
2656         int ret;
2657
2658         /* Wait for the device to get ready */
2659         panic_nand_wait(mtd, chip, 400);
2660
2661         /* Grab the device */
2662         panic_nand_get_device(chip, mtd, FL_WRITING);
2663
2664         ops.len = len;
2665         ops.datbuf = (uint8_t *)buf;
2666         ops.oobbuf = NULL;
2667         ops.mode = MTD_OPS_PLACE_OOB;
2668
2669         ret = nand_do_write_ops(mtd, to, &ops);
2670
2671         *retlen = ops.retlen;
2672         return ret;
2673 }
2674
2675 /**
2676  * nand_write - [MTD Interface] NAND write with ECC
2677  * @mtd: MTD device structure
2678  * @to: offset to write to
2679  * @len: number of bytes to write
2680  * @retlen: pointer to variable to store the number of written bytes
2681  * @buf: the data to write
2682  *
2683  * NAND write with ECC.
2684  */
2685 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2686                           size_t *retlen, const uint8_t *buf)
2687 {
2688         struct mtd_oob_ops ops;
2689         int ret;
2690
2691         nand_get_device(mtd, FL_WRITING);
2692         ops.len = len;
2693         ops.datbuf = (uint8_t *)buf;
2694         ops.oobbuf = NULL;
2695         ops.mode = MTD_OPS_PLACE_OOB;
2696         ret = nand_do_write_ops(mtd, to, &ops);
2697         *retlen = ops.retlen;
2698         nand_release_device(mtd);
2699         return ret;
2700 }
2701
2702 /**
2703  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2704  * @mtd: MTD device structure
2705  * @to: offset to write to
2706  * @ops: oob operation description structure
2707  *
2708  * NAND write out-of-band.
2709  */
2710 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2711                              struct mtd_oob_ops *ops)
2712 {
2713         int chipnr, page, status, len;
2714         struct nand_chip *chip = mtd->priv;
2715
2716         pr_debug("%s: to = 0x%08x, len = %i\n",
2717                          __func__, (unsigned int)to, (int)ops->ooblen);
2718
2719         if (ops->mode == MTD_OPS_AUTO_OOB)
2720                 len = chip->ecc.layout->oobavail;
2721         else
2722                 len = mtd->oobsize;
2723
2724         /* Do not allow write past end of page */
2725         if ((ops->ooboffs + ops->ooblen) > len) {
2726                 pr_debug("%s: attempt to write past end of page\n",
2727                                 __func__);
2728                 return -EINVAL;
2729         }
2730
2731         if (unlikely(ops->ooboffs >= len)) {
2732                 pr_debug("%s: attempt to start write outside oob\n",
2733                                 __func__);
2734                 return -EINVAL;
2735         }
2736
2737         /* Do not allow write past end of device */
2738         if (unlikely(to >= mtd->size ||
2739                      ops->ooboffs + ops->ooblen >
2740                         ((mtd->size >> chip->page_shift) -
2741                          (to >> chip->page_shift)) * len)) {
2742                 pr_debug("%s: attempt to write beyond end of device\n",
2743                                 __func__);
2744                 return -EINVAL;
2745         }
2746
2747         chipnr = (int)(to >> chip->chip_shift);
2748         chip->select_chip(mtd, chipnr);
2749
2750         /* Shift to get page */
2751         page = (int)(to >> chip->page_shift);
2752
2753         /*
2754          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2755          * of my DiskOnChip 2000 test units) will clear the whole data page too
2756          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2757          * it in the doc2000 driver in August 1999.  dwmw2.
2758          */
2759         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2760
2761         /* Check, if it is write protected */
2762         if (nand_check_wp(mtd)) {
2763                 chip->select_chip(mtd, -1);
2764                 return -EROFS;
2765         }
2766
2767         /* Invalidate the page cache, if we write to the cached page */
2768         if (page == chip->pagebuf)
2769                 chip->pagebuf = -1;
2770
2771         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2772
2773         if (ops->mode == MTD_OPS_RAW)
2774                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2775         else
2776                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2777
2778         chip->select_chip(mtd, -1);
2779
2780         if (status)
2781                 return status;
2782
2783         ops->oobretlen = ops->ooblen;
2784
2785         return 0;
2786 }
2787
2788 /**
2789  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2790  * @mtd: MTD device structure
2791  * @to: offset to write to
2792  * @ops: oob operation description structure
2793  */
2794 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2795                           struct mtd_oob_ops *ops)
2796 {
2797         int ret = -ENOTSUPP;
2798
2799         ops->retlen = 0;
2800
2801         /* Do not allow writes past end of device */
2802         if (ops->datbuf && (to + ops->len) > mtd->size) {
2803                 pr_debug("%s: attempt to write beyond end of device\n",
2804                                 __func__);
2805                 return -EINVAL;
2806         }
2807
2808         nand_get_device(mtd, FL_WRITING);
2809
2810         switch (ops->mode) {
2811         case MTD_OPS_PLACE_OOB:
2812         case MTD_OPS_AUTO_OOB:
2813         case MTD_OPS_RAW:
2814                 break;
2815
2816         default:
2817                 goto out;
2818         }
2819
2820         if (!ops->datbuf)
2821                 ret = nand_do_write_oob(mtd, to, ops);
2822         else
2823                 ret = nand_do_write_ops(mtd, to, ops);
2824
2825 out:
2826         nand_release_device(mtd);
2827         return ret;
2828 }
2829
2830 /**
2831  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2832  * @mtd: MTD device structure
2833  * @page: the page address of the block which will be erased
2834  *
2835  * Standard erase command for NAND chips.
2836  */
2837 static void single_erase_cmd(struct mtd_info *mtd, int page)
2838 {
2839         struct nand_chip *chip = mtd->priv;
2840         /* Send commands to erase a block */
2841         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2842         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2843 }
2844
2845 /**
2846  * nand_erase - [MTD Interface] erase block(s)
2847  * @mtd: MTD device structure
2848  * @instr: erase instruction
2849  *
2850  * Erase one ore more blocks.
2851  */
2852 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2853 {
2854         return nand_erase_nand(mtd, instr, 0);
2855 }
2856
2857 /**
2858  * nand_erase_nand - [INTERN] erase block(s)
2859  * @mtd: MTD device structure
2860  * @instr: erase instruction
2861  * @allowbbt: allow erasing the bbt area
2862  *
2863  * Erase one ore more blocks.
2864  */
2865 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2866                     int allowbbt)
2867 {
2868         int page, status, pages_per_block, ret, chipnr;
2869         struct nand_chip *chip = mtd->priv;
2870         loff_t len;
2871
2872         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2873                         __func__, (unsigned long long)instr->addr,
2874                         (unsigned long long)instr->len);
2875
2876         if (check_offs_len(mtd, instr->addr, instr->len))
2877                 return -EINVAL;
2878
2879         /* Grab the lock and see if the device is available */
2880         nand_get_device(mtd, FL_ERASING);
2881
2882         /* Shift to get first page */
2883         page = (int)(instr->addr >> chip->page_shift);
2884         chipnr = (int)(instr->addr >> chip->chip_shift);
2885
2886         /* Calculate pages in each block */
2887         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2888
2889         /* Select the NAND device */
2890         chip->select_chip(mtd, chipnr);
2891
2892         /* Check, if it is write protected */
2893         if (nand_check_wp(mtd)) {
2894                 pr_debug("%s: device is write protected!\n",
2895                                 __func__);
2896                 instr->state = MTD_ERASE_FAILED;
2897                 goto erase_exit;
2898         }
2899
2900         /* Loop through the pages */
2901         len = instr->len;
2902
2903         instr->state = MTD_ERASING;
2904
2905         while (len) {
2906                 WATCHDOG_RESET();
2907
2908                 /* Check if we have a bad block, we do not erase bad blocks! */
2909                 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2910                                         chip->page_shift, 0, allowbbt)) {
2911                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2912                                     __func__, page);
2913                         instr->state = MTD_ERASE_FAILED;
2914                         goto erase_exit;
2915                 }
2916
2917                 /*
2918                  * Invalidate the page cache, if we erase the block which
2919                  * contains the current cached page.
2920                  */
2921                 if (page <= chip->pagebuf && chip->pagebuf <
2922                     (page + pages_per_block))
2923                         chip->pagebuf = -1;
2924
2925                 chip->erase_cmd(mtd, page & chip->pagemask);
2926
2927                 status = chip->waitfunc(mtd, chip);
2928
2929                 /*
2930                  * See if operation failed and additional status checks are
2931                  * available
2932                  */
2933                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2934                         status = chip->errstat(mtd, chip, FL_ERASING,
2935                                                status, page);
2936
2937                 /* See if block erase succeeded */
2938                 if (status & NAND_STATUS_FAIL) {
2939                         pr_debug("%s: failed erase, page 0x%08x\n",
2940                                         __func__, page);
2941                         instr->state = MTD_ERASE_FAILED;
2942                         instr->fail_addr =
2943                                 ((loff_t)page << chip->page_shift);
2944                         goto erase_exit;
2945                 }
2946
2947                 /* Increment page address and decrement length */
2948                 len -= (1ULL << chip->phys_erase_shift);
2949                 page += pages_per_block;
2950
2951                 /* Check, if we cross a chip boundary */
2952                 if (len && !(page & chip->pagemask)) {
2953                         chipnr++;
2954                         chip->select_chip(mtd, -1);
2955                         chip->select_chip(mtd, chipnr);
2956                 }
2957         }
2958         instr->state = MTD_ERASE_DONE;
2959
2960 erase_exit:
2961
2962         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2963
2964         /* Deselect and wake up anyone waiting on the device */
2965         chip->select_chip(mtd, -1);
2966         nand_release_device(mtd);
2967
2968         /* Do call back function */
2969         if (!ret)
2970                 mtd_erase_callback(instr);
2971
2972         /* Return more or less happy */
2973         return ret;
2974 }
2975
2976 /**
2977  * nand_sync - [MTD Interface] sync
2978  * @mtd: MTD device structure
2979  *
2980  * Sync is actually a wait for chip ready function.
2981  */
2982 static void nand_sync(struct mtd_info *mtd)
2983 {
2984         pr_debug("%s: called\n", __func__);
2985
2986         /* Grab the lock and see if the device is available */
2987         nand_get_device(mtd, FL_SYNCING);
2988         /* Release it and go back */
2989         nand_release_device(mtd);
2990 }
2991
2992 /**
2993  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2994  * @mtd: MTD device structure
2995  * @offs: offset relative to mtd start
2996  */
2997 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2998 {
2999         return nand_block_checkbad(mtd, offs, 1, 0);
3000 }
3001
3002 /**
3003  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3004  * @mtd: MTD device structure
3005  * @ofs: offset relative to mtd start
3006  */
3007 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3008 {
3009         int ret;
3010
3011         ret = nand_block_isbad(mtd, ofs);
3012         if (ret) {
3013                 /* If it was bad already, return success and do nothing */
3014                 if (ret > 0)
3015                         return 0;
3016                 return ret;
3017         }
3018
3019         return nand_block_markbad_lowlevel(mtd, ofs);
3020 }
3021
3022 /**
3023  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3024  * @mtd: MTD device structure
3025  * @chip: nand chip info structure
3026  * @addr: feature address.
3027  * @subfeature_param: the subfeature parameters, a four bytes array.
3028  */
3029 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3030                         int addr, uint8_t *subfeature_param)
3031 {
3032         int status;
3033         int i;
3034
3035 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3036         if (!chip->onfi_version ||
3037             !(le16_to_cpu(chip->onfi_params.opt_cmd)
3038               & ONFI_OPT_CMD_SET_GET_FEATURES))
3039                 return -EINVAL;
3040 #endif
3041
3042         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3043         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3044                 chip->write_byte(mtd, subfeature_param[i]);
3045
3046         status = chip->waitfunc(mtd, chip);
3047         if (status & NAND_STATUS_FAIL)
3048                 return -EIO;
3049         return 0;
3050 }
3051
3052 /**
3053  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3054  * @mtd: MTD device structure
3055  * @chip: nand chip info structure
3056  * @addr: feature address.
3057  * @subfeature_param: the subfeature parameters, a four bytes array.
3058  */
3059 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3060                         int addr, uint8_t *subfeature_param)
3061 {
3062         int i;
3063
3064 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3065         if (!chip->onfi_version ||
3066             !(le16_to_cpu(chip->onfi_params.opt_cmd)
3067               & ONFI_OPT_CMD_SET_GET_FEATURES))
3068                 return -EINVAL;
3069 #endif
3070
3071         /* clear the sub feature parameters */
3072         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3073
3074         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3075         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3076                 *subfeature_param++ = chip->read_byte(mtd);
3077         return 0;
3078 }
3079
3080 #ifndef __UBOOT__
3081 /**
3082  * nand_suspend - [MTD Interface] Suspend the NAND flash
3083  * @mtd: MTD device structure
3084  */
3085 static int nand_suspend(struct mtd_info *mtd)
3086 {
3087         return nand_get_device(mtd, FL_PM_SUSPENDED);
3088 }
3089
3090 /**
3091  * nand_resume - [MTD Interface] Resume the NAND flash
3092  * @mtd: MTD device structure
3093  */
3094 static void nand_resume(struct mtd_info *mtd)
3095 {
3096         struct nand_chip *chip = mtd->priv;
3097
3098         if (chip->state == FL_PM_SUSPENDED)
3099                 nand_release_device(mtd);
3100         else
3101                 pr_err("%s called for a chip which is not in suspended state\n",
3102                         __func__);
3103 }
3104 #endif
3105
3106 /* Set default functions */
3107 static void nand_set_defaults(struct nand_chip *chip, int busw)
3108 {
3109         /* check for proper chip_delay setup, set 20us if not */
3110         if (!chip->chip_delay)
3111                 chip->chip_delay = 20;
3112
3113         /* check, if a user supplied command function given */
3114         if (chip->cmdfunc == NULL)
3115                 chip->cmdfunc = nand_command;
3116
3117         /* check, if a user supplied wait function given */
3118         if (chip->waitfunc == NULL)
3119                 chip->waitfunc = nand_wait;
3120
3121         if (!chip->select_chip)
3122                 chip->select_chip = nand_select_chip;
3123
3124         /* set for ONFI nand */
3125         if (!chip->onfi_set_features)
3126                 chip->onfi_set_features = nand_onfi_set_features;
3127         if (!chip->onfi_get_features)
3128                 chip->onfi_get_features = nand_onfi_get_features;
3129
3130         /* If called twice, pointers that depend on busw may need to be reset */
3131         if (!chip->read_byte || chip->read_byte == nand_read_byte)
3132                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3133         if (!chip->read_word)
3134                 chip->read_word = nand_read_word;
3135         if (!chip->block_bad)
3136                 chip->block_bad = nand_block_bad;
3137         if (!chip->block_markbad)
3138                 chip->block_markbad = nand_default_block_markbad;
3139         if (!chip->write_buf || chip->write_buf == nand_write_buf)
3140                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3141         if (!chip->write_byte || chip->write_byte == nand_write_byte)
3142                 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3143         if (!chip->read_buf || chip->read_buf == nand_read_buf)
3144                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3145         if (!chip->scan_bbt)
3146                 chip->scan_bbt = nand_default_bbt;
3147 #ifdef __UBOOT__
3148 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
3149         if (!chip->verify_buf)
3150                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
3151 #endif
3152 #endif
3153
3154         if (!chip->controller) {
3155                 chip->controller = &chip->hwcontrol;
3156                 spin_lock_init(&chip->controller->lock);
3157                 init_waitqueue_head(&chip->controller->wq);
3158         }
3159
3160 }
3161
3162 /* Sanitize ONFI strings so we can safely print them */
3163 #ifndef __UBOOT__
3164 static void sanitize_string(uint8_t *s, size_t len)
3165 #else
3166 static void sanitize_string(char *s, size_t len)
3167 #endif
3168 {
3169         ssize_t i;
3170
3171         /* Null terminate */
3172         s[len - 1] = 0;
3173
3174         /* Remove non printable chars */
3175         for (i = 0; i < len - 1; i++) {
3176                 if (s[i] < ' ' || s[i] > 127)
3177                         s[i] = '?';
3178         }
3179
3180         /* Remove trailing spaces */
3181         strim(s);
3182 }
3183
3184 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3185 {
3186         int i;
3187         while (len--) {
3188                 crc ^= *p++ << 8;
3189                 for (i = 0; i < 8; i++)
3190                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3191         }
3192
3193         return crc;
3194 }
3195
3196 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3197 /* Parse the Extended Parameter Page. */
3198 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3199                 struct nand_chip *chip, struct nand_onfi_params *p)
3200 {
3201         struct onfi_ext_param_page *ep;
3202         struct onfi_ext_section *s;
3203         struct onfi_ext_ecc_info *ecc;
3204         uint8_t *cursor;
3205         int ret = -EINVAL;
3206         int len;
3207         int i;
3208
3209         len = le16_to_cpu(p->ext_param_page_length) * 16;
3210         ep = kmalloc(len, GFP_KERNEL);
3211         if (!ep)
3212                 return -ENOMEM;
3213
3214         /* Send our own NAND_CMD_PARAM. */
3215         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3216
3217         /* Use the Change Read Column command to skip the ONFI param pages. */
3218         chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3219                         sizeof(*p) * p->num_of_param_pages , -1);
3220
3221         /* Read out the Extended Parameter Page. */
3222         chip->read_buf(mtd, (uint8_t *)ep, len);
3223         if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3224                 != le16_to_cpu(ep->crc))) {
3225                 pr_debug("fail in the CRC.\n");
3226                 goto ext_out;
3227         }
3228
3229         /*
3230          * Check the signature.
3231          * Do not strictly follow the ONFI spec, maybe changed in future.
3232          */
3233 #ifndef __UBOOT__
3234         if (strncmp(ep->sig, "EPPS", 4)) {
3235 #else
3236         if (strncmp((char *)ep->sig, "EPPS", 4)) {
3237 #endif
3238                 pr_debug("The signature is invalid.\n");
3239                 goto ext_out;
3240         }
3241
3242         /* find the ECC section. */
3243         cursor = (uint8_t *)(ep + 1);
3244         for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3245                 s = ep->sections + i;
3246                 if (s->type == ONFI_SECTION_TYPE_2)
3247                         break;
3248                 cursor += s->length * 16;
3249         }
3250         if (i == ONFI_EXT_SECTION_MAX) {
3251                 pr_debug("We can not find the ECC section.\n");
3252                 goto ext_out;
3253         }
3254
3255         /* get the info we want. */
3256         ecc = (struct onfi_ext_ecc_info *)cursor;
3257
3258         if (!ecc->codeword_size) {
3259                 pr_debug("Invalid codeword size\n");
3260                 goto ext_out;
3261         }
3262
3263         chip->ecc_strength_ds = ecc->ecc_bits;
3264         chip->ecc_step_ds = 1 << ecc->codeword_size;
3265         ret = 0;
3266
3267 ext_out:
3268         kfree(ep);
3269         return ret;
3270 }
3271
3272 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3273 {
3274         struct nand_chip *chip = mtd->priv;
3275         uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3276
3277         return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3278                         feature);
3279 }
3280
3281 /*
3282  * Configure chip properties from Micron vendor-specific ONFI table
3283  */
3284 static void nand_onfi_detect_micron(struct nand_chip *chip,
3285                 struct nand_onfi_params *p)
3286 {
3287         struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3288
3289         if (le16_to_cpu(p->vendor_revision) < 1)
3290                 return;
3291
3292         chip->read_retries = micron->read_retry_options;
3293         chip->setup_read_retry = nand_setup_read_retry_micron;
3294 }
3295
3296 /*
3297  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3298  */
3299 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3300                                         int *busw)
3301 {
3302         struct nand_onfi_params *p = &chip->onfi_params;
3303         int i, j;
3304         int val;
3305
3306         /* Try ONFI for unknown chip or LP */
3307         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3308         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3309                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3310                 return 0;
3311
3312         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3313         for (i = 0; i < 3; i++) {
3314                 for (j = 0; j < sizeof(*p); j++)
3315                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
3316                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3317                                 le16_to_cpu(p->crc)) {
3318                         break;
3319                 }
3320         }
3321
3322         if (i == 3) {
3323                 pr_err("Could not find valid ONFI parameter page; aborting\n");
3324                 return 0;
3325         }
3326
3327         /* Check version */
3328         val = le16_to_cpu(p->revision);
3329         if (val & (1 << 5))
3330                 chip->onfi_version = 23;
3331         else if (val & (1 << 4))
3332                 chip->onfi_version = 22;
3333         else if (val & (1 << 3))
3334                 chip->onfi_version = 21;
3335         else if (val & (1 << 2))
3336                 chip->onfi_version = 20;
3337         else if (val & (1 << 1))
3338                 chip->onfi_version = 10;
3339
3340         if (!chip->onfi_version) {
3341                 pr_info("unsupported ONFI version: %d\n", val);
3342                 return 0;
3343         }
3344
3345         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3346         sanitize_string(p->model, sizeof(p->model));
3347         if (!mtd->name)
3348                 mtd->name = p->model;
3349
3350         mtd->writesize = le32_to_cpu(p->byte_per_page);
3351
3352         /*
3353          * pages_per_block and blocks_per_lun may not be a power-of-2 size
3354          * (don't ask me who thought of this...). MTD assumes that these
3355          * dimensions will be power-of-2, so just truncate the remaining area.
3356          */
3357         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3358         mtd->erasesize *= mtd->writesize;
3359
3360         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3361
3362         /* See erasesize comment */
3363         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3364         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3365         chip->bits_per_cell = p->bits_per_cell;
3366
3367         if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3368                 *busw = NAND_BUSWIDTH_16;
3369         else
3370                 *busw = 0;
3371
3372         if (p->ecc_bits != 0xff) {
3373                 chip->ecc_strength_ds = p->ecc_bits;
3374                 chip->ecc_step_ds = 512;
3375         } else if (chip->onfi_version >= 21 &&
3376                 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3377
3378                 /*
3379                  * The nand_flash_detect_ext_param_page() uses the
3380                  * Change Read Column command which maybe not supported
3381                  * by the chip->cmdfunc. So try to update the chip->cmdfunc
3382                  * now. We do not replace user supplied command function.
3383                  */
3384                 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3385                         chip->cmdfunc = nand_command_lp;
3386
3387                 /* The Extended Parameter Page is supported since ONFI 2.1. */
3388                 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3389                         pr_warn("Failed to detect ONFI extended param page\n");
3390         } else {
3391                 pr_warn("Could not retrieve ONFI ECC requirements\n");
3392         }
3393
3394         if (p->jedec_id == NAND_MFR_MICRON)
3395                 nand_onfi_detect_micron(chip, p);
3396
3397         return 1;
3398 }
3399 #else
3400 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3401                                         int *busw)
3402 {
3403         return 0;
3404 }
3405 #endif
3406
3407 /*
3408  * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3409  */
3410 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3411                                         int *busw)
3412 {
3413         struct nand_jedec_params *p = &chip->jedec_params;
3414         struct jedec_ecc_info *ecc;
3415         int val;
3416         int i, j;
3417
3418         /* Try JEDEC for unknown chip or LP */
3419         chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3420         if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3421                 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3422                 chip->read_byte(mtd) != 'C')
3423                 return 0;
3424
3425         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3426         for (i = 0; i < 3; i++) {
3427                 for (j = 0; j < sizeof(*p); j++)
3428                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
3429
3430                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3431                                 le16_to_cpu(p->crc))
3432                         break;
3433         }
3434
3435         if (i == 3) {
3436                 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3437                 return 0;
3438         }
3439
3440         /* Check version */
3441         val = le16_to_cpu(p->revision);
3442         if (val & (1 << 2))
3443                 chip->jedec_version = 10;
3444         else if (val & (1 << 1))
3445                 chip->jedec_version = 1; /* vendor specific version */
3446
3447         if (!chip->jedec_version) {
3448                 pr_info("unsupported JEDEC version: %d\n", val);
3449                 return 0;
3450         }
3451
3452         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3453         sanitize_string(p->model, sizeof(p->model));
3454         if (!mtd->name)
3455                 mtd->name = p->model;
3456
3457         mtd->writesize = le32_to_cpu(p->byte_per_page);
3458
3459         /* Please reference to the comment for nand_flash_detect_onfi. */
3460         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3461         mtd->erasesize *= mtd->writesize;
3462
3463         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3464
3465         /* Please reference to the comment for nand_flash_detect_onfi. */
3466         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3467         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3468         chip->bits_per_cell = p->bits_per_cell;
3469
3470         if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3471                 *busw = NAND_BUSWIDTH_16;
3472         else
3473                 *busw = 0;
3474
3475         /* ECC info */
3476         ecc = &p->ecc_info[0];
3477
3478         if (ecc->codeword_size >= 9) {
3479                 chip->ecc_strength_ds = ecc->ecc_bits;
3480                 chip->ecc_step_ds = 1 << ecc->codeword_size;
3481         } else {
3482                 pr_warn("Invalid codeword size\n");
3483         }
3484
3485         return 1;
3486 }
3487
3488 /*
3489  * nand_id_has_period - Check if an ID string has a given wraparound period
3490  * @id_data: the ID string
3491  * @arrlen: the length of the @id_data array
3492  * @period: the period of repitition
3493  *
3494  * Check if an ID string is repeated within a given sequence of bytes at
3495  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3496  * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3497  * if the repetition has a period of @period; otherwise, returns zero.
3498  */
3499 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3500 {
3501         int i, j;
3502         for (i = 0; i < period; i++)
3503                 for (j = i + period; j < arrlen; j += period)
3504                         if (id_data[i] != id_data[j])
3505                                 return 0;
3506         return 1;
3507 }
3508
3509 /*
3510  * nand_id_len - Get the length of an ID string returned by CMD_READID
3511  * @id_data: the ID string
3512  * @arrlen: the length of the @id_data array
3513
3514  * Returns the length of the ID string, according to known wraparound/trailing
3515  * zero patterns. If no pattern exists, returns the length of the array.
3516  */
3517 static int nand_id_len(u8 *id_data, int arrlen)
3518 {
3519         int last_nonzero, period;
3520
3521         /* Find last non-zero byte */
3522         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3523                 if (id_data[last_nonzero])
3524                         break;
3525
3526         /* All zeros */
3527         if (last_nonzero < 0)
3528                 return 0;
3529
3530         /* Calculate wraparound period */
3531         for (period = 1; period < arrlen; period++)
3532                 if (nand_id_has_period(id_data, arrlen, period))
3533                         break;
3534
3535         /* There's a repeated pattern */
3536         if (period < arrlen)
3537                 return period;
3538
3539         /* There are trailing zeros */
3540         if (last_nonzero < arrlen - 1)
3541                 return last_nonzero + 1;
3542
3543         /* No pattern detected */
3544         return arrlen;
3545 }
3546
3547 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3548 static int nand_get_bits_per_cell(u8 cellinfo)
3549 {
3550         int bits;
3551
3552         bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3553         bits >>= NAND_CI_CELLTYPE_SHIFT;
3554         return bits + 1;
3555 }
3556
3557 /*
3558  * Many new NAND share similar device ID codes, which represent the size of the
3559  * chip. The rest of the parameters must be decoded according to generic or
3560  * manufacturer-specific "extended ID" decoding patterns.
3561  */
3562 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3563                                 u8 id_data[8], int *busw)
3564 {
3565         int extid, id_len;
3566         /* The 3rd id byte holds MLC / multichip data */
3567         chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3568         /* The 4th id byte is the important one */
3569         extid = id_data[3];
3570
3571         id_len = nand_id_len(id_data, 8);
3572
3573         /*
3574          * Field definitions are in the following datasheets:
3575          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3576          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3577          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
3578          *
3579          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3580          * ID to decide what to do.
3581          */
3582         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3583                         !nand_is_slc(chip) && id_data[5] != 0x00) {
3584                 /* Calc pagesize */
3585                 mtd->writesize = 2048 << (extid & 0x03);
3586                 extid >>= 2;
3587                 /* Calc oobsize */
3588                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3589                 case 1:
3590                         mtd->oobsize = 128;
3591                         break;
3592                 case 2:
3593                         mtd->oobsize = 218;
3594                         break;
3595                 case 3:
3596                         mtd->oobsize = 400;
3597                         break;
3598                 case 4:
3599                         mtd->oobsize = 436;
3600                         break;
3601                 case 5:
3602                         mtd->oobsize = 512;
3603                         break;
3604                 case 6:
3605                         mtd->oobsize = 640;
3606                         break;
3607                 case 7:
3608                 default: /* Other cases are "reserved" (unknown) */
3609                         mtd->oobsize = 1024;
3610                         break;
3611                 }
3612                 extid >>= 2;
3613                 /* Calc blocksize */
3614                 mtd->erasesize = (128 * 1024) <<
3615                         (((extid >> 1) & 0x04) | (extid & 0x03));
3616                 *busw = 0;
3617         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3618                         !nand_is_slc(chip)) {
3619                 unsigned int tmp;
3620
3621                 /* Calc pagesize */
3622                 mtd->writesize = 2048 << (extid & 0x03);
3623                 extid >>= 2;
3624                 /* Calc oobsize */
3625                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3626                 case 0:
3627                         mtd->oobsize = 128;
3628                         break;
3629                 case 1:
3630                         mtd->oobsize = 224;
3631                         break;
3632                 case 2:
3633                         mtd->oobsize = 448;
3634                         break;
3635                 case 3:
3636                         mtd->oobsize = 64;
3637                         break;
3638                 case 4:
3639                         mtd->oobsize = 32;
3640                         break;
3641                 case 5:
3642                         mtd->oobsize = 16;
3643                         break;
3644                 default:
3645                         mtd->oobsize = 640;
3646                         break;
3647                 }
3648                 extid >>= 2;
3649                 /* Calc blocksize */
3650                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3651                 if (tmp < 0x03)
3652                         mtd->erasesize = (128 * 1024) << tmp;
3653                 else if (tmp == 0x03)
3654                         mtd->erasesize = 768 * 1024;
3655                 else
3656                         mtd->erasesize = (64 * 1024) << tmp;
3657                 *busw = 0;
3658         } else {
3659                 /* Calc pagesize */
3660                 mtd->writesize = 1024 << (extid & 0x03);
3661                 extid >>= 2;
3662                 /* Calc oobsize */
3663                 mtd->oobsize = (8 << (extid & 0x01)) *
3664                         (mtd->writesize >> 9);
3665                 extid >>= 2;
3666                 /* Calc blocksize. Blocksize is multiples of 64KiB */
3667                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3668                 extid >>= 2;
3669                 /* Get buswidth information */
3670                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3671
3672                 /*
3673                  * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3674                  * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3675                  * follows:
3676                  * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3677                  *                         110b -> 24nm
3678                  * - ID byte 5, bit[7]:    1 -> BENAND, 0 -> raw SLC
3679                  */
3680                 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3681                                 nand_is_slc(chip) &&
3682                                 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3683                                 !(id_data[4] & 0x80) /* !BENAND */) {
3684                         mtd->oobsize = 32 * mtd->writesize >> 9;
3685                 }
3686
3687         }
3688 }
3689
3690 /*
3691  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3692  * decodes a matching ID table entry and assigns the MTD size parameters for
3693  * the chip.
3694  */
3695 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3696                                 struct nand_flash_dev *type, u8 id_data[8],
3697                                 int *busw)
3698 {
3699         int maf_id = id_data[0];
3700
3701         mtd->erasesize = type->erasesize;
3702         mtd->writesize = type->pagesize;
3703         mtd->oobsize = mtd->writesize / 32;
3704         *busw = type->options & NAND_BUSWIDTH_16;
3705
3706         /* All legacy ID NAND are small-page, SLC */
3707         chip->bits_per_cell = 1;
3708
3709         /*
3710          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3711          * some Spansion chips have erasesize that conflicts with size
3712          * listed in nand_ids table.
3713          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3714          */
3715         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3716                         && id_data[6] == 0x00 && id_data[7] == 0x00
3717                         && mtd->writesize == 512) {
3718                 mtd->erasesize = 128 * 1024;
3719                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3720         }
3721 }
3722
3723 /*
3724  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3725  * heuristic patterns using various detected parameters (e.g., manufacturer,
3726  * page size, cell-type information).
3727  */
3728 static void nand_decode_bbm_options(struct mtd_info *mtd,
3729                                     struct nand_chip *chip, u8 id_data[8])
3730 {
3731         int maf_id = id_data[0];
3732
3733         /* Set the bad block position */
3734         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3735                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3736         else
3737                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3738
3739         /*
3740          * Bad block marker is stored in the last page of each block on Samsung
3741          * and Hynix MLC devices; stored in first two pages of each block on
3742          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3743          * AMD/Spansion, and Macronix.  All others scan only the first page.
3744          */
3745         if (!nand_is_slc(chip) &&
3746                         (maf_id == NAND_MFR_SAMSUNG ||
3747                          maf_id == NAND_MFR_HYNIX))
3748                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3749         else if ((nand_is_slc(chip) &&
3750                                 (maf_id == NAND_MFR_SAMSUNG ||
3751                                  maf_id == NAND_MFR_HYNIX ||
3752                                  maf_id == NAND_MFR_TOSHIBA ||
3753                                  maf_id == NAND_MFR_AMD ||
3754                                  maf_id == NAND_MFR_MACRONIX)) ||
3755                         (mtd->writesize == 2048 &&
3756                          maf_id == NAND_MFR_MICRON))
3757                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3758 }
3759
3760 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3761 {
3762         return type->id_len;
3763 }
3764
3765 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3766                    struct nand_flash_dev *type, u8 *id_data, int *busw)
3767 {
3768 #ifndef __UBOOT__
3769         if (!strncmp(type->id, id_data, type->id_len)) {
3770 #else
3771         if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3772 #endif
3773                 mtd->writesize = type->pagesize;
3774                 mtd->erasesize = type->erasesize;
3775                 mtd->oobsize = type->oobsize;
3776
3777                 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3778                 chip->chipsize = (uint64_t)type->chipsize << 20;
3779                 chip->options |= type->options;
3780                 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3781                 chip->ecc_step_ds = NAND_ECC_STEP(type);
3782
3783                 *busw = type->options & NAND_BUSWIDTH_16;
3784
3785                 if (!mtd->name)
3786                         mtd->name = type->name;
3787
3788                 return true;
3789         }
3790         return false;
3791 }
3792
3793 /*
3794  * Get the flash and manufacturer id and lookup if the type is supported.
3795  */
3796 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3797                                                   struct nand_chip *chip,
3798                                                   int *maf_id, int *dev_id,
3799                                                   struct nand_flash_dev *type)
3800 {
3801         int busw;
3802         int i, maf_idx;
3803         u8 id_data[8];
3804
3805         /* Select the device */
3806         chip->select_chip(mtd, 0);
3807
3808         /*
3809          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3810          * after power-up.
3811          */
3812         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3813
3814         /* Send the command for reading device ID */
3815         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3816
3817         /* Read manufacturer and device IDs */
3818         *maf_id = chip->read_byte(mtd);
3819         *dev_id = chip->read_byte(mtd);
3820
3821         /*
3822          * Try again to make sure, as some systems the bus-hold or other
3823          * interface concerns can cause random data which looks like a
3824          * possibly credible NAND flash to appear. If the two results do
3825          * not match, ignore the device completely.
3826          */
3827
3828         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3829
3830         /* Read entire ID string */
3831         for (i = 0; i < 8; i++)
3832                 id_data[i] = chip->read_byte(mtd);
3833
3834         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3835                 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3836                         *maf_id, *dev_id, id_data[0], id_data[1]);
3837                 return ERR_PTR(-ENODEV);
3838         }
3839
3840         if (!type)
3841                 type = nand_flash_ids;
3842
3843         for (; type->name != NULL; type++) {
3844                 if (is_full_id_nand(type)) {
3845                         if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3846                                 goto ident_done;
3847                 } else if (*dev_id == type->dev_id) {
3848                                 break;
3849                 }
3850         }
3851
3852         chip->onfi_version = 0;
3853         if (!type->name || !type->pagesize) {
3854                 /* Check is chip is ONFI compliant */
3855                 if (nand_flash_detect_onfi(mtd, chip, &busw))
3856                         goto ident_done;
3857
3858                 /* Check if the chip is JEDEC compliant */
3859                 if (nand_flash_detect_jedec(mtd, chip, &busw))
3860                         goto ident_done;
3861         }
3862
3863         if (!type->name)
3864                 return ERR_PTR(-ENODEV);
3865
3866         if (!mtd->name)
3867                 mtd->name = type->name;
3868
3869         chip->chipsize = (uint64_t)type->chipsize << 20;
3870
3871         if (!type->pagesize && chip->init_size) {
3872                 /* Set the pagesize, oobsize, erasesize by the driver */
3873                 busw = chip->init_size(mtd, chip, id_data);
3874         } else if (!type->pagesize) {
3875                 /* Decode parameters from extended ID */
3876                 nand_decode_ext_id(mtd, chip, id_data, &busw);
3877         } else {
3878                 nand_decode_id(mtd, chip, type, id_data, &busw);
3879         }
3880         /* Get chip options */
3881         chip->options |= type->options;
3882
3883         /*
3884          * Check if chip is not a Samsung device. Do not clear the
3885          * options for chips which do not have an extended id.
3886          */
3887         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3888                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3889 ident_done:
3890
3891         /* Try to identify manufacturer */
3892         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3893                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3894                         break;
3895         }
3896
3897         if (chip->options & NAND_BUSWIDTH_AUTO) {
3898                 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3899                 chip->options |= busw;
3900                 nand_set_defaults(chip, busw);
3901         } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3902                 /*
3903                  * Check, if buswidth is correct. Hardware drivers should set
3904                  * chip correct!
3905                  */
3906                 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3907                         *maf_id, *dev_id);
3908                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3909                 pr_warn("bus width %d instead %d bit\n",
3910                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3911                            busw ? 16 : 8);
3912                 return ERR_PTR(-EINVAL);
3913         }
3914
3915         nand_decode_bbm_options(mtd, chip, id_data);
3916
3917         /* Calculate the address shift from the page size */
3918         chip->page_shift = ffs(mtd->writesize) - 1;
3919         /* Convert chipsize to number of pages per chip -1 */
3920         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3921
3922         chip->bbt_erase_shift = chip->phys_erase_shift =
3923                 ffs(mtd->erasesize) - 1;
3924         if (chip->chipsize & 0xffffffff)
3925                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3926         else {
3927                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3928                 chip->chip_shift += 32 - 1;
3929         }
3930
3931         chip->badblockbits = 8;
3932         chip->erase_cmd = single_erase_cmd;
3933
3934         /* Do not replace user supplied command function! */
3935         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3936                 chip->cmdfunc = nand_command_lp;
3937
3938         pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3939                 *maf_id, *dev_id);
3940
3941 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3942         if (chip->onfi_version)
3943                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3944                                 chip->onfi_params.model);
3945         else if (chip->jedec_version)
3946                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3947                                 chip->jedec_params.model);
3948         else
3949                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3950                                 type->name);
3951 #else
3952         if (chip->jedec_version)
3953                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3954                                 chip->jedec_params.model);
3955         else
3956                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3957                                 type->name);
3958
3959         pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3960                 type->name);
3961 #endif
3962
3963         pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3964                 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3965                 mtd->writesize, mtd->oobsize);
3966         return type;
3967 }
3968
3969 /**
3970  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3971  * @mtd: MTD device structure
3972  * @maxchips: number of chips to scan for
3973  * @table: alternative NAND ID table
3974  *
3975  * This is the first phase of the normal nand_scan() function. It reads the
3976  * flash ID and sets up MTD fields accordingly.
3977  *
3978  * The mtd->owner field must be set to the module of the caller.
3979  */
3980 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3981                     struct nand_flash_dev *table)
3982 {
3983         int i, nand_maf_id, nand_dev_id;
3984         struct nand_chip *chip = mtd->priv;
3985         struct nand_flash_dev *type;
3986
3987         /* Set the default functions */
3988         nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3989
3990         /* Read the flash type */
3991         type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3992                                    &nand_dev_id, table);
3993
3994         if (IS_ERR(type)) {
3995                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3996                         pr_warn("No NAND device found\n");
3997                 chip->select_chip(mtd, -1);
3998                 return PTR_ERR(type);
3999         }
4000
4001         chip->select_chip(mtd, -1);
4002
4003         /* Check for a chip array */
4004         for (i = 1; i < maxchips; i++) {
4005                 chip->select_chip(mtd, i);
4006                 /* See comment in nand_get_flash_type for reset */
4007                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4008                 /* Send the command for reading device ID */
4009                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4010                 /* Read manufacturer and device IDs */
4011                 if (nand_maf_id != chip->read_byte(mtd) ||
4012                     nand_dev_id != chip->read_byte(mtd)) {
4013                         chip->select_chip(mtd, -1);
4014                         break;
4015                 }
4016                 chip->select_chip(mtd, -1);
4017         }
4018
4019 #ifdef DEBUG
4020         if (i > 1)
4021                 pr_info("%d chips detected\n", i);
4022 #endif
4023
4024         /* Store the number of chips and calc total size for mtd */
4025         chip->numchips = i;
4026         mtd->size = i * chip->chipsize;
4027
4028         return 0;
4029 }
4030 EXPORT_SYMBOL(nand_scan_ident);
4031
4032
4033 /**
4034  * nand_scan_tail - [NAND Interface] Scan for the NAND device
4035  * @mtd: MTD device structure
4036  *
4037  * This is the second phase of the normal nand_scan() function. It fills out
4038  * all the uninitialized function pointers with the defaults and scans for a
4039  * bad block table if appropriate.
4040  */
4041 int nand_scan_tail(struct mtd_info *mtd)
4042 {
4043         int i;
4044         struct nand_chip *chip = mtd->priv;
4045         struct nand_ecc_ctrl *ecc = &chip->ecc;
4046         struct nand_buffers *nbuf;
4047
4048         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4049         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4050                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
4051
4052         if (!(chip->options & NAND_OWN_BUFFERS)) {
4053 #ifndef __UBOOT__
4054                 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4055                                 + mtd->oobsize * 3, GFP_KERNEL);
4056                 if (!nbuf)
4057                         return -ENOMEM;
4058                 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4059                 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4060                 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4061 #else
4062                 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4063 #endif
4064
4065                 chip->buffers = nbuf;
4066         } else {
4067                 if (!chip->buffers)
4068                         return -ENOMEM;
4069         }
4070
4071         /* Set the internal oob buffer location, just after the page data */
4072         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4073
4074         /*
4075          * If no default placement scheme is given, select an appropriate one.
4076          */
4077         if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4078                 switch (mtd->oobsize) {
4079                 case 8:
4080                         ecc->layout = &nand_oob_8;
4081                         break;
4082                 case 16:
4083                         ecc->layout = &nand_oob_16;
4084                         break;
4085                 case 64:
4086                         ecc->layout = &nand_oob_64;
4087                         break;
4088                 case 128:
4089                         ecc->layout = &nand_oob_128;
4090                         break;
4091                 default:
4092                         pr_warn("No oob scheme defined for oobsize %d\n",
4093                                    mtd->oobsize);
4094                         BUG();
4095                 }
4096         }
4097
4098         if (!chip->write_page)
4099                 chip->write_page = nand_write_page;
4100
4101         /*
4102          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4103          * selected and we have 256 byte pagesize fallback to software ECC
4104          */
4105
4106         switch (ecc->mode) {
4107         case NAND_ECC_HW_OOB_FIRST:
4108                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4109                 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4110                         pr_warn("No ECC functions supplied; "
4111                                    "hardware ECC not possible\n");
4112                         BUG();
4113                 }
4114                 if (!ecc->read_page)
4115                         ecc->read_page = nand_read_page_hwecc_oob_first;
4116
4117         case NAND_ECC_HW:
4118                 /* Use standard hwecc read page function? */
4119                 if (!ecc->read_page)
4120                         ecc->read_page = nand_read_page_hwecc;
4121                 if (!ecc->write_page)
4122                         ecc->write_page = nand_write_page_hwecc;
4123                 if (!ecc->read_page_raw)
4124                         ecc->read_page_raw = nand_read_page_raw;
4125                 if (!ecc->write_page_raw)
4126                         ecc->write_page_raw = nand_write_page_raw;
4127                 if (!ecc->read_oob)
4128                         ecc->read_oob = nand_read_oob_std;
4129                 if (!ecc->write_oob)
4130                         ecc->write_oob = nand_write_oob_std;
4131                 if (!ecc->read_subpage)
4132                         ecc->read_subpage = nand_read_subpage;
4133                 if (!ecc->write_subpage)
4134                         ecc->write_subpage = nand_write_subpage_hwecc;
4135
4136         case NAND_ECC_HW_SYNDROME:
4137                 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4138                     (!ecc->read_page ||
4139                      ecc->read_page == nand_read_page_hwecc ||
4140                      !ecc->write_page ||
4141                      ecc->write_page == nand_write_page_hwecc)) {
4142                         pr_warn("No ECC functions supplied; "
4143                                    "hardware ECC not possible\n");
4144                         BUG();
4145                 }
4146                 /* Use standard syndrome read/write page function? */
4147                 if (!ecc->read_page)
4148                         ecc->read_page = nand_read_page_syndrome;
4149                 if (!ecc->write_page)
4150                         ecc->write_page = nand_write_page_syndrome;
4151                 if (!ecc->read_page_raw)
4152                         ecc->read_page_raw = nand_read_page_raw_syndrome;
4153                 if (!ecc->write_page_raw)
4154                         ecc->write_page_raw = nand_write_page_raw_syndrome;
4155                 if (!ecc->read_oob)
4156                         ecc->read_oob = nand_read_oob_syndrome;
4157                 if (!ecc->write_oob)
4158                         ecc->write_oob = nand_write_oob_syndrome;
4159
4160                 if (mtd->writesize >= ecc->size) {
4161                         if (!ecc->strength) {
4162                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4163                                 BUG();
4164                         }
4165                         break;
4166                 }
4167                 pr_warn("%d byte HW ECC not possible on "
4168                            "%d byte page size, fallback to SW ECC\n",
4169                            ecc->size, mtd->writesize);
4170                 ecc->mode = NAND_ECC_SOFT;
4171
4172         case NAND_ECC_SOFT:
4173                 ecc->calculate = nand_calculate_ecc;
4174                 ecc->correct = nand_correct_data;
4175                 ecc->read_page = nand_read_page_swecc;
4176                 ecc->read_subpage = nand_read_subpage;
4177                 ecc->write_page = nand_write_page_swecc;
4178                 ecc->read_page_raw = nand_read_page_raw;
4179                 ecc->write_page_raw = nand_write_page_raw;
4180                 ecc->read_oob = nand_read_oob_std;
4181                 ecc->write_oob = nand_write_oob_std;
4182                 if (!ecc->size)
4183                         ecc->size = 256;
4184                 ecc->bytes = 3;
4185                 ecc->strength = 1;
4186                 break;
4187
4188         case NAND_ECC_SOFT_BCH:
4189                 if (!mtd_nand_has_bch()) {
4190                         pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4191                         BUG();
4192                 }
4193                 ecc->calculate = nand_bch_calculate_ecc;
4194                 ecc->correct = nand_bch_correct_data;
4195                 ecc->read_page = nand_read_page_swecc;
4196                 ecc->read_subpage = nand_read_subpage;
4197                 ecc->write_page = nand_write_page_swecc;
4198                 ecc->read_page_raw = nand_read_page_raw;
4199                 ecc->write_page_raw = nand_write_page_raw;
4200                 ecc->read_oob = nand_read_oob_std;
4201                 ecc->write_oob = nand_write_oob_std;
4202                 /*
4203                  * Board driver should supply ecc.size and ecc.bytes values to
4204                  * select how many bits are correctable; see nand_bch_init()
4205                  * for details. Otherwise, default to 4 bits for large page
4206                  * devices.
4207                  */
4208                 if (!ecc->size && (mtd->oobsize >= 64)) {
4209                         ecc->size = 512;
4210                         ecc->bytes = 7;
4211                 }
4212                 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4213                                                &ecc->layout);
4214                 if (!ecc->priv) {
4215                         pr_warn("BCH ECC initialization failed!\n");
4216                         BUG();
4217                 }
4218                 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4219                 break;
4220
4221         case NAND_ECC_NONE:
4222                 pr_warn("NAND_ECC_NONE selected by board driver. "
4223                            "This is not recommended!\n");
4224                 ecc->read_page = nand_read_page_raw;
4225                 ecc->write_page = nand_write_page_raw;
4226                 ecc->read_oob = nand_read_oob_std;
4227                 ecc->read_page_raw = nand_read_page_raw;
4228                 ecc->write_page_raw = nand_write_page_raw;
4229                 ecc->write_oob = nand_write_oob_std;
4230                 ecc->size = mtd->writesize;
4231                 ecc->bytes = 0;
4232                 ecc->strength = 0;
4233                 break;
4234
4235         default:
4236                 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4237                 BUG();
4238         }
4239
4240         /* For many systems, the standard OOB write also works for raw */
4241         if (!ecc->read_oob_raw)
4242                 ecc->read_oob_raw = ecc->read_oob;
4243         if (!ecc->write_oob_raw)
4244                 ecc->write_oob_raw = ecc->write_oob;
4245
4246         /*
4247          * The number of bytes available for a client to place data into
4248          * the out of band area.
4249          */
4250         ecc->layout->oobavail = 0;
4251         for (i = 0; ecc->layout->oobfree[i].length
4252                         && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4253                 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4254         mtd->oobavail = ecc->layout->oobavail;
4255
4256         /*
4257          * Set the number of read / write steps for one page depending on ECC
4258          * mode.
4259          */
4260         ecc->steps = mtd->writesize / ecc->size;
4261         if (ecc->steps * ecc->size != mtd->writesize) {
4262                 pr_warn("Invalid ECC parameters\n");
4263                 pr_warn("steps=%d size=%d writesize=%d\n",
4264                         chip->ecc.steps, chip->ecc.size, mtd->writesize);
4265                 BUG();
4266         }
4267         ecc->total = ecc->steps * ecc->bytes;
4268
4269         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4270         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4271                 switch (ecc->steps) {
4272                 case 2:
4273                         mtd->subpage_sft = 1;
4274                         break;
4275                 case 4:
4276                 case 8:
4277                 case 16:
4278                         mtd->subpage_sft = 2;
4279                         break;
4280                 }
4281         }
4282         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4283
4284         /* Initialize state */
4285         chip->state = FL_READY;
4286
4287         /* Invalidate the pagebuffer reference */
4288         chip->pagebuf = -1;
4289
4290         /* Large page NAND with SOFT_ECC should support subpage reads */
4291         if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4292                 chip->options |= NAND_SUBPAGE_READ;
4293
4294         /* Fill in remaining MTD driver data */
4295         mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4296         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4297                                                 MTD_CAP_NANDFLASH;
4298         mtd->_erase = nand_erase;
4299 #ifndef __UBOOT__
4300         mtd->_point = NULL;
4301         mtd->_unpoint = NULL;
4302 #endif
4303         mtd->_read = nand_read;
4304         mtd->_write = nand_write;
4305         mtd->_panic_write = panic_nand_write;
4306         mtd->_read_oob = nand_read_oob;
4307         mtd->_write_oob = nand_write_oob;
4308         mtd->_sync = nand_sync;
4309         mtd->_lock = NULL;
4310         mtd->_unlock = NULL;
4311 #ifndef __UBOOT__
4312         mtd->_suspend = nand_suspend;
4313         mtd->_resume = nand_resume;
4314 #endif
4315         mtd->_block_isbad = nand_block_isbad;
4316         mtd->_block_markbad = nand_block_markbad;
4317         mtd->writebufsize = mtd->writesize;
4318
4319         /* propagate ecc info to mtd_info */
4320         mtd->ecclayout = ecc->layout;
4321         mtd->ecc_strength = ecc->strength;
4322         mtd->ecc_step_size = ecc->size;
4323         /*
4324          * Initialize bitflip_threshold to its default prior scan_bbt() call.
4325          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4326          * properly set.
4327          */
4328         if (!mtd->bitflip_threshold)
4329                 mtd->bitflip_threshold = mtd->ecc_strength;
4330
4331         return 0;
4332 }
4333 EXPORT_SYMBOL(nand_scan_tail);
4334
4335 /*
4336  * is_module_text_address() isn't exported, and it's mostly a pointless
4337  * test if this is a module _anyway_ -- they'd have to try _really_ hard
4338  * to call us from in-kernel code if the core NAND support is modular.
4339  */
4340 #ifdef MODULE
4341 #define caller_is_module() (1)
4342 #else
4343 #define caller_is_module() \
4344         is_module_text_address((unsigned long)__builtin_return_address(0))
4345 #endif
4346
4347 /**
4348  * nand_scan - [NAND Interface] Scan for the NAND device
4349  * @mtd: MTD device structure
4350  * @maxchips: number of chips to scan for
4351  *
4352  * This fills out all the uninitialized function pointers with the defaults.
4353  * The flash ID is read and the mtd/chip structures are filled with the
4354  * appropriate values. The mtd->owner field must be set to the module of the
4355  * caller.
4356  */
4357 int nand_scan(struct mtd_info *mtd, int maxchips)
4358 {
4359         int ret;
4360
4361         /* Many callers got this wrong, so check for it for a while... */
4362         if (!mtd->owner && caller_is_module()) {
4363                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4364                 BUG();
4365         }
4366
4367         ret = nand_scan_ident(mtd, maxchips, NULL);
4368         if (!ret)
4369                 ret = nand_scan_tail(mtd);
4370         return ret;
4371 }
4372 EXPORT_SYMBOL(nand_scan);
4373
4374 #ifndef __UBOOT__
4375 /**
4376  * nand_release - [NAND Interface] Free resources held by the NAND device
4377  * @mtd: MTD device structure
4378  */
4379 void nand_release(struct mtd_info *mtd)
4380 {
4381         struct nand_chip *chip = mtd->priv;
4382
4383         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4384                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4385
4386         mtd_device_unregister(mtd);
4387
4388         /* Free bad block table memory */
4389         kfree(chip->bbt);
4390         if (!(chip->options & NAND_OWN_BUFFERS))
4391                 kfree(chip->buffers);
4392
4393         /* Free bad block descriptor memory */
4394         if (chip->badblock_pattern && chip->badblock_pattern->options
4395                         & NAND_BBT_DYNAMICSTRUCT)
4396                 kfree(chip->badblock_pattern);
4397 }
4398 EXPORT_SYMBOL_GPL(nand_release);
4399
4400 static int __init nand_base_init(void)
4401 {
4402         led_trigger_register_simple("nand-disk", &nand_led_trigger);
4403         return 0;
4404 }
4405
4406 static void __exit nand_base_exit(void)
4407 {
4408         led_trigger_unregister_simple(nand_led_trigger);
4409 }
4410 #endif
4411
4412 module_init(nand_base_init);
4413 module_exit(nand_base_exit);
4414
4415 MODULE_LICENSE("GPL");
4416 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4417 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4418 MODULE_DESCRIPTION("Generic NAND flash driver code");