drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/mem.h>
  12 #include <linux/mtd/omap_gpmc.h>
  13 #include <linux/mtd/nand_ecc.h>
  14 #include <linux/bch.h>
  15 #include <linux/compiler.h>
  16 #include <nand.h>
  17 #include <linux/mtd/omap_elm.h>
  18
  19 #define BADBLOCK_MARKER_LENGTH  2
  20 #define SECTOR_BYTES            512
  21 #define ECCCLEAR                (0x1 << 8)
  22 #define ECCRESULTREG1           (0x1 << 0)
  23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  24 #define BCH4_BIT_PAD            4
  25
  26 #ifdef CONFIG_BCH
  27 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  28                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  29 #endif
  30 static uint8_t cs;
  31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  32
  33 /*
  34  * omap_nand_hwcontrol - Set the address pointers corretly for the
  35  *                      following address/data/command operation
  36  */
  37 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
  38                                 uint32_t ctrl)
  39 {
  40         register struct nand_chip *this = mtd->priv;
  41
  42         /*
  43          * Point the IO_ADDR to DATA and ADDRESS registers instead
  44          * of chip address
  45          */
  46         switch (ctrl) {
  47         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
  48                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  49                 break;
  50         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
  51                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
  52                 break;
  53         case NAND_CTRL_CHANGE | NAND_NCE:
  54                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  55                 break;
  56         }
  57
  58         if (cmd != NAND_CMD_NONE)
  59                 writeb(cmd, this->IO_ADDR_W);
  60 }
  61
  62 #ifdef CONFIG_SPL_BUILD
  63 /* Check wait pin as dev ready indicator */
  64 int omap_spl_dev_ready(struct mtd_info *mtd)
  65 {
  66         return gpmc_cfg->status & (1 << 8);
  67 }
  68 #endif
  69
  70
  71 /*
  72  * gen_true_ecc - This function will generate true ECC value, which
  73  * can be used when correcting data read from NAND flash memory core
  74  *
  75  * @ecc_buf:    buffer to store ecc code
  76  *
  77  * @return:     re-formatted ECC value
  78  */
  79 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
  80 {
  81         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
  82                 ((ecc_buf[2] & 0x0F) << 8);
  83 }
  84
  85 /*
  86  * omap_correct_data - Compares the ecc read from nand spare area with ECC
  87  * registers values and corrects one bit error if it has occured
  88  * Further details can be had from OMAP TRM and the following selected links:
  89  * http://en.wikipedia.org/wiki/Hamming_code
  90  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
  91  *
  92  * @mtd:                 MTD device structure
  93  * @dat:                 page data
  94  * @read_ecc:            ecc read from nand flash
  95  * @calc_ecc:            ecc read from ECC registers
  96  *
  97  * @return 0 if data is OK or corrected, else returns -1
  98  */
  99 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 100                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 101 {
 102         uint32_t orig_ecc, new_ecc, res, hm;
 103         uint16_t parity_bits, byte;
 104         uint8_t bit;
 105
 106         /* Regenerate the orginal ECC */
 107         orig_ecc = gen_true_ecc(read_ecc);
 108         new_ecc = gen_true_ecc(calc_ecc);
 109         /* Get the XOR of real ecc */
 110         res = orig_ecc ^ new_ecc;
 111         if (res) {
 112                 /* Get the hamming width */
 113                 hm = hweight32(res);
 114                 /* Single bit errors can be corrected! */
 115                 if (hm == 12) {
 116                         /* Correctable data! */
 117                         parity_bits = res >> 16;
 118                         bit = (parity_bits & 0x7);
 119                         byte = (parity_bits >> 3) & 0x1FF;
 120                         /* Flip the bit to correct */
 121                         dat[byte] ^= (0x1 << bit);
 122                 } else if (hm == 1) {
 123                         printf("Error: Ecc is wrong\n");
 124                         /* ECC itself is corrupted */
 125                         return 2;
 126                 } else {
 127                         /*
 128                          * hm distance != parity pairs OR one, could mean 2 bit
 129                          * error OR potentially be on a blank page..
 130                          * orig_ecc: contains spare area data from nand flash.
 131                          * new_ecc: generated ecc while reading data area.
 132                          * Note: if the ecc = 0, all data bits from which it was
 133                          * generated are 0xFF.
 134                          * The 3 byte(24 bits) ecc is generated per 512byte
 135                          * chunk of a page. If orig_ecc(from spare area)
 136                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 137                          * this means that data area is 0xFF and spare area is
 138                          * 0xFF. A sure sign of a erased page!
 139                          */
 140                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 141                                 return 0;
 142                         printf("Error: Bad compare! failed\n");
 143                         /* detected 2 bit error */
 144                         return -1;
 145                 }
 146         }
 147         return 0;
 148 }
 149
 150 /*
 151  * Driver configurations
 152  */
 153 struct omap_nand_info {
 154         struct bch_control *control;
 155         enum omap_ecc ecc_scheme;
 156 };
 157
 158 /*
 159  * This can be a single instance cause all current users have only one NAND
 160  * with nearly the same setup (BCH8, some with ELM and others with sw BCH
 161  * library).
 162  * When some users with other BCH strength will exists this have to change!
 163  */
 164 static __maybe_unused struct omap_nand_info omap_nand_info = {
 165         .control = NULL
 166 };
 167
 168 /*
 169  * omap_reverse_list - re-orders list elements in reverse order [internal]
 170  * @list:       pointer to start of list
 171  * @length:     length of list
 172 */
 173 void omap_reverse_list(u8 *list, unsigned int length)
 174 {
 175         unsigned int i, j;
 176         unsigned int half_length = length / 2;
 177         u8 tmp;
 178         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 179                 tmp = list[i];
 180                 list[i] = list[j];
 181                 list[j] = tmp;
 182         }
 183 }
 184
 185 /*
 186  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 187  * @mtd:        MTD device structure
 188  * @mode:       Read/Write mode
 189  */
 190 __maybe_unused
 191 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 192 {
 193         struct nand_chip        *nand   = mtd->priv;
 194         struct omap_nand_info   *info   = nand->priv;
 195         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 196         unsigned int ecc_algo = 0;
 197         unsigned int bch_type = 0;
 198         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 199         u32 ecc_size_config_val = 0;
 200         u32 ecc_config_val = 0;
 201
 202         /* configure GPMC for specific ecc-scheme */
 203         switch (info->ecc_scheme) {
 204         case OMAP_ECC_HAM1_CODE_SW:
 205                 return;
 206         case OMAP_ECC_HAM1_CODE_HW:
 207                 ecc_algo = 0x0;
 208                 bch_type = 0x0;
 209                 bch_wrapmode = 0x00;
 210                 eccsize0 = 0xFF;
 211                 eccsize1 = 0xFF;
 212                 break;
 213         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 214         case OMAP_ECC_BCH8_CODE_HW:
 215                 ecc_algo = 0x1;
 216                 bch_type = 0x1;
 217                 if (mode == NAND_ECC_WRITE) {
 218                         bch_wrapmode = 0x01;
 219                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 220                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 221                 } else {
 222                         bch_wrapmode = 0x01;
 223                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 224                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 225                 }
 226                 break;
 227         case OMAP_ECC_BCH16_CODE_HW:
 228                 ecc_algo = 0x1;
 229                 bch_type = 0x2;
 230                 if (mode == NAND_ECC_WRITE) {
 231                         bch_wrapmode = 0x01;
 232                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 233                         eccsize1 = 52; /* OOB bits in nibbles per sector */
 234                 } else {
 235                         bch_wrapmode = 0x01;
 236                         eccsize0 = 52; /* ECC bits in nibbles per sector */
 237                         eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
 238                 }
 239                 break;
 240         default:
 241                 return;
 242         }
 243         /* Clear ecc and enable bits */
 244         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 245         /* Configure ecc size for BCH */
 246         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 247         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 248
 249         /* Configure device details for BCH engine */
 250         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 251                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 252                         (bch_wrapmode << 8)     | /* wrap mode */
 253                         (dev_width << 7)        | /* bus width */
 254                         (0x0 << 4)              | /* number of sectors */
 255                         (cs <<  1)              | /* ECC CS */
 256                         (0x1));                   /* enable ECC */
 257         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 258 }
 259
 260 /*
 261  *  omap_calculate_ecc - Read ECC result
 262  *  @mtd:       MTD structure
 263  *  @dat:       unused
 264  *  @ecc_code:  ecc_code buffer
 265  *  Using noninverted ECC can be considered ugly since writing a blank
 266  *  page ie. padding will clear the ECC bytes. This is no problem as
 267  *  long nobody is trying to write data on the seemingly unused page.
 268  *  Reading an erased page will produce an ECC mismatch between
 269  *  generated and read ECC bytes that has to be dealt with separately.
 270  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 271  *  is used, the result of read will be 0x0 while the ECC offsets of the
 272  *  spare area will be 0xFF which will result in an ECC mismatch.
 273  */
 274 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 275                                 uint8_t *ecc_code)
 276 {
 277         struct nand_chip *chip = mtd->priv;
 278         struct omap_nand_info *info = chip->priv;
 279         uint32_t *ptr, val = 0;
 280         int8_t i = 0, j;
 281
 282         switch (info->ecc_scheme) {
 283         case OMAP_ECC_HAM1_CODE_HW:
 284                 val = readl(&gpmc_cfg->ecc1_result);
 285                 ecc_code[0] = val & 0xFF;
 286                 ecc_code[1] = (val >> 16) & 0xFF;
 287                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 288                 break;
 289 #ifdef CONFIG_BCH
 290         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 291 #endif
 292         case OMAP_ECC_BCH8_CODE_HW:
 293                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 294                 val = readl(ptr);
 295                 ecc_code[i++] = (val >>  0) & 0xFF;
 296                 ptr--;
 297                 for (j = 0; j < 3; j++) {
 298                         val = readl(ptr);
 299                         ecc_code[i++] = (val >> 24) & 0xFF;
 300                         ecc_code[i++] = (val >> 16) & 0xFF;
 301                         ecc_code[i++] = (val >>  8) & 0xFF;
 302                         ecc_code[i++] = (val >>  0) & 0xFF;
 303                         ptr--;
 304                 }
 305                 break;
 306         case OMAP_ECC_BCH16_CODE_HW:
 307                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
 308                 ecc_code[i++] = (val >>  8) & 0xFF;
 309                 ecc_code[i++] = (val >>  0) & 0xFF;
 310                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
 311                 ecc_code[i++] = (val >> 24) & 0xFF;
 312                 ecc_code[i++] = (val >> 16) & 0xFF;
 313                 ecc_code[i++] = (val >>  8) & 0xFF;
 314                 ecc_code[i++] = (val >>  0) & 0xFF;
 315                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
 316                 ecc_code[i++] = (val >> 24) & 0xFF;
 317                 ecc_code[i++] = (val >> 16) & 0xFF;
 318                 ecc_code[i++] = (val >>  8) & 0xFF;
 319                 ecc_code[i++] = (val >>  0) & 0xFF;
 320                 for (j = 3; j >= 0; j--) {
 321                         val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
 322                                                                         );
 323                         ecc_code[i++] = (val >> 24) & 0xFF;
 324                         ecc_code[i++] = (val >> 16) & 0xFF;
 325                         ecc_code[i++] = (val >>  8) & 0xFF;
 326                         ecc_code[i++] = (val >>  0) & 0xFF;
 327                 }
 328                 break;
 329         default:
 330                 return -EINVAL;
 331         }
 332         /* ECC scheme specific syndrome customizations */
 333         switch (info->ecc_scheme) {
 334         case OMAP_ECC_HAM1_CODE_HW:
 335                 break;
 336 #ifdef CONFIG_BCH
 337         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 338
 339                 for (i = 0; i < chip->ecc.bytes; i++)
 340                         *(ecc_code + i) = *(ecc_code + i) ^
 341                                                 bch8_polynomial[i];
 342                 break;
 343 #endif
 344         case OMAP_ECC_BCH8_CODE_HW:
 345                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 346                 break;
 347         case OMAP_ECC_BCH16_CODE_HW:
 348                 break;
 349         default:
 350                 return -EINVAL;
 351         }
 352         return 0;
 353 }
 354
 355 #ifdef CONFIG_NAND_OMAP_ELM
 356 /*
 357  * omap_correct_data_bch - Compares the ecc read from nand spare area
 358  * with ECC registers values and corrects one bit error if it has occured
 359  *
 360  * @mtd:        MTD device structure
 361  * @dat:        page data
 362  * @read_ecc:   ecc read from nand flash (ignored)
 363  * @calc_ecc:   ecc read from ECC registers
 364  *
 365  * @return 0 if data is OK or corrected, else returns -1
 366  */
 367 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 368                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 369 {
 370         struct nand_chip *chip = mtd->priv;
 371         struct omap_nand_info *info = chip->priv;
 372         struct nand_ecc_ctrl *ecc = &chip->ecc;
 373         uint32_t error_count = 0, error_max;
 374         uint32_t error_loc[ELM_MAX_ERROR_COUNT];
 375         enum bch_level bch_type;
 376         uint32_t i, ecc_flag = 0;
 377         uint8_t count, err = 0;
 378         uint32_t byte_pos, bit_pos;
 379
 380         /* check calculated ecc */
 381         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 382                 if (calc_ecc[i] != 0x00)
 383                         ecc_flag = 1;
 384         }
 385         if (!ecc_flag)
 386                 return 0;
 387
 388         /* check for whether its a erased-page */
 389         ecc_flag = 0;
 390         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 391                 if (read_ecc[i] != 0xff)
 392                         ecc_flag = 1;
 393         }
 394         if (!ecc_flag)
 395                 return 0;
 396
 397         /*
 398          * while reading ECC result we read it in big endian.
 399          * Hence while loading to ELM we have rotate to get the right endian.
 400          */
 401         switch (info->ecc_scheme) {
 402         case OMAP_ECC_BCH8_CODE_HW:
 403                 bch_type = BCH_8_BIT;
 404                 omap_reverse_list(calc_ecc, ecc->bytes - 1);
 405                 break;
 406         case OMAP_ECC_BCH16_CODE_HW:
 407                 bch_type = BCH_16_BIT;
 408                 omap_reverse_list(calc_ecc, ecc->bytes);
 409                 break;
 410         default:
 411                 return -EINVAL;
 412         }
 413         /* use elm module to check for errors */
 414         elm_config(bch_type);
 415         err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
 416         if (err)
 417                 return err;
 418
 419         /* correct bch error */
 420         for (count = 0; count < error_count; count++) {
 421                 switch (info->ecc_scheme) {
 422                 case OMAP_ECC_BCH8_CODE_HW:
 423                         /* 14th byte in ECC is reserved to match ROM layout */
 424                         error_max = SECTOR_BYTES + (ecc->bytes - 1);
 425                         break;
 426                 case OMAP_ECC_BCH16_CODE_HW:
 427                         error_max = SECTOR_BYTES + ecc->bytes;
 428                         break;
 429                 default:
 430                         return -EINVAL;
 431                 }
 432                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 433                 bit_pos  = error_loc[count] % 8;
 434                 if (byte_pos < SECTOR_BYTES) {
 435                         dat[byte_pos] ^= 1 << bit_pos;
 436                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 437                 } else if (byte_pos < error_max) {
 438                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 439                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 440                                                                 SECTOR_BYTES);
 441                 } else {
 442                         err = -EBADMSG;
 443                         printf("nand: error: invalid bit-flip location\n");
 444                 }
 445         }
 446         return (err) ? err : error_count;
 447 }
 448
 449 /**
 450  * omap_read_page_bch - hardware ecc based page read function
 451  * @mtd:        mtd info structure
 452  * @chip:       nand chip info structure
 453  * @buf:        buffer to store read data
 454  * @oob_required: caller expects OOB data read to chip->oob_poi
 455  * @page:       page number to read
 456  *
 457  */
 458 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 459                                 uint8_t *buf, int oob_required, int page)
 460 {
 461         int i, eccsize = chip->ecc.size;
 462         int eccbytes = chip->ecc.bytes;
 463         int eccsteps = chip->ecc.steps;
 464         uint8_t *p = buf;
 465         uint8_t *ecc_calc = chip->buffers->ecccalc;
 466         uint8_t *ecc_code = chip->buffers->ecccode;
 467         uint32_t *eccpos = chip->ecc.layout->eccpos;
 468         uint8_t *oob = chip->oob_poi;
 469         uint32_t data_pos;
 470         uint32_t oob_pos;
 471
 472         data_pos = 0;
 473         /* oob area start */
 474         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
 475         oob += chip->ecc.layout->eccpos[0];
 476
 477         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 478                                 oob += eccbytes) {
 479                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 480                 /* read data */
 481                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
 482                 chip->read_buf(mtd, p, eccsize);
 483
 484                 /* read respective ecc from oob area */
 485                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
 486                 chip->read_buf(mtd, oob, eccbytes);
 487                 /* read syndrome */
 488                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 489
 490                 data_pos += eccsize;
 491                 oob_pos += eccbytes;
 492         }
 493
 494         for (i = 0; i < chip->ecc.total; i++)
 495                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 496
 497         eccsteps = chip->ecc.steps;
 498         p = buf;
 499
 500         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 501                 int stat;
 502
 503                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 504                 if (stat < 0)
 505                         mtd->ecc_stats.failed++;
 506                 else
 507                         mtd->ecc_stats.corrected += stat;
 508         }
 509         return 0;
 510 }
 511 #endif /* CONFIG_NAND_OMAP_ELM */
 512
 513 /*
 514  * OMAP3 BCH8 support (with BCH library)
 515  */
 516 #ifdef CONFIG_BCH
 517 /**
 518  * omap_correct_data_bch_sw - Decode received data and correct errors
 519  * @mtd: MTD device structure
 520  * @data: page data
 521  * @read_ecc: ecc read from nand flash
 522  * @calc_ecc: ecc read from HW ECC registers
 523  */
 524 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 525                                  u_char *read_ecc, u_char *calc_ecc)
 526 {
 527         int i, count;
 528         /* cannot correct more than 8 errors */
 529         unsigned int errloc[8];
 530         struct nand_chip *chip = mtd->priv;
 531         struct omap_nand_info *info = chip->priv;
 532
 533         count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 534                                                         NULL, errloc);
 535         if (count > 0) {
 536                 /* correct errors */
 537                 for (i = 0; i < count; i++) {
 538                         /* correct data only, not ecc bytes */
 539                         if (errloc[i] < 8*512)
 540                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 541                         printf("corrected bitflip %u\n", errloc[i]);
 542 #ifdef DEBUG
 543                         puts("read_ecc: ");
 544                         /*
 545                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 546                          * here!
 547                          */
 548                         for (i = 0; i < 13; i++)
 549                                 printf("%02x ", read_ecc[i]);
 550                         puts("\n");
 551                         puts("calc_ecc: ");
 552                         for (i = 0; i < 13; i++)
 553                                 printf("%02x ", calc_ecc[i]);
 554                         puts("\n");
 555 #endif
 556                 }
 557         } else if (count < 0) {
 558                 puts("ecc unrecoverable error\n");
 559         }
 560         return count;
 561 }
 562
 563 /**
 564  * omap_free_bch - Release BCH ecc resources
 565  * @mtd: MTD device structure
 566  */
 567 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 568 {
 569         struct nand_chip *chip = mtd->priv;
 570         struct omap_nand_info *info = chip->priv;
 571
 572         if (info->control) {
 573                 free_bch(info->control);
 574                 info->control = NULL;
 575         }
 576 }
 577 #endif /* CONFIG_BCH */
 578
 579 /**
 580  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 581  * @nand: NAND chip device structure
 582  * @ecc_scheme: ecc scheme to configure
 583  * @pagesize: number of main-area bytes per page of NAND device
 584  * @oobsize: number of OOB/spare bytes per page of NAND device
 585  */
 586 static int omap_select_ecc_scheme(struct nand_chip *nand,
 587         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 588         struct omap_nand_info   *info           = nand->priv;
 589         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 590         int eccsteps = pagesize / SECTOR_BYTES;
 591         int i;
 592
 593         switch (ecc_scheme) {
 594         case OMAP_ECC_HAM1_CODE_SW:
 595                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 596                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 597                  * initialized in nand_scan_tail(), so just set ecc.mode */
 598                 info->control           = NULL;
 599                 nand->ecc.mode          = NAND_ECC_SOFT;
 600                 nand->ecc.layout        = NULL;
 601                 nand->ecc.size          = 0;
 602                 break;
 603
 604         case OMAP_ECC_HAM1_CODE_HW:
 605                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 606                 /* check ecc-scheme requirements before updating ecc info */
 607                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 608                         printf("nand: error: insufficient OOB: require=%d\n", (
 609                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 610                         return -EINVAL;
 611                 }
 612                 info->control           = NULL;
 613                 /* populate ecc specific fields */
 614                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 615                 nand->ecc.mode          = NAND_ECC_HW;
 616                 nand->ecc.strength      = 1;
 617                 nand->ecc.size          = SECTOR_BYTES;
 618                 nand->ecc.bytes         = 3;
 619                 nand->ecc.hwctl         = omap_enable_hwecc;
 620                 nand->ecc.correct       = omap_correct_data;
 621                 nand->ecc.calculate     = omap_calculate_ecc;
 622                 /* define ecc-layout */
 623                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 624                 for (i = 0; i < ecclayout->eccbytes; i++) {
 625                         if (nand->options & NAND_BUSWIDTH_16)
 626                                 ecclayout->eccpos[i] = i + 2;
 627                         else
 628                                 ecclayout->eccpos[i] = i + 1;
 629                 }
 630                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 631                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 632                                                 BADBLOCK_MARKER_LENGTH;
 633                 break;
 634
 635         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 636 #ifdef CONFIG_BCH
 637                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 638                 /* check ecc-scheme requirements before updating ecc info */
 639                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 640                         printf("nand: error: insufficient OOB: require=%d\n", (
 641                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 642                         return -EINVAL;
 643                 }
 644                 /* check if BCH S/W library can be used for error detection */
 645                 info->control = init_bch(13, 8, 0x201b);
 646                 if (!info->control) {
 647                         printf("nand: error: could not init_bch()\n");
 648                         return -ENODEV;
 649                 }
 650                 /* populate ecc specific fields */
 651                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 652                 nand->ecc.mode          = NAND_ECC_HW;
 653                 nand->ecc.strength      = 8;
 654                 nand->ecc.size          = SECTOR_BYTES;
 655                 nand->ecc.bytes         = 13;
 656                 nand->ecc.hwctl         = omap_enable_hwecc;
 657                 nand->ecc.correct       = omap_correct_data_bch_sw;
 658                 nand->ecc.calculate     = omap_calculate_ecc;
 659                 /* define ecc-layout */
 660                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 661                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 662                 for (i = 1; i < ecclayout->eccbytes; i++) {
 663                         if (i % nand->ecc.bytes)
 664                                 ecclayout->eccpos[i] =
 665                                                 ecclayout->eccpos[i - 1] + 1;
 666                         else
 667                                 ecclayout->eccpos[i] =
 668                                                 ecclayout->eccpos[i - 1] + 2;
 669                 }
 670                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 671                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 672                                                 BADBLOCK_MARKER_LENGTH;
 673                 break;
 674 #else
 675                 printf("nand: error: CONFIG_BCH required for ECC\n");
 676                 return -EINVAL;
 677 #endif
 678
 679         case OMAP_ECC_BCH8_CODE_HW:
 680 #ifdef CONFIG_NAND_OMAP_ELM
 681                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 682                 /* check ecc-scheme requirements before updating ecc info */
 683                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 684                         printf("nand: error: insufficient OOB: require=%d\n", (
 685                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 686                         return -EINVAL;
 687                 }
 688                 /* intialize ELM for ECC error detection */
 689                 elm_init();
 690                 info->control           = NULL;
 691                 /* populate ecc specific fields */
 692                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 693                 nand->ecc.mode          = NAND_ECC_HW;
 694                 nand->ecc.strength      = 8;
 695                 nand->ecc.size          = SECTOR_BYTES;
 696                 nand->ecc.bytes         = 14;
 697                 nand->ecc.hwctl         = omap_enable_hwecc;
 698                 nand->ecc.correct       = omap_correct_data_bch;
 699                 nand->ecc.calculate     = omap_calculate_ecc;
 700                 nand->ecc.read_page     = omap_read_page_bch;
 701                 /* define ecc-layout */
 702                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 703                 for (i = 0; i < ecclayout->eccbytes; i++)
 704                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 705                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 706                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 707                                                 BADBLOCK_MARKER_LENGTH;
 708                 break;
 709 #else
 710                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 711                 return -EINVAL;
 712 #endif
 713
 714         case OMAP_ECC_BCH16_CODE_HW:
 715 #ifdef CONFIG_NAND_OMAP_ELM
 716                 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
 717                 /* check ecc-scheme requirements before updating ecc info */
 718                 if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 719                         printf("nand: error: insufficient OOB: require=%d\n", (
 720                                 (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 721                         return -EINVAL;
 722                 }
 723                 /* intialize ELM for ECC error detection */
 724                 elm_init();
 725                 /* populate ecc specific fields */
 726                 nand->ecc.mode          = NAND_ECC_HW;
 727                 nand->ecc.size          = SECTOR_BYTES;
 728                 nand->ecc.bytes         = 26;
 729                 nand->ecc.strength      = 16;
 730                 nand->ecc.hwctl         = omap_enable_hwecc;
 731                 nand->ecc.correct       = omap_correct_data_bch;
 732                 nand->ecc.calculate     = omap_calculate_ecc;
 733                 nand->ecc.read_page     = omap_read_page_bch;
 734                 /* define ecc-layout */
 735                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 736                 for (i = 0; i < ecclayout->eccbytes; i++)
 737                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 738                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 739                 ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
 740                                                 BADBLOCK_MARKER_LENGTH;
 741                 break;
 742 #else
 743                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 744                 return -EINVAL;
 745 #endif
 746         default:
 747                 debug("nand: error: ecc scheme not enabled or supported\n");
 748                 return -EINVAL;
 749         }
 750
 751         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
 752         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
 753                 nand->ecc.layout = ecclayout;
 754
 755         info->ecc_scheme = ecc_scheme;
 756         return 0;
 757 }
 758
 759 #ifndef CONFIG_SPL_BUILD
 760 /*
 761  * omap_nand_switch_ecc - switch the ECC operation between different engines
 762  * (h/w and s/w) and different algorithms (hamming and BCHx)
 763  *
 764  * @hardware            - true if one of the HW engines should be used
 765  * @eccstrength         - the number of bits that could be corrected
 766  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
 767  */
 768 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 769 {
 770         struct nand_chip *nand;
 771         struct mtd_info *mtd;
 772         int err = 0;
 773
 774         if (nand_curr_device < 0 ||
 775             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 776             !nand_info[nand_curr_device].name) {
 777                 printf("nand: error: no NAND devices found\n");
 778                 return -ENODEV;
 779         }
 780
 781         mtd = &nand_info[nand_curr_device];
 782         nand = mtd->priv;
 783         nand->options |= NAND_OWN_BUFFERS;
 784         nand->options &= ~NAND_SUBPAGE_READ;
 785         /* Setup the ecc configurations again */
 786         if (hardware) {
 787                 if (eccstrength == 1) {
 788                         err = omap_select_ecc_scheme(nand,
 789                                         OMAP_ECC_HAM1_CODE_HW,
 790                                         mtd->writesize, mtd->oobsize);
 791                 } else if (eccstrength == 8) {
 792                         err = omap_select_ecc_scheme(nand,
 793                                         OMAP_ECC_BCH8_CODE_HW,
 794                                         mtd->writesize, mtd->oobsize);
 795                 } else {
 796                         printf("nand: error: unsupported ECC scheme\n");
 797                         return -EINVAL;
 798                 }
 799         } else {
 800                 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 801                                         mtd->writesize, mtd->oobsize);
 802         }
 803
 804         /* Update NAND handling after ECC mode switch */
 805         if (!err)
 806                 err = nand_scan_tail(mtd);
 807         return err;
 808 }
 809 #endif /* CONFIG_SPL_BUILD */
 810
 811 /*
 812  * Board-specific NAND initialization. The following members of the
 813  * argument are board-specific:
 814  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
 815  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
 816  * - cmd_ctrl: hardwarespecific function for accesing control-lines
 817  * - waitfunc: hardwarespecific function for accesing device ready/busy line
 818  * - ecc.hwctl: function to enable (reset) hardware ecc generator
 819  * - ecc.mode: mode of ecc, see defines
 820  * - chip_delay: chip dependent delay for transfering data from array to
 821  *   read regs (tR)
 822  * - options: various chip options. They can partly be set to inform
 823  *   nand_scan about special functionality. See the defines for further
 824  *   explanation
 825  */
 826 int board_nand_init(struct nand_chip *nand)
 827 {
 828         int32_t gpmc_config = 0;
 829         cs = 0;
 830         int err = 0;
 831         /*
 832          * xloader/Uboot's gpmc configuration would have configured GPMC for
 833          * nand type of memory. The following logic scans and latches on to the
 834          * first CS with NAND type memory.
 835          * TBD: need to make this logic generic to handle multiple CS NAND
 836          * devices.
 837          */
 838         while (cs < GPMC_MAX_CS) {
 839                 /* Check if NAND type is set */
 840                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
 841                         /* Found it!! */
 842                         break;
 843                 }
 844                 cs++;
 845         }
 846         if (cs >= GPMC_MAX_CS) {
 847                 printf("nand: error: Unable to find NAND settings in "
 848                         "GPMC Configuration - quitting\n");
 849                 return -ENODEV;
 850         }
 851
 852         gpmc_config = readl(&gpmc_cfg->config);
 853         /* Disable Write protect */
 854         gpmc_config |= 0x10;
 855         writel(gpmc_config, &gpmc_cfg->config);
 856
 857         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 858         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 859         nand->priv      = &omap_nand_info;
 860         nand->cmd_ctrl  = omap_nand_hwcontrol;
 861         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
 862         nand->chip_delay = 100;
 863         nand->ecc.layout = &omap_ecclayout;
 864
 865         /* configure driver and controller based on NAND device bus-width */
 866         gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
 867 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
 868         nand->options |= NAND_BUSWIDTH_16;
 869         writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
 870 #else
 871         nand->options &= ~NAND_BUSWIDTH_16;
 872         writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
 873 #endif
 874         /* select ECC scheme */
 875 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
 876         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
 877                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
 878 #else
 879         /* pagesize and oobsize are not required to configure sw ecc-scheme */
 880         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 881                         0, 0);
 882 #endif
 883         if (err)
 884                 return err;
 885
 886 #ifdef CONFIG_SPL_BUILD
 887         if (nand->options & NAND_BUSWIDTH_16)
 888                 nand->read_buf = nand_read_buf16;
 889         else
 890                 nand->read_buf = nand_read_buf;
 891         nand->dev_ready = omap_spl_dev_ready;
 892 #endif
 893
 894         return 0;
 895 }