drivers/net/cpsw.c

   1 /*
   2  * CPSW Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <common.h>
  17 #include <command.h>
  18 #include <net.h>
  19 #include <miiphy.h>
  20 #include <malloc.h>
  21 #include <net.h>
  22 #include <netdev.h>
  23 #include <asm/errno.h>
  24 #include <asm/io.h>
  25 #include <phy.h>
  26 #include <asm/arch/cpu.h>
  27
  28 #define BITMASK(bits)           (BIT(bits) - 1)
  29 #define PHY_REG_MASK            0x1f
  30 #define PHY_ID_MASK             0x1f
  31 #define NUM_DESCS               (PKTBUFSRX * 2)
  32 #define PKT_MIN                 60
  33 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  34 #define CLEAR_BIT               1
  35 #define GIGABITEN               BIT(7)
  36 #define FULLDUPLEXEN            BIT(0)
  37 #define MIIEN                   BIT(15)
  38
  39 /* DMA Registers */
  40 #define CPDMA_TXCONTROL         0x004
  41 #define CPDMA_RXCONTROL         0x014
  42 #define CPDMA_SOFTRESET         0x01c
  43 #define CPDMA_RXFREE            0x0e0
  44 #define CPDMA_TXHDP_VER1        0x100
  45 #define CPDMA_TXHDP_VER2        0x200
  46 #define CPDMA_RXHDP_VER1        0x120
  47 #define CPDMA_RXHDP_VER2        0x220
  48 #define CPDMA_TXCP_VER1         0x140
  49 #define CPDMA_TXCP_VER2         0x240
  50 #define CPDMA_RXCP_VER1         0x160
  51 #define CPDMA_RXCP_VER2         0x260
  52
  53 #define CPDMA_RAM_ADDR          0x4a102000
  54
  55 /* Descriptor mode bits */
  56 #define CPDMA_DESC_SOP          BIT(31)
  57 #define CPDMA_DESC_EOP          BIT(30)
  58 #define CPDMA_DESC_OWNER        BIT(29)
  59 #define CPDMA_DESC_EOQ          BIT(28)
  60
  61 /*
  62  * This timeout definition is a worst-case ultra defensive measure against
  63  * unexpected controller lock ups.  Ideally, we should never ever hit this
  64  * scenario in practice.
  65  */
  66 #define MDIO_TIMEOUT            100 /* msecs */
  67 #define CPDMA_TIMEOUT           100 /* msecs */
  68
  69 struct cpsw_mdio_regs {
  70         u32     version;
  71         u32     control;
  72 #define CONTROL_IDLE            BIT(31)
  73 #define CONTROL_ENABLE          BIT(30)
  74
  75         u32     alive;
  76         u32     link;
  77         u32     linkintraw;
  78         u32     linkintmasked;
  79         u32     __reserved_0[2];
  80         u32     userintraw;
  81         u32     userintmasked;
  82         u32     userintmaskset;
  83         u32     userintmaskclr;
  84         u32     __reserved_1[20];
  85
  86         struct {
  87                 u32             access;
  88                 u32             physel;
  89 #define USERACCESS_GO           BIT(31)
  90 #define USERACCESS_WRITE        BIT(30)
  91 #define USERACCESS_ACK          BIT(29)
  92 #define USERACCESS_READ         0
  93 #define USERACCESS_DATA         0xffff
  94         } user[0];
  95 };
  96
  97 struct cpsw_regs {
  98         u32     id_ver;
  99         u32     control;
 100         u32     soft_reset;
 101         u32     stat_port_en;
 102         u32     ptype;
 103 };
 104
 105 struct cpsw_slave_regs {
 106         u32     max_blks;
 107         u32     blk_cnt;
 108         u32     flow_thresh;
 109         u32     port_vlan;
 110         u32     tx_pri_map;
 111         u32     gap_thresh;
 112         u32     sa_lo;
 113         u32     sa_hi;
 114 };
 115
 116 struct cpsw_host_regs {
 117         u32     max_blks;
 118         u32     blk_cnt;
 119         u32     flow_thresh;
 120         u32     port_vlan;
 121         u32     tx_pri_map;
 122         u32     cpdma_tx_pri_map;
 123         u32     cpdma_rx_chan_map;
 124 };
 125
 126 struct cpsw_sliver_regs {
 127         u32     id_ver;
 128         u32     mac_control;
 129         u32     mac_status;
 130         u32     soft_reset;
 131         u32     rx_maxlen;
 132         u32     __reserved_0;
 133         u32     rx_pause;
 134         u32     tx_pause;
 135         u32     __reserved_1;
 136         u32     rx_pri_map;
 137 };
 138
 139 #define ALE_ENTRY_BITS          68
 140 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 141
 142 /* ALE Registers */
 143 #define ALE_CONTROL             0x08
 144 #define ALE_UNKNOWNVLAN         0x18
 145 #define ALE_TABLE_CONTROL       0x20
 146 #define ALE_TABLE               0x34
 147 #define ALE_PORTCTL             0x40
 148
 149 #define ALE_TABLE_WRITE         BIT(31)
 150
 151 #define ALE_TYPE_FREE                   0
 152 #define ALE_TYPE_ADDR                   1
 153 #define ALE_TYPE_VLAN                   2
 154 #define ALE_TYPE_VLAN_ADDR              3
 155
 156 #define ALE_UCAST_PERSISTANT            0
 157 #define ALE_UCAST_UNTOUCHED             1
 158 #define ALE_UCAST_OUI                   2
 159 #define ALE_UCAST_TOUCHED               3
 160
 161 #define ALE_MCAST_FWD                   0
 162 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 163 #define ALE_MCAST_FWD_LEARN             2
 164 #define ALE_MCAST_FWD_2                 3
 165
 166 enum cpsw_ale_port_state {
 167         ALE_PORT_STATE_DISABLE  = 0x00,
 168         ALE_PORT_STATE_BLOCK    = 0x01,
 169         ALE_PORT_STATE_LEARN    = 0x02,
 170         ALE_PORT_STATE_FORWARD  = 0x03,
 171 };
 172
 173 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 174 #define ALE_SECURE      1
 175 #define ALE_BLOCKED     2
 176
 177 struct cpsw_slave {
 178         struct cpsw_slave_regs          *regs;
 179         struct cpsw_sliver_regs         *sliver;
 180         int                             slave_num;
 181         u32                             mac_control;
 182         struct cpsw_slave_data          *data;
 183 };
 184
 185 struct cpdma_desc {
 186         /* hardware fields */
 187         u32                     hw_next;
 188         u32                     hw_buffer;
 189         u32                     hw_len;
 190         u32                     hw_mode;
 191 } __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE)));
 192
 193 struct cpsw_desc {
 194         void *sw_buffer;
 195         struct cpsw_desc *next;
 196         struct cpdma_desc *dma_desc;
 197 };
 198
 199 struct cpdma_chan {
 200         struct cpsw_desc        *head, *tail;
 201         void                    *hdp, *cp, *rxfree;
 202 };
 203
 204 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->dma_desc->fld)
 205 #define desc_read(desc, fld)            __raw_readl(&(desc)->dma_desc->fld)
 206 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->dma_desc->fld))
 207
 208 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 209 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 210 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 211
 212 #define for_each_slave(slave, priv) \
 213         for (slave = (priv)->slaves; slave != (priv)->slaves + \
 214                                 (priv)->data->slaves; slave++)
 215
 216 struct cpsw_priv {
 217         struct eth_device               *dev;
 218         struct cpsw_platform_data       *data;
 219         int                             host_port;
 220
 221         struct cpsw_regs                *regs;
 222         void                            *dma_regs;
 223         struct cpsw_host_regs           *host_port_regs;
 224         void                            *ale_regs;
 225
 226         struct cpsw_desc                descs[NUM_DESCS];
 227         struct cpsw_desc                *desc_free;
 228         struct cpdma_chan               rx_chan, tx_chan;
 229
 230         struct cpsw_slave               *slaves;
 231         struct phy_device               *phydev;
 232         struct mii_dev                  *bus;
 233 };
 234
 235 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 236 {
 237         int idx;
 238
 239         idx    = start / 32;
 240         start -= idx * 32;
 241         idx    = 2 - idx; /* flip */
 242         return (ale_entry[idx] >> start) & BITMASK(bits);
 243 }
 244
 245 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 246                                       u32 value)
 247 {
 248         int idx;
 249
 250         value &= BITMASK(bits);
 251         idx    = start / 32;
 252         start -= idx * 32;
 253         idx    = 2 - idx; /* flip */
 254         ale_entry[idx] &= ~(BITMASK(bits) << start);
 255         ale_entry[idx] |=  (value << start);
 256 }
 257
 258 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 259 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
 260 {                                                                       \
 261         return cpsw_ale_get_field(ale_entry, start, bits);              \
 262 }                                                                       \
 263 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
 264 {                                                                       \
 265         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 266 }
 267
 268 DEFINE_ALE_FIELD(entry_type,            60,     2)
 269 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 270 DEFINE_ALE_FIELD(port_mask,             66,     3)
 271 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 272 DEFINE_ALE_FIELD(port_num,              66,     2)
 273 DEFINE_ALE_FIELD(blocked,               65,     1)
 274 DEFINE_ALE_FIELD(secure,                64,     1)
 275 DEFINE_ALE_FIELD(mcast,                 40,     1)
 276
 277 /* The MAC address field in the ALE entry cannot be macroized as above */
 278 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 279 {
 280         int i;
 281
 282         for (i = 0; i < 6; i++)
 283                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 284 }
 285
 286 static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
 287 {
 288         int i;
 289
 290         for (i = 0; i < 6; i++)
 291                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 292 }
 293
 294 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 295 {
 296         int i;
 297
 298         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 299
 300         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 301                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 302
 303         return idx;
 304 }
 305
 306 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 307 {
 308         int i;
 309
 310         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 311                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 312
 313         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 314
 315         return idx;
 316 }
 317
 318 static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
 319 {
 320         u32 ale_entry[ALE_ENTRY_WORDS];
 321         int type, idx;
 322
 323         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 324                 u8 entry_addr[6];
 325
 326                 cpsw_ale_read(priv, idx, ale_entry);
 327                 type = cpsw_ale_get_entry_type(ale_entry);
 328                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 329                         continue;
 330                 cpsw_ale_get_addr(ale_entry, entry_addr);
 331                 if (memcmp(entry_addr, addr, 6) == 0)
 332                         return idx;
 333         }
 334         return -ENOENT;
 335 }
 336
 337 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 338 {
 339         u32 ale_entry[ALE_ENTRY_WORDS];
 340         int type, idx;
 341
 342         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 343                 cpsw_ale_read(priv, idx, ale_entry);
 344                 type = cpsw_ale_get_entry_type(ale_entry);
 345                 if (type == ALE_TYPE_FREE)
 346                         return idx;
 347         }
 348         return -ENOENT;
 349 }
 350
 351 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 352 {
 353         u32 ale_entry[ALE_ENTRY_WORDS];
 354         int type, idx;
 355
 356         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 357                 cpsw_ale_read(priv, idx, ale_entry);
 358                 type = cpsw_ale_get_entry_type(ale_entry);
 359                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 360                         continue;
 361                 if (cpsw_ale_get_mcast(ale_entry))
 362                         continue;
 363                 type = cpsw_ale_get_ucast_type(ale_entry);
 364                 if (type != ALE_UCAST_PERSISTANT &&
 365                     type != ALE_UCAST_OUI)
 366                         return idx;
 367         }
 368         return -ENOENT;
 369 }
 370
 371 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
 372                               int port, int flags)
 373 {
 374         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 375         int idx;
 376
 377         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 378         cpsw_ale_set_addr(ale_entry, addr);
 379         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 380         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 381         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 382         cpsw_ale_set_port_num(ale_entry, port);
 383
 384         idx = cpsw_ale_match_addr(priv, addr);
 385         if (idx < 0)
 386                 idx = cpsw_ale_match_free(priv);
 387         if (idx < 0)
 388                 idx = cpsw_ale_find_ageable(priv);
 389         if (idx < 0)
 390                 return -ENOMEM;
 391
 392         cpsw_ale_write(priv, idx, ale_entry);
 393         return 0;
 394 }
 395
 396 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
 397 {
 398         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 399         int idx, mask;
 400
 401         idx = cpsw_ale_match_addr(priv, addr);
 402         if (idx >= 0)
 403                 cpsw_ale_read(priv, idx, ale_entry);
 404
 405         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 406         cpsw_ale_set_addr(ale_entry, addr);
 407         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 408
 409         mask = cpsw_ale_get_port_mask(ale_entry);
 410         port_mask |= mask;
 411         cpsw_ale_set_port_mask(ale_entry, port_mask);
 412
 413         if (idx < 0)
 414                 idx = cpsw_ale_match_free(priv);
 415         if (idx < 0)
 416                 idx = cpsw_ale_find_ageable(priv);
 417         if (idx < 0)
 418                 return -ENOMEM;
 419
 420         cpsw_ale_write(priv, idx, ale_entry);
 421         return 0;
 422 }
 423
 424 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 425 {
 426         u32 tmp, mask = BIT(bit);
 427
 428         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 429         tmp &= ~mask;
 430         tmp |= val ? mask : 0;
 431         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 432 }
 433
 434 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 435 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 436 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 437
 438 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 439                                        int val)
 440 {
 441         int offset = ALE_PORTCTL + 4 * port;
 442         u32 tmp, mask = 0x3;
 443
 444         tmp  = __raw_readl(priv->ale_regs + offset);
 445         tmp &= ~mask;
 446         tmp |= val & mask;
 447         __raw_writel(tmp, priv->ale_regs + offset);
 448 }
 449
 450 static struct cpsw_mdio_regs *mdio_regs;
 451
 452 /* wait until hardware is ready for another user access */
 453 static inline u32 wait_for_user_access(void)
 454 {
 455         int timeout = MDIO_TIMEOUT;
 456         u32 reg;
 457
 458         while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) {
 459                 udelay(1000);
 460                 if (--timeout <= 0) {
 461                         printf("TIMEOUT waiting for USERACCESS_GO\n");
 462                         return -1;
 463                 }
 464         }
 465
 466         return reg;
 467 }
 468
 469 /* wait until hardware state machine is idle */
 470 static inline void wait_for_idle(void)
 471 {
 472         int timeout = MDIO_TIMEOUT;
 473
 474         while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) {
 475                 if (--timeout <= 0) {
 476                         printf("TIMEOUT waiting for state machine idle\n");
 477                         break;
 478                 }
 479                 udelay(1000);
 480         }
 481 }
 482
 483 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
 484                                 int dev_addr, int phy_reg)
 485 {
 486         unsigned short data;
 487         u32 reg;
 488
 489         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 490                 return -EINVAL;
 491
 492         wait_for_user_access();
 493         reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
 494                (phy_id << 16));
 495         __raw_writel(reg, &mdio_regs->user[0].access);
 496         reg = wait_for_user_access();
 497
 498         data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
 499         return data;
 500 }
 501
 502 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
 503                                 int phy_reg, u16 data)
 504 {
 505         u32 reg;
 506
 507         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 508                 return -EINVAL;
 509
 510         wait_for_user_access();
 511         reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
 512                    (phy_id << 16) | (data & USERACCESS_DATA));
 513         __raw_writel(reg, &mdio_regs->user[0].access);
 514         wait_for_user_access();
 515
 516         return 0;
 517 }
 518
 519 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
 520 {
 521         struct mii_dev *bus = mdio_alloc();
 522
 523         mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
 524
 525         /* set enable and clock divider */
 526         __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
 527
 528         /*
 529          * wait for scan logic to settle:
 530          * the scan time consists of (a) a large fixed component, and (b) a
 531          * small component that varies with the mii bus frequency.  These
 532          * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
 533          * silicon.  Since the effect of (b) was found to be largely
 534          * negligible, we keep things simple here.
 535          */
 536         udelay(1000);
 537
 538         bus->read = cpsw_mdio_read;
 539         bus->write = cpsw_mdio_write;
 540         sprintf(bus->name, name);
 541
 542         mdio_register(bus);
 543 }
 544
 545 /* Set a self-clearing bit in a register, and wait for it to clear */
 546 static inline void setbit_and_wait_for_clear32(void *addr)
 547 {
 548         int loops = 0;
 549
 550         __raw_writel(CLEAR_BIT, addr);
 551         while (__raw_readl(addr) & CLEAR_BIT)
 552                 loops++;
 553         debug("%s: reset finished after %u loops\n", __func__, loops);
 554 }
 555
 556 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 557                          ((mac)[2] << 16) | ((mac)[3] << 24))
 558 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 559
 560 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 561                                struct cpsw_priv *priv)
 562 {
 563         __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
 564         __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
 565 }
 566
 567 #define NUM_TRIES 50
 568 static void cpsw_slave_update_link(struct cpsw_slave *slave,
 569                                    struct cpsw_priv *priv, int *link)
 570 {
 571         struct phy_device *phy = priv->phydev;
 572         u32 mac_control = 0;
 573         int retries = NUM_TRIES;
 574
 575         do {
 576                 phy_startup(phy);
 577                 *link = phy->link;
 578
 579                 if (*link) { /* link up */
 580                         mac_control = priv->data->mac_control;
 581                         if (phy->speed == 1000)
 582                                 mac_control |= GIGABITEN;
 583                         if (phy->duplex == DUPLEX_FULL)
 584                                 mac_control |= FULLDUPLEXEN;
 585                         if (phy->speed == 100)
 586                                 mac_control |= MIIEN;
 587                 } else {
 588                         udelay(10000);
 589                 }
 590         } while (!*link && retries-- > 0);
 591         debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
 592                 slave->mac_control, mac_control, NUM_TRIES - retries);
 593
 594         if (mac_control == slave->mac_control)
 595                 return;
 596
 597         if (mac_control) {
 598                 printf("link up on port %d, speed %d, %s duplex\n",
 599                                 slave->slave_num, phy->speed,
 600                                 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 601         } else {
 602                 printf("link down on port %d\n", slave->slave_num);
 603         }
 604
 605         __raw_writel(mac_control, &slave->sliver->mac_control);
 606         slave->mac_control = mac_control;
 607 }
 608
 609 static int cpsw_update_link(struct cpsw_priv *priv)
 610 {
 611         int link = 0;
 612         struct cpsw_slave *slave;
 613
 614         for_each_slave(slave, priv)
 615                 cpsw_slave_update_link(slave, priv, &link);
 616
 617         return link;
 618 }
 619
 620 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 621 {
 622         if (priv->host_port == 0)
 623                 return slave_num + 1;
 624         else
 625                 return slave_num;
 626 }
 627
 628 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 629 {
 630         u32     slave_port;
 631
 632         debug("%s\n", __func__);
 633         setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
 634
 635         /* setup priority mapping */
 636         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 637         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 638
 639         /* setup max packet size, and mac address */
 640         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 641         cpsw_set_slave_mac(slave, priv);
 642
 643         slave->mac_control = 0; /* no link yet */
 644
 645         /* enable forwarding */
 646         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 647         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 648
 649         cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
 650 }
 651
 652 static void cpdma_desc_get(struct cpsw_desc *desc)
 653 {
 654         invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
 655 }
 656
 657 static void cpdma_desc_put(struct cpsw_desc *desc)
 658 {
 659         flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
 660 }
 661
 662 static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 663 {
 664         struct cpsw_desc *desc = priv->desc_free;
 665
 666         if (desc) {
 667                 cpdma_desc_get(desc);
 668                 priv->desc_free = desc->next;
 669         }
 670         return desc;
 671 }
 672
 673 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpsw_desc *desc)
 674 {
 675         if (desc) {
 676                 desc_write(desc, hw_next, priv->desc_free->dma_desc);
 677                 cpdma_desc_put(desc);
 678                 desc->next = priv->desc_free;
 679                 priv->desc_free = desc;
 680         }
 681 }
 682
 683 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 684                         void *buffer, int len)
 685 {
 686         struct cpsw_desc *desc, *prev;
 687         u32 mode;
 688
 689         if (!buffer) {
 690                 printf("ERROR: %s() NULL buffer\n", __func__);
 691                 return -EINVAL;
 692         }
 693
 694         flush_dcache_range((u32)buffer, (u32)buffer + len);
 695
 696         desc = cpdma_desc_alloc(priv);
 697         if (!desc)
 698                 return -ENOMEM;
 699
 700         debug("%s@%d: %cX desc %p DMA %p\n", __func__, __LINE__,
 701                 chan == &priv->rx_chan ? 'R' : 'T', desc, desc->dma_desc);
 702         if (len < PKT_MIN)
 703                 len = PKT_MIN;
 704
 705         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 706
 707         desc->next = NULL;
 708         desc_write(desc, hw_next,   0);
 709         desc_write(desc, hw_buffer, buffer);
 710         desc_write(desc, hw_len,    len);
 711         desc_write(desc, hw_mode,   mode | len);
 712
 713         desc->sw_buffer = buffer;
 714
 715         cpdma_desc_put(desc);
 716         if (!chan->head) {
 717                 /* simple case - first packet enqueued */
 718                 chan->head = desc;
 719                 chan->tail = desc;
 720                 chan_write(chan, hdp, desc->dma_desc);
 721                 goto done;
 722         }
 723
 724         /* not the first packet - enqueue at the tail */
 725         prev = chan->tail;
 726
 727         prev->next = desc;
 728         cpdma_desc_get(prev);
 729         desc_write(prev, hw_next, desc->dma_desc);
 730         cpdma_desc_put(prev);
 731
 732         chan->tail = desc;
 733
 734         /* next check if EOQ has been triggered already */
 735         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 736                 chan_write(chan, hdp, desc->dma_desc);
 737
 738 done:
 739         if (chan->rxfree)
 740                 chan_write(chan, rxfree, 1);
 741         debug("%s@%d\n", __func__, __LINE__);
 742         return 0;
 743 }
 744
 745 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 746                          void **buffer, int *len)
 747 {
 748         struct cpsw_desc *desc = chan->head;
 749         u32 status;
 750
 751         if (!desc)
 752                 return -ENOENT;
 753
 754         cpdma_desc_get(desc);
 755
 756         status = desc_read(desc, hw_mode);
 757         if (status & CPDMA_DESC_OWNER)
 758                 return -EBUSY;
 759
 760         if (len)
 761                 *len = status & 0x7ff;
 762
 763         if (buffer)
 764                 *buffer = desc->sw_buffer;
 765         debug("%s@%d: buffer=%p\n", __func__, __LINE__, desc->sw_buffer);
 766
 767         chan->head = desc->next;
 768         chan_write(chan, cp, desc->dma_desc);
 769
 770         cpdma_desc_free(priv, desc);
 771         return 0;
 772 }
 773
 774 static int cpsw_init(struct eth_device *dev, bd_t *bis)
 775 {
 776         struct cpsw_priv        *priv = dev->priv;
 777         struct cpsw_slave       *slave;
 778         int i, ret;
 779
 780         debug("%s\n", __func__);
 781         /* soft reset the controller and initialize priv */
 782         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 783
 784         /* initialize and reset the address lookup engine */
 785         cpsw_ale_enable(priv, 1);
 786         cpsw_ale_clear(priv, 1);
 787         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 788
 789         /* setup host port priority mapping */
 790         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 791         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 792
 793         /* disable priority elevation and enable statistics on all ports */
 794         __raw_writel(0, &priv->regs->ptype);
 795
 796         /* enable statistics collection only on the host port */
 797         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 798
 799         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 800
 801         cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
 802                            ALE_SECURE);
 803         cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port);
 804
 805         for_each_slave(slave, priv)
 806                 cpsw_slave_init(slave, priv);
 807
 808         cpsw_update_link(priv);
 809
 810         /* init descriptor pool */
 811         for (i = 0; i < NUM_DESCS; i++) {
 812                 struct cpsw_desc *next_desc = (i < (NUM_DESCS - 1)) ?
 813                         &priv->descs[i + 1] : NULL;
 814
 815                 priv->descs[i].next = next_desc;
 816                 desc_write(&priv->descs[i], hw_next,
 817                         next_desc ? next_desc->dma_desc : 0);
 818                 cpdma_desc_put(&priv->descs[i]);
 819         }
 820         priv->desc_free = &priv->descs[0];
 821
 822         /* initialize channels */
 823         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 824                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 825                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 826                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 827                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 828
 829                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 830                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 831                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 832         } else {
 833                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 834                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 835                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 836                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 837
 838                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 839                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 840                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 841         }
 842
 843         /* clear dma state */
 844         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 845
 846         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 847                 for (i = 0; i < priv->data->channels; i++) {
 848                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i);
 849                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
 850                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i);
 851                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i);
 852                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i);
 853                 }
 854         } else {
 855                 for (i = 0; i < priv->data->channels; i++) {
 856                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i);
 857                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
 858                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i);
 859                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i);
 860                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i);
 861
 862                 }
 863         }
 864
 865         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 866         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 867
 868         /* submit rx descs */
 869         for (i = 0; i < PKTBUFSRX; i++) {
 870                 ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
 871                                    PKTSIZE);
 872                 if (ret < 0) {
 873                         printf("error %d submitting rx desc\n", ret);
 874                         break;
 875                 }
 876         }
 877
 878         return ret;
 879 }
 880
 881 static void cpsw_halt(struct eth_device *dev)
 882 {
 883         struct cpsw_priv        *priv = dev->priv;
 884
 885         writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 886         writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 887
 888         /* soft reset the controller and initialize priv */
 889         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 890
 891         /* clear dma state */
 892         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 893
 894         debug("%s\n", __func__);
 895         priv->data->control(0);
 896 }
 897
 898 static int cpsw_send(struct eth_device *dev, void *packet, int length)
 899 {
 900         struct cpsw_priv *priv = dev->priv;
 901         void *buffer;
 902         int len;
 903
 904         debug("%s@%d: sending packet %p..%p\n", __func__, __LINE__,
 905                 packet, packet + length - 1);
 906
 907         if (!priv->data->mac_control && !cpsw_update_link(priv)) {
 908                 printf("%s: Cannot send packet; link is down\n", __func__);
 909                 return -EIO;
 910         }
 911
 912         /* first reap completed packets */
 913         while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
 914                 /* NOP */;
 915
 916         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 917 }
 918
 919 static int cpsw_recv(struct eth_device *dev)
 920 {
 921         struct cpsw_priv        *priv = dev->priv;
 922         void *buffer;
 923         int len;
 924
 925         while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) {
 926                 if (buffer) {
 927                         NetReceive(buffer, len);
 928                         cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
 929                 } else {
 930                         printf("NULL buffer returned from cpdma_process\n");
 931                         return -EIO;
 932                 }
 933         }
 934
 935         return 0;
 936 }
 937
 938 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 939                             struct cpsw_priv *priv)
 940 {
 941         void                    *regs = priv->regs;
 942         struct cpsw_slave_data  *data = priv->data->slave_data + slave_num;
 943
 944         debug("%s@%d: slave[%d] %p\n", __func__, __LINE__,
 945                 slave_num, slave);
 946         slave->slave_num = slave_num;
 947         slave->data     = data;
 948         slave->regs     = regs + data->slave_reg_ofs;
 949         slave->sliver   = regs + data->sliver_reg_ofs;
 950 }
 951
 952 static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
 953 {
 954         struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
 955         struct phy_device *phydev;
 956         u32 supported = (SUPPORTED_10baseT_Half |
 957                         SUPPORTED_10baseT_Full |
 958                         SUPPORTED_100baseT_Half |
 959                         SUPPORTED_100baseT_Full |
 960                         SUPPORTED_1000baseT_Full);
 961
 962         phydev = phy_connect(priv->bus,
 963                         CONFIG_PHY_ADDR,
 964                         dev,
 965                         slave->data->phy_if);
 966
 967         phydev->supported &= supported;
 968         phydev->advertising = phydev->supported;
 969
 970         priv->phydev = phydev;
 971         phy_config(phydev);
 972
 973         return 1;
 974 }
 975
 976 int cpsw_register(struct cpsw_platform_data *data)
 977 {
 978         struct cpsw_priv        *priv;
 979         struct cpsw_slave       *slave;
 980         void                    *regs = (void *)data->cpsw_base;
 981         struct eth_device       *dev;
 982         int i;
 983         int idx = 0;
 984
 985         debug("%s@%d\n", __func__, __LINE__);
 986
 987         dev = calloc(sizeof(*dev), 1);
 988         if (!dev)
 989                 return -ENOMEM;
 990
 991         priv = calloc(sizeof(*priv), 1);
 992         if (!priv) {
 993                 free(dev);
 994                 return -ENOMEM;
 995         }
 996
 997         priv->data = data;
 998         priv->dev = dev;
 999
1000         priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves);
1001         if (!priv->slaves) {
1002                 free(dev);
1003                 free(priv);
1004                 return -ENOMEM;
1005         }
1006
1007         for (i = 0; i < NUM_DESCS; i++) {
1008                 priv->descs[i].dma_desc = memalign(CONFIG_SYS_CACHELINE_SIZE,
1009                                 sizeof(struct cpsw_desc) * NUM_DESCS);
1010                 if (!priv->descs[i].dma_desc) {
1011                         while (--i >= 0) {
1012                                 free(priv->descs[i].dma_desc);
1013                         }
1014                         free(priv->slaves);
1015                         free(priv);
1016                         free(dev);
1017                         return -ENOMEM;
1018                 }
1019                 debug("DMA desc[%d] allocated @ %p desc_size %u\n",
1020                         i, priv->descs[i].dma_desc,
1021                         sizeof(*priv->descs[i].dma_desc));
1022         }
1023
1024         priv->host_port         = data->host_port_num;
1025         priv->regs              = regs;
1026         priv->host_port_regs    = regs + data->host_port_reg_ofs;
1027         priv->dma_regs          = regs + data->cpdma_reg_ofs;
1028         priv->ale_regs          = regs + data->ale_reg_ofs;
1029
1030         for_each_slave(slave, priv) {
1031                 cpsw_slave_setup(slave, idx, priv);
1032                 idx = idx + 1;
1033         }
1034
1035         strcpy(dev->name, "cpsw");
1036         dev->iobase     = 0;
1037         dev->init       = cpsw_init;
1038         dev->halt       = cpsw_halt;
1039         dev->send       = cpsw_send;
1040         dev->recv       = cpsw_recv;
1041         dev->priv       = priv;
1042
1043         eth_register(dev);
1044
1045         cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
1046         priv->bus = miiphy_get_dev_by_name(dev->name);
1047         for_each_slave(slave, priv)
1048                 cpsw_phy_init(dev, slave);
1049
1050         return 1;
1051 }